JPH05328224A - Amplification type solid-state image pickup device - Google Patents

Abstract

PURPOSE:To provide the amplification type solid-state image pickup device provided with an output section giving an output at a high speed apparently even when the operating speed of output transistors (TRs) is slow in which the number of output TRs connecting to one horizontal signal line is reduced and the number of output pins is reduced. CONSTITUTION:Four picture elements of one horizontal line are used for one block and signals of each picture element are read to four horizontal signal lines 5-1-5-4 in the unit of blocks and the signals are read to the 1st and 3rd horizontal signal lines 5-1 and 5-3 and to the 2nd and 4th horizontal signal lines 5-2 and 5-4 while the phases are shifted, and each signal read on the 1st and 2nd horizontal signal lines 5-1, 5-2 is used for an output signal OUT1 in time division and each signal read on the 3rd and 4th horizontal signal lines 5-3, 5-4 is used for an output signal OUT2 in time division by using changeover switches SW1, SW2 to realize 4-line read 2-output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplification type solid-state image pickup device, and more particularly to a structure of an output section of the amplification type solid-state image pickup device.

[0002]

2. Description of the Related Art In a solid-state image pickup device, the charge accumulated in each pixel of an image sensor section is directly transferred to a CCD (Charge Coupling).
CCD that transfers horizontally and vertically by a led device) and finally converts it into an electric signal and outputs it as an image signal.
In addition to the solid-state image pickup device, a MOS solid-state image pickup device that amplifies the charge accumulated in each pixel as an electric signal in the pixel and then reads out to a vertical signal line and a horizontal signal line to output as an image signal is represented. There is an amplification type solid-state imaging device.

An example of the structure of this amplification type solid-state image pickup device is shown in FIG. In FIG. 3, for example, a photo sensor and a MOS
A plurality of pixels 1 formed by a combination of transistors
The image sensor unit 2 is formed by two-dimensionally arranging (indicated as a symbol with a circle in the drawing and omitting a specific configuration) in a matrix in the horizontal and vertical directions. The vertical shift register 3, which is a horizontal scanning circuit, performs vertical scanning for sequentially selecting one of the horizontal lines formed of a pixel row in the horizontal direction and reading a signal from each pixel of the selected horizontal line to the vertical signal line 4. It is a circuit, and only the bit of the horizontal line to be selected is set to "1" and all the other bits are set to "0". Then, every 1H (H: horizontal scanning period), the bit that becomes "1" is shifted in the vertical direction.

A gate MOS transistor Q1 is connected between the node N1 which is the output point of the vertical signal line 4 and the power supply V _DD , and a load MOS transistor Q2 is connected between the node N1 and the ground. .. The gate MOS transistor Q1 receives the signal φ _S as a gate input, and permits signal transmission when the signal φ _S is applied. M for load
The OS transistor Q2 receives the bias voltage V _GG as a gate input. The signal of each pixel output to the vertical signal line 4 and allowed to be transmitted by the gate MOS transistor Q1 is stored in the noise removing capacitor C _C.

A clamp MOS transistor Q3 is connected to a node N2 which is an output terminal of the noise removing capacitor C _C , and a clamp pulse φ _clp is applied to the gate electrode of the clamp MOS transistor Q3. This turns on and clamps the node N2 to a predetermined clamp voltage V _clp . By the noise removing capacitor C _C and the clamping MOS transistor Q3, correlated double sampling (CD is performed for suppressing noise such as reset noise included in the signal of each pixel.
S) circuit is configured.

FIG. 5 shows the configuration of a conventional example of an output section in this amplification type solid-state image pickup device. In FIG. 5, the output of the noise removing capacitor C _C passes through a buffer amplifier (not shown), and then the switching MOS transistors Q4 and Q5.
Are alternately supplied to the sample / hold capacitors C1 and C2, and are sampled / held by these capacitors C1 and C2. The switching MOS transistors Q4, Q5 are controlled by controlling the sample / hold signals SH1, S generated during the horizontal blanking period.
H2 is performed line by line. As a result, for example, the signal of each pixel on the even line is held in the capacitor C1 and the signal of each pixel on the odd line is held in the capacitor C2.

Here, in this conventional example, four pixels of each pixel of one horizontal line are regarded as one block, and the signal of each pixel is read out to the four horizontal signal lines 5 _{-1 to} 5 _-4 in block units. , A so-called 4-wire read-out 4-output configuration is adopted. As a result, the hold outputs of the sample / hold capacitors C1 and C2 for four pixels are switched by the horizontal gate MOS transistors Q6 and Q7 to the horizontal signal line 5 via the output transistor Q9 of the source follower.
It is output to _{-1 to} 5 _-4 .

Horizontal gate MOS transistors Q6, Q
The switching control of 7 is performed by the horizontal scanning clock φ _n-1 output from the horizontal shift register 6 which is a horizontal scanning circuit. The horizontal clock φ _H is supplied to the horizontal shift register 6 via the logic gate 7.
Further, the sample / hold capacitors C1 and C2 are
It is reset by the reset MOS transistor Q8 whose gate input is the horizontal scanning clock φ _n output from the horizontal shift register 6. 4 horizontal signal lines 5 _-1 ~
A load MOS transistor Q1 is connected between each of 5 _-4 and ground.
0 _{-1 to} Q10 _-4 are connected to each other, and a bias voltage V _GG is applied to the base electrodes of these load MOS transistors Q10 _{-1 to} Q10 _-4 .

[0009]

However, the conventional output section of the 4-wire read-out 4-output constructed as above has the following problem.
Although the operating speed of the output transistor Q9 is 1/4 as compared with the case of 1-line read-out 1 output, 4
There is a drawback in that the number of output pins is increased because four output pins are required for each output.

On the other hand, in order to reduce the number of output pins to, for example, 2 pins, it is sufficient to adopt a configuration of two-line read-out two-output, but in the case of two-line read-out two-output, the output transistor Q
This means that the operating speed of 9 must be doubled with respect to the 4-wire read 4 output, and each output transistor Q9 must be able to derive a stable output during the time Δt of one cycle. FIG. 4 shows a time chart in the case of 2-line reading and 2-output.

By the way, the capacitance of the horizontal signal line is C _Al , the source-gate capacitance of each output transistor Q9 is C _sg , and the source coupling capacitance is C _j , the number of transistors connected to one horizontal signal line is Assuming N, the load capacitance C _H per output line is

## EQU1 ## C _H = C _Al + N (C _sg + C _j ) and the mutual conductance g of the output transistor Q9
_The time constant τ for _m is

## EQU2 ## τ = C _H / g _m = C _Al / g _m + N {(C _sg / g _m ) + (C _j / g _m )}. In this equation, the second term does not become smaller no matter how large the channel width W of the transistor is made. Therefore, it is also necessary to reduce the number N of output transistors Q9 connected to one horizontal signal line by performing multi-line reading.

The present invention has been made in view of the above-mentioned points, and can reduce the number of output transistors connected to one horizontal signal line and the number of output pins.
It is an object of the present invention to provide an amplification type solid-state imaging device including an output section that can derive an output at an apparently high speed even if the operation speed of an output transistor is slow.

[0013]

An amplification type solid-state image pickup device according to the present invention includes an image sensor section in which a plurality of pixels are two-dimensionally arranged in a matrix in the horizontal and vertical directions, and each horizontal line of the image sensor section. A vertical scanning circuit that sequentially selects one and reads out a signal from each pixel of the selected horizontal line, and n blocks of each pixel of one horizontal line selected by this vertical scanning circuit as one block A configuration including a horizontal scanning circuit that reads out the signal of each pixel to n horizontal signal lines and an output circuit that outputs each signal read out to the n horizontal signal lines in combination of two predetermined signals Is becoming

[0014]

In each pixel of one horizontal line, for example, four pixels are set as one block, and the signal of each pixel is set to 4 in block units.
Four lines are read out and two outputs are realized by reading out on a horizontal signal line of a book and combining each of the read out signals by two predetermined signals to derive two outputs.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention. For example, four pixels of each pixel on one horizontal line are regarded as one block, and signals of each pixel are supplied in units of blocks to four horizontal signal lines 5. _{-1 to} 5 _-4 shows the case of applying to the 4-wire read. In FIG. 1, the horizontal shift register 6
Is the signal of each pixel on a block-by-block basis by the four horizontal signal lines 5
When reading to _{-1 to} 5 _-4 , the horizontal scanning clock φ is used to read signals to the first and third horizontal signal lines 5 _-1 and 5 _-3 .
_{In accordance with n} (φ _n-2 , φ _{n + 2} ), the horizontal scanning clock φ _{n + 1} is used to read out signals to the second and fourth horizontal signal lines 5 _-2 and 5 _-4 .
(Φ _n-1 , φ _{n + 3} ) respectively. That is, the reading of signals to the first and third horizontal signal lines 5 _-1 , 5 _-3 and the second and fourth horizontal signal lines 5 _-2 , 5 _-4 is performed with a phase shift. ..

Load MOS transistors Q10 _{-1 to} Q1
In the latter stage of 0 _-4 , the first and second horizontal signal lines 5 _-1 , 5
_A switch SW1 composed of a pair of C-MOS for selectively outputting each signal on both signal lines is provided between both ends of _-2 , and similarly, the third and fourth horizontal signal lines 5 _-3 , 5 _A switch SW consisting of a pair of C-MOS between both ends of _-4
Two are provided. The changeover switch SW1 is the first,
The second horizontal signal lines 5 _-1 , 5 _-2 are paired to derive each signal read out to both signal lines as an output signal OUT1 in a time-division manner, and the changeover switch SW2 is provided with a third switch and a fourth switch. The horizontal signal lines 5 _-3 and 5 _-4 are paired to derive each signal read out on both signal lines as an output signal OUT2 in a time division manner.

Next, the operation of the 4-wire read 2 output having the above-mentioned structure will be described with reference to the time chart of FIG.
As the horizontal clock φ _H of the horizontal shift register 6, a clock having the same cycle as in the case of 2-line reading and 2-output (see FIG. 4) is used. Now, when two high level data are input to the horizontal shift register 6, each horizontal scanning clock φ _n becomes high level for 2 clock (φ _H ) periods. Then, the signals are read out to the first and third horizontal signal lines 5 _-1 , 5 _-3 by the horizontal scanning clock φ _n (φ _n-2 , φ _{n + 2} ). The reading of the signals to the lines 5 _-2 and 5 _-4 is performed by the horizontal scanning clock φ _{n + 1} (φ _n-1 , φ _{n + 3} ).

Further, the changeover switches SW1 and SW2 are
By performing switching control by the clock φ _S and its inverted clock, the first and second horizontal signal lines 5 _-1 , 5
_-2 , each signal read out is output signal OUT1 in a time division manner
As a result, the signals read out to the third and fourth horizontal signal lines 5 _-3 and 5 _-4 are time-divisionally derived as the output signal OUT2. In the switching control by the changeover switches SW1 and SW2, as is apparent from the waveforms of OUT1 and OUT2 in FIG. 2, if the stable one of the signals is output by the clock φ _S and its inverted clock, the output The operating speed of the transistor Q9 can be covered.

As described above, among the pixels of one horizontal line, for example, four pixels are set as one block and the signal of each pixel is read out to the four horizontal signal lines 5 _{-1 to} 5 _-4 in block units. , The first and third horizontal signal lines 5 _-1 , 5 _-3 and the second and fourth horizontal signal lines 5 _-2 , 5 _-4 are read out of phase, while the changeover switch SW1 , SW2
The respective signals read out to the first and second horizontal signal lines 5 _-1 , 5 _-2 by means of time division are used as the output signal OUT1 to output the third and fourth horizontal signal lines 5 _-3 , 5 _-4. By deriving each of the signals read out as the output signal OUT2 in a time-division manner, it is possible to realize the 4-wire read out 2 output, so that the number of output pins can be reduced and the operating speed of the output transistor Q9 is slow. Output signal OUT at high speed apparently
1 and OUT2 can be derived.

In the above embodiment, the case where the 4-line reading and the 2-output are used has been described. However, the 4-line reading and the 1-output can be realized by further deriving the 2-output in a time division manner. Further, among the pixels of one horizontal line, for example, eight pixels are set as one block and the signal of each pixel is read in block units, so that four-output, two-output, and one-output are possible by 8-line reading. Become. in this way,
By performing multi-line reading, the number of output transistors Q9 connected to one horizontal signal line can be reduced, and as a result, the second term of the equation of the equation 2 can be reduced.

[0021]

As described above, according to the present invention,
Of the pixels of one horizontal line, n pixels are set as one block, and the signal of each pixel is read in a block unit into n horizontal signal lines, and each signal read out in the n horizontal signal lines is predetermined. By combining and outputting two signals each, the number of outputs can be smaller than the number of horizontal signal lines, so the number of output transistors connected to one horizontal signal line can be reduced and the number of output pins can be reduced. Moreover, even if the operating speed of the output transistor is slow, the output can be derived at an apparently high speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a time chart in the case of 4-line reading 2-output.

FIG. 3 is a configuration diagram of an example of an amplification type solid-state imaging device.

FIG. 4 is a time chart in the case of 2-line reading and 2-output.

FIG. 5 is a circuit diagram showing a conventional example of 4-line reading and 4-output.

[Explanation of symbols]

2 Image sensor section 3 Vertical shift register 5 _{-1 to} 5 _-4 Horizontal signal line 6 Horizontal shift register SW1, SW2 Changeover switch Q4, Q5 Switching MOS transistor Q6, Q7 Horizontal gate MOS transistor Q9 Output transistor Q10 _{-1 to} Q10 _-4 Load transistor C1, C2 Sample / hold capacitor

Claims (6)

[Claims] 1. An image sensor unit in which a plurality of pixels are two-dimensionally arranged in a matrix in the horizontal and vertical directions, and one of the horizontal lines of the image sensor unit is sequentially selected while each of the selected horizontal lines is selected. A vertical scanning circuit for reading a signal from a pixel, and n pixels of each pixel of one horizontal line selected by the vertical scanning circuit as one block, and a signal of each pixel is read out to n horizontal signal lines in block units. The horizontal scanning circuit and each of the signals read out on the n horizontal signal lines are set to a predetermined number of 2
An amplification type solid-state imaging device, comprising: an output circuit that outputs signals in combination. 2. n = 4, and the output circuit combines each of the signals read to the four horizontal signal lines by a predetermined two signals to derive two output signals. Item 2. The amplification type solid-state imaging device according to item 1. 3. The horizontal scanning circuit phase-shifts each signal read to the first and third horizontal signal lines and each signal read to the second and fourth horizontal signal lines of the four horizontal signal lines. The output circuit combines the respective signals read to the first and second horizontal signal lines to derive a first output signal, and reads it to the third and fourth horizontal signal lines. 3. The amplification type solid-state imaging device according to claim 2, wherein the respective output signals are combined to derive a second output signal. 4. The output circuit comprises switch means for switching between the first and second horizontal signal lines, and the signals read out to the respective horizontal signal lines by the switch means are time-divided into the first signal. The amplification type solid-state imaging device according to claim 3, wherein the amplification type solid-state imaging device is derived as an output signal of 5. The output circuit includes switch means for switching between the third and fourth horizontal signal lines, and the signals read out to the respective horizontal signal lines by the switch means are time-divided into the second signal. The amplification type solid-state imaging device according to claim 3, wherein the amplification type solid-state imaging device is derived as an output signal of 6. When n = 8, the output circuit derives four, two or one output signals by sequentially combining the respective signals read out on the eight horizontal signal lines by predetermined two signals each. The amplification type solid-state imaging device according to claim 1.