JPH05326552A - Semiconductor element and its manufacture - Google Patents

Abstract

PURPOSE:To solve the problem that, when the size of an element is reduced, the junction depth of source-drain mainly becomes shallow, the interval from the bottom surface of the layer of the surface to be silicide-formed to a junction becomes short, and junction leak current is generated, regarding the structure and the manufacturing method of a field effect transistor (MOS FET mainly concerned) in a semiconductor element. CONSTITUTION:A first side wall 6 and a second side wall 8 are formed on the side wall of a gate electrode 4; a shallow source.drain layer 5a is formed by applying a main part of the first side wall 6 to a mask; a deep source.drain layer 5b is formed by applying the second side wall 8 to a mask; a silicide layer 9 is formed at least on the deep layer 8. It depends on the requirement of device formation whether a silicide layer 9 is formed also on the gate electrode 4. The order of formation of the shallow source.drain layer and the deep source.drain layer is different according to the manufacturing method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a FET portion of a CMOS device having a field effect transistor (mainly MOSFET) among semiconductor elements.

[0002]

2. Description of the Related Art As the miniaturization of semiconductor devices progresses and the MOSFETs shrink in size, the gate length becomes shorter, and in order to suppress the short channel effect, the junction depth of the source / drain regions (Xj ) Has to be shallow. The gate length is shortened, the on-resistance of the MOSFET is lowered, and on the other hand, Xj is shallow, so that the sheet resistance of the source / drain is increased. Therefore, in a MOSFET with a gate length in the submicron region, the sheet resistance of the source / drain cannot be ignored with respect to the on-resistance of the MOSFET, and the driving force of the MOSFET decreases due to the parasitic resistance of the source / drain region. It will be noticeable.

To solve the above problem, there is a salicide process in which the source / drain and the gate are silicided by self-alignment to reduce the sheet resistance. 11
Shows the salicide process that has been used in the past. Note that this figure is an example of a CMOS device, and therefore, as is well known, the Pch MOSFET region (the right half of the figure).
And an Nch MOSFET region (the left half of the figure) are formed.

First, as shown in FIG. 11A, an N-type impurity (phosphorus or the like) is formed on a part of the P-type Si substrate 1 by using ordinary photolithography (hereinafter abbreviated as photolithography) etching and ion implantation. ) Is introduced to form the N well region 2. Next, normal LOCOS (Local Oxida)
The field oxide film 3 is formed by the method of silicon of silicon. A gate oxide film 4 is formed on the surface of the Si substrate 1 by thermal oxidation, and a polysilicon 5 to be a gate electrode is deposited on the entire surface, and the gate electrode is patterned by using a normal photolithographic etching technique. By a normal photolithography process, the Pch MOSFET formation region is covered with the photoresist 6, and the entire surface is LDD (Lightly).
30 to 50 keV, 1 to 4 × 10 ¹³ ions of phosphorus or arsenic to be the doped drain) layer (N ⁻ layer) 7
/ Cm ² Ion implantation method allows NchM
The N ⁻ layer 7 is formed only in the OSFET region.

After that, as shown in FIG. 11 (b), C is formed on the entire surface.
An oxide film or an oxide film containing boron, phosphorus, etc. is deposited by the VD (chemical vapor deposition) method, and RIE (React
The sidewalls 8 are left on the sidewalls of the gate electrode 5 by performing anisotropic etching by the ive Ion Etching method. Thereafter, similarly to the above, the Pch MOSFET side and the Nch MOSFET side are covered with photoresist, respectively, and the arsenic (N
⁺ Layer) and boron (P ⁺ layer).

Thereafter, as shown in FIG.
After heat treatment at 1000 ° C. is performed to activate the impurities in the source / drain portions, refractory metal 9 is deposited. After that, as shown in FIG.
When subjected to heat treatment at ℃, refractory metal 9 and Poly-Si
A silicidation reaction occurs between Si and Si, and the gate electrode 5 and the source / drain portion (7) are self-aligned.
Then, the silicide 10 of the refractory metal 9 is formed. Thereafter, as shown in FIG. 11E, the salicide structure is completed by removing the unreacted refractory metal 11.

On the other hand, there are various proposals for a shallow junction forming method. In particular, in the case of a Pch MOSFET, since the source / drain impurity is boron, channeling occurs during ion implantation, the impurity distribution draws a tail, and the formed junction becomes deeper. Further, boron is a common impurity in silicon. The diffusion coefficient is large, and during activation annealing, it diffuses deeply and the junction becomes deep. For the above two items, a method of preventing channeling by implanting silicon, germanium or the like before the impurity implantation to make the silicon crystal amorphous and then implanting boron is considered. Further, due to short-time heat treatment, reduction of acceleration energy in implantation, and the like, attempts have been made to prevent deep diffusion even if the number of diffusion systems is large.

[0008]

However, in the above-described conventional salicide process, the source / drain junction depth (Xj) becomes shallow to suppress the short channel effect due to the miniaturization of the element, and the silicidation is achieved. There is a problem in that the distance between the bottom surface of the layer and the junction becomes short (see FIG. 12) and a junction leak current occurs.

Regarding the shallow junction formation, the method of preamorphization using silicon or germanium complicates the process, and there is a problem that residual defects are inevitably left by the subsequent heat treatment and the junction leak current increases. is there. Even in the short-time heat treatment and the implantation with the low acceleration energy, the junction depth to be formed is not shallow and has a limit.

It is difficult to perform the above two items (salicide and shallow junction) at the same time. As the miniaturization of MOSFET progresses in the future, the junction depth of the source / drain region must be shallow to suppress the short channel effect, and the parasitic resistance of the source / drain should be kept below a certain value. Then, the silicide on the source / drain regions due to salicide must be formed with a thickness of a certain value or more, and in order to realize both of them at the same time in the future, the problem of increased junction leakage current will be unavoidable.

As described above, the present invention provides a fine MOS.
In the FET, in order to suppress the short channel effect, the junction depth of the source / drain region is made shallower than before, and further, the parasitic resistance of the source / drain region is increased by the MOSFET.
The source / drain regions have a sufficiently low resistance so as not to deteriorate the performance of the device and the junction leakage current is not increased, and the contradictory technical items (salicide and shallow junction) described above are realized at the same time. It is an object of the present invention to provide a semiconductor device having excellent performance and a manufacturing method thereof.

Further, in manufacturing the CMOS type semiconductor device according to the present invention, even in the Pch region of the CMOS portion, even if the shallow junction is formed, the gate offset does not occur, and the variation of the driving current does not increase. It is another object of the present invention to provide a method for manufacturing a semiconductor device, which does not complicate the manufacturing process.

[0013]

In order to achieve the above object, the present invention is a MOSFET for self-aligning the source / drain regions as a first to fourth embodiments.
In, the sidewall formation is performed twice,
The source / drain layer having a shallow junction depth (Xj) is formed by the first sidewall, and the source / drain layer having a deep junction depth is formed by the second sidewall. After that, the upper surfaces of the source / drain layers are silicided by self-alignment.

Further, as a fifth and a sixth embodiment, in the method of manufacturing a semiconductor device, the dose of the impurity implanted into the source / drain regions is set so that the driving force is not lowered and the junction depth is shallow. Set to a certain range, inject, and perform salicide in a region slightly away from the gate that is not related to the short channel effect of MOSFET.
The resistance of the source / drain region is reduced, and deep impurity implantation for forming the source / drain is performed only in the salicided region so as to prevent a junction leak current.

In manufacturing the CMOS by the above method, the source / drain regions in the Pch region are not separated from the gate electrode (offset does not occur) before forming the side wall, and the dose is lower than before. The source / drain impurities are implanted.
Furthermore, the CMOS drain formation including the LDD layer formation can be made as small as the mask step 2 layer.

[0016]

As described above, in the first to fourth embodiments of the present invention, the shallow N ⁺ layer formed by using the first sidewall as a mask causes the short channel effect which is a problem in a fine MOSFET. Can be suppressed, and only on the deep N ⁺ layer formed using the second sidewall as a mask,
Since the silicide is formed, a sufficient distance can be provided between the bottom surface of the silicide and the junction, and it becomes possible to form a good junction in which no junction leakage current occurs.

In the fifth and sixth embodiments, the source
The implantation dose for drain formation makes the junction depth sufficiently shallow,
Moreover, since the control is performed within a range that does not reduce the driving force, it is possible to realize a MOSFET having a sufficiently short channel effect and a high driving force even in a fine MOSFET. Furthermore, the source / drain is salicided outside the relatively wide sidewall, and the junction is deep only in that region, so the increase in junction leakage current is suppressed without increasing the short channel effect of the transistor. it can. Moreover, the source / drain implantation is performed at a relatively low dose, and the increase in the sheet resistance of the source / drain is suppressed by salicide to realize a sufficiently low resistance. Moreover, in the step of reacting silicon with the refractory metal (silicidation step), the impurity concentration in the silicon is not as high as in the conventional case, so that the silicidation step can be performed stably with good reproducibility.

In manufacturing a CMOS, Pch source / drain (low dose compared to the prior art) impurity implantation is performed before the formation of a narrow side wall to prevent an offset while making the junction shallow and to prevent MO fluctuation.
A SFET can be realized.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the first embodiment of the present invention is shown in FIG. 1 and the manufacturing method thereof is shown in FIG. This embodiment is an NMOS-FE in which Ti (titanium) is a refractory metal.
This is the case of the T structure.

As shown in FIG. 1, in this embodiment, the gate electrode 4 is formed in the element forming region separated by the field oxide film 2 similar to the conventional one, and the side wall of the gate electrode 4 is the first feature of the present invention. The side wall 6 and the second side wall 8 are formed on the side surface of the side wall 6. The source / drain layer has a shallow layer 5a formed by using the first sidewall 6 as a mask and a deep layer 5b formed by using the second sidewall 8 as a mask. Then, titanium silicide 9 is formed on the deep layer 5b and on the gate electrode 4. That is, it has a salicide structure.

FIG. 2 shows the manufacturing method thereof. First, as shown in FIG. 2A, a field oxide film 2 for element isolation is formed on a P-type Si substrate 1 in a thickness of about 5000 Å (hereinafter Gate electrode 4 including a gate oxide film 3 (about 150Å) formed in the element formation region.
(About 3000 Å of polysilicon) is formed, and P ^{+ is set} to 30 in order to form the N ⁻ layer 5c serving as the source / drain layer.
Ion implantation (hereinafter abbreviated as ion implantation) is performed under the conditions of keV and 2 × 10 ¹³ / cm ² .

After that, the first sidewalls 6 are formed on the sidewalls of the gate electrode 4 by a usual method (such as a method of depositing an oxide film and performing anisotropic etching) to a thickness of about 1500 Å. Then, by using this as a mask and ion-implanting As (arsenic) in the source / drain regions under the conditions of 5 × 10 ¹⁵ / cm ² and 40 keV, the shallow layer 5a is formed.

After that, the oxide film 7 is formed on the entire surface by the CVD method.
About 3000 Å is deposited. Next, as shown in FIG.
The oxide film 7 is etched by anisotropic etching, and the second
The sidewall 8 of about 3000 Å is formed. afterwards,
When P ⁺ (phosphorus) is implanted under the conditions of 80 keV and 1 × 10 ¹⁵ / cm ^{2 using} the ^second sidewall 8 as a mask, deep layers 5b are formed in the source / drain regions. Further, it is annealed at 900 ° C. for about 20 minutes in a nitrogen atmosphere to activate and diffuse the implanted impurities. Under the above conditions, the N ⁻ layer 5c is used as the source / drain layer.
Has a junction depth of about 0.2 μm, the arsenic N ⁺ layer 5a has a junction depth of about 0.2 μm, and the phosphorus N ⁺ layer 5b has a junction depth of about 0.4 μm.

Next, as shown in FIG. 2 (c), titanium (Ti) 9a is deposited on the entire surface by sputtering to about 500 Å. Then, as shown in FIG. 2D, annealing is performed in a nitrogen atmosphere at 700 ° C. for about 10 seconds, and silicidation is performed on the portion where the Si layer and Ti of the gate electrode 4 and the source / drain regions are in contact, that is, on the deep layer 5b. Cause a reaction. Then, the unreacted Ti on the field oxide film 2 and the sidewalls 6 and 8 is selectively removed by etching by selective etching (ammonia hydrogen peroxide, etc.). Further, the resistance of titanium silicide 9 is reduced by annealing at 900 ° C. for about 10 seconds. Thereafter, although not shown, an intermediate insulating film is deposited, contact holes are opened, a wiring layer is formed, and finally a protective film is formed, as in the conventional case.

FIG. 3 shows a second embodiment of the present invention. When a deep source / drain layer is formed, the gate electrode is prevented from penetrating during ion implantation.

First, as shown in FIG. 3 (a), after forming the field oxide film 2, the gate oxide film 3 is formed, the polysilicon 4 is deposited thereon, and the oxide film 10 is further deposited to 2000 Å by the CVD method. Deposit to a degree. Next, as shown in FIG. 3B, the gate electrode 4 composed of the oxide film 3 / polysilicon 4 / gate oxide film 10 is patterned by photolithography etching. Thereafter, similarly to the manufacturing method of the first embodiment, the first sidewall 6 and the second sidewall 8 are formed, and the shallow N ⁺ source / drain layer 5a,
A deep N ⁺ source / drain layer 5b is formed and silicidation is performed. In this case, only the source / drain layers are silicidized. That is, deep N ⁺ source / drain layer 5
In the ion implantation for forming b, since the gate electrode is thickened by the oxide film 10, the impurities do not penetrate the gate electrode 4.

When introducing impurities into the deep N ⁺ junction, the dose is lowered to 5 × 10 ^{13 to} 5 × 10 ¹⁴ / cm 3.
^{If it is 2} , the impurity concentration on the N ⁺ layer side of the junction formed by the N ⁺ layer and the P-type substrate is about 5 × 10 ^{18 to} 5 × 10 ¹⁹ / cm ³ , and the depletion layer extends to the N ⁺ layer side. Therefore, the junction capacitance is reduced. However, in this case, the edge of the depletion layer toward the N ⁺ layer is
It is necessary not to reach the bottom of the silicide.

The manufacturing method of the third embodiment is shown in FIGS. 4 and 5 and the manufacturing method of the fourth embodiment is shown in FIGS. 6 and 7 and will be described below. However, this embodiment is more practical for manufacturing CMOS devices. It is in compliance.

4 to 5 show a manufacturing method according to the third embodiment of the present invention. First, as shown in FIG.
After forming the field oxide film 2, the gate oxide film 3, and the gate electrode 4 on the P-type substrate 1, by a normal photolithography process,
By covering the PchMOSFET region (right half of FIG. 4) with the photoresist 26a and ion-implanting phosphorus or arsenic as the LDD layer (N ⁻ layer), the NchMOSFET is formed.
N ^{− of the} source / drain layer only in the region (left half of FIG. 4)
Form layer 20. Next, as shown in FIG. 4B, the photoresist 26a is removed, an oxide film or an oxide film containing boron / phosphorus or the like is deposited on the entire surface by the CVD method, and anisotropic etching is performed by the RIE method. As a result, the first sidewall 2 is formed on the sidewall of the gate electrode 4.
Leave 1 After that, as shown in FIG. 4C, before forming the source / drain regions, S at a temperature of 850 to 900 ° C.
The i surface is oxidized to form a thermal oxide film 22 of 100 to 200 Å. After that, the Si nitride film 23 is formed by the CVD method.
(100-1000Å) is deposited on the entire surface, and further C
By the VD method, an oxide film or an oxide film 24 containing impurities such as boron / phosphorus is deposited in a range of 3000 to 6000Å.

Thereafter, as shown in FIG. 4D, anisotropic etching is performed by the RIE method to leave the second sidewalls 25 on the sidewalls of the first sidewalls 21. At this time, the width of the second sidewall is 0.2
Is about 0.4 μm. At this time, the second sidewall 2
After the etching of 5, the silicon nitride film 23 and the thermal oxide film 22 other than the sidewall portion are also removed by etching.

Thereafter, as shown in FIG. 4E, a Pch MOSFET forming region is covered with a photoresist 26b by a photolithography process, and ion implantation for forming a deep junction layer 5b on the entire surface is performed by using phosphorus. 50-150 ke
V is injected under the condition of 1 × 10 ¹⁴ to 1 × 10 ¹⁵ ions / cm ² .

Then, as shown in FIG. 5 (f), PchMO
After removing the second side wall 25 by hydrofluoric acid solution or dry etching by RIE method without removing the photoresist 26 in the SFET region, that is, the first side wall 21 is left and a shallow junction is formed by the structure. Arsenic was added at 30 to 60 keV for 3 to 8 × 10 ¹⁵ to form the layer 5a.
injection under the conditions of ions / cm ² . In this case, the sidewall 21 remains substantially L-shaped, but the protruding portion of the bottom side is thin, and therefore the implantation passes through that portion. That is, the main part of the first sidewall 21 (described as such in this description) serves as a mask. Then Figure 5
As shown in (g), the photoresist 26b is removed, and the same operation is performed for the Pch MOSFET. Therefore, the explanation will be simplified. That is, the Nch MOSFET formation region is covered with the photoresist 27, and ion implantation for forming a deep junction is performed by ¹¹ B ⁺ , 30 to 70 keV, 1 × 10.
¹⁴ to 1 × 10 ¹⁵ ions / cm ² or ⁴⁹ BF ₂ ⁺⁵⁰
〜150 keV, 1 × 10 ¹⁴ 〜1 × 10 ¹⁵ ions / c
The condition is m ² . After that, as shown in FIG.
Without removing the photoresist 27 in the hMOSFET region,
The second sidewall 28 on the Pch side is provided with a hydrofluoric acid solution,
Alternatively, after removing by dry etching by the RIE method, ⁴⁹ BF ₂ ⁺ is added to 40 to 70 keV with the main portion of the first sidewall as a mask for forming a shallow junction.
It is injected under the condition of 3 to 8 × 10 ¹⁵ ions / cm ² .

Then, the photoresist 27 is removed, and 85
A heat treatment at 0 to 950 ° C. for about 10 to 40 minutes is annealed in a nitrogen atmosphere to activate and diffuse the implanted impurities.

Under the above conditions, the NchMOSFE
Similar to T, the N ^- layer has a junction depth of 0.05 to 0.15μ.
The N ⁺ layer of m and arsenic has a junction depth of 0.1 to 0.2 μm, and the N ⁺ layer of phosphorus has a junction depth of 0.20 to 0.45 μm. Similarly, the P ⁺ layer with ⁴⁹ BF ₂ ⁺ is
Junction depth 0.20 to 0.40 μm, ¹¹ B ⁺ or ⁴⁹ BF
_The P ⁺ layer formed of ₂ ⁺ has a junction depth of 0.35 to 0.50 μm.

Thereafter, as shown in FIG. 5 (i), a refractory metal is deposited on the entire surface and heat-treated at 600 to 1000 ° C., whereby the refractory metal, Poly-Si and Si are added.
A silicidation reaction occurs between and, and the refractory metal silicide 28 is formed on the gate electrode 4 and the deep layers of the source / drain portions in a self-aligned manner. Then, the unreacted refractory metal 29 is removed to complete the salicide structure as shown in FIG.

A fourth embodiment is shown in FIGS. 6 to 7 and described below. However, there are almost the same steps as in the third embodiment, and the description of that part will be simplified.

As shown in FIG. 6A, the field oxide film 2, the gate oxide film 3 as a gate electrode, and the polysilicon 2 are formed.
1, after forming a refractory metal (WSi _x) 22, by the CVD method, the oxide film 23 is 1000~3000Å form, gate electrodes. After that, by a normal photolithography process, the Pch MOSFET region is covered with the photoresist 24, and phosphorus or arsenic is ion-implanted as a Lightly Dope layer (N ⁻ layer) to obtain Nc.
The N ⁻ layer 25 is formed only in the hMOSFET region. Thereafter, as shown in FIG. 6B, the resist 24 is removed, an oxide film 26 of 250 to 1000 Å is deposited on the entire surface by a CVD method, and subsequently, a Si nitride film 27 of 50 is deposited by a CVD method.
Deposit ~ 500Å. The oxide film 26 and the Si nitride film 27 function as a first sidewall having a width of 300 to 1500Å. Subsequently, an oxide film or an oxide film 28 containing boron, phosphorus or the like is formed to 300 by the CVD method.
Deposit 0 to 6000Å.

Thereafter, as shown in FIG. 6C, anisotropic etching is performed by the RIE method to leave the second side wall 29 on the side wall of the first side wall. Then, as shown in FIG. 6D, after etching the second sidewall 29, the Si nitride film 27 and the oxide film 26 other than the sidewall portion are also removed by etching.

After that, as shown in FIG. 6E, the Pch MOSFET formation region is formed into a photoresist 3 by a photolithography process.
Ion implantation for forming a deep junction on the entire surface is performed with phosphorus at 50 to 150 keV, 1 × 10 ¹⁴
It is injected under the condition of ˜1 × 10 ¹⁵ ions / cm ² . Then, as shown in FIG. 7F, the photoresist 30 in the Pch MOSFET region is not removed and the second sidewall 2 is not removed.
9 was removed by a hydrofluoric acid solution or dry etching by the RIE method, and then arsenic was removed at 40 to 100 keV.
Inject 3 to 8 × 10 ¹⁵ ions / cm ² . After that, the photoresist 30 is removed, and the same operation is performed on Pch.
Perform on MOSFET.

That is, as shown in FIG. 7 (g), NchM
The OSFET formation region is covered with a photoresist 31, and ion implantation for forming a deep junction is performed with ¹¹ B ⁺ , 30 to 7
0 keV, 1 × 10 ¹⁴ to 1 × 10 ¹⁵ ions / cm ² or ⁴⁹ BF ₂ ⁺ 50 to 150 keV, 1 × 10 ¹⁴ to 1 ×
It is carried out under the condition of 10 ¹⁵ ions / cm ² .

After that, as shown in FIG. 7H, NchMOS
Without removing photoresist 31 of FET region, a second sidewall 32 of the Pch side, hydrofluoric acid solution or, after removal by dry etching by RIE method, ⁴⁹
BF ₂ ⁺ is 40 to 70 keV, 3 to 8 × 10 ¹⁵ ions
/ Cm ² conditions.

After that, as shown in FIG. 7I, the photoresist 31 is removed, and a heat treatment at 850 to 950 ° C. for about 10 to 40 minutes is annealed in a nitrogen atmosphere to activate and diffuse the implanted impurities. Under the above conditions, the N ⁻ layer has a junction depth of 0.1 to 0.2 μm, the arsenic N ⁺ layer has a junction depth of 0.15 to 0.25 μm, and the phosphorus N ⁺ layer has a thickness of 0.
The bonding has a bonding depth of 35 to 0.50 μm. Similarly, the P ⁺ layer of ⁴⁹ BF ₂ ⁺ has a junction depth of 0.25 to
The P ⁺ layer of 0.40 μm, ¹¹ B ⁺ or ⁴⁹ BF ₂ ⁺ is
The bonding has a bonding depth of 0.35 to 0.50 μm.

After that, as shown in FIG. 7 (i), the hot-phosphoric acid solution is used to remove the Si nitride film 27, the refractory metal 32 is deposited on the entire surface, and a heat treatment at 600 to 1000 ° C. is performed. As a result, a silicidation reaction occurs between the refractory metal and Si, and the refractory metal silicide 33 is formed in the source / drain portions in a self-aligned manner. In this case, as in the second embodiment, since the oxide film 23 is present on the gate electrode, the silicide is not formed. Then, the unreacted refractory metal is removed to complete the salicide structure as shown in FIG. 7 (j).

In the fourth embodiment, if the oxide film 23 is not formed on the upper layer of the gate electrode, silicide can be formed on the gate electrode as in the third embodiment.

FIG. 8 is a manufacturing method showing a fifth embodiment of the present invention. The steps will be described below in order.

FIG. 8 (a): A field oxide film 2 is formed on the semiconductor substrate 1 to a thickness of 4000Å and a gate oxide film 3 is formed on the semiconductor substrate 1 in accordance with the usual method, and impurities are ion-implanted for adjusting the threshold voltage. Further, the gate electrode 4 is formed by using a normal photolithography etching. Furthermore, an oxide film 6 that becomes a narrow sidewall (a width of 0.3 μm or less is desirable as described later) is formed on the entire surface by LP
CVD (uses O ₃ -TEOS (tetraethoxylane) because it has good step coverage and good film growth controllability)
Therefore, about 700Å is deposited. Nch type MOS ・ FET
In this case, the impurity N ⁻ (phosphorus or arsenic) for forming an LDD layer for suppressing the hot carrier effect is implanted by oblique ion implantation with a large oblique angle (about 45 °) at a dose of 2 × 10 ¹³ / cm ² . Impurity N for source / drain formation
⁺ (Arsenic) is continuously implanted at an energy of 60 keV and a dose amount of 1 × 10 ¹⁴ to 1 × 10 ¹⁵ / cm ² , which is lower than the normally used dose amount (3 to 5 × 10 ¹⁵ / cm ² ). In the case of the Pch-type MOSFET, it is not necessary to care about the hot carrier effect, so only the impurities (boron) for forming the source / drain are implanted. In this case as well, the dose amount normally used (3 to 5 × 10 ¹⁵ / cm
² ) at lower doses, eg BF ₂ ⁺ , 60 ke
V is injected under the condition of 1 × 10 ¹⁴ to 1 × 10 ¹⁵ / cm ² . FIG. 10A shows an experimental result of the junction depth when the dose amount of the source / drain is decreased by taking the Pch MOSFET as an example. The dose is 4 × 10 ¹⁵ / c
from ^{m 2, 1 × 10 14 /} cm 2 and the junction depth by becomes 0.1μm and conventional 1/2 or less than 0.23 .mu.m. Further, in this case, the implantation dose is 7 × 10
If it is ¹³ / cm ² or more, the surface concentration is 1 × 10 ¹⁹ / c.
Since it becomes m ³ or more, the driving force of the MOSFET is not significantly reduced. In fact, according to this result, 1 × 10 ²⁰
Source / drain with surface concentration of 1 / cm ³ and 1 × 10 ¹⁹
Source / drain MOSFE with surface concentration of / cm ³
The difference in driving force of T is 1 when the sidewall width is 0.3 μm.
It was 0% or less.

Next, as shown in FIG. 8B, an oxide film (or a nitride film) 8 is deposited on the entire surface by CVD to about 2000 to 3000 Å.

FIG. 8C, and a wide sidewall 8a is formed by anisotropic etching. In this case, the width of the formed sidewall is 2500Å to 3500Å
Becomes

Next, FIG. 8 (d), a refractory metal (titanium, cobalt, etc.) 9 is deposited on the entire surface by sputtering at about 400 Å. By silicidation annealing, silicon on the upper surface of the gate electrode 4 and the upper surfaces of the source / drain regions reacts with the refractory metal 9 to form silicide.

Next, FIG. 8E, the unreacted refractory metal on the field oxide film 2 and the sidewalls 8a is selectively removed by selective etching. Then, silicide low resistance annealing 9a is performed.

FIG. 8 (f), further, in the case of Nch, arsenic or phosphorus is used, and in the case of Pch, boron is used as B.
By ion implantation (N ⁺ or P ⁺ ) of F ₂ ⁺ ions,
For example, acceleration energy of 50 keV, dose amount of 1 × 10
It is injected under the condition of about ¹⁵ / cm ² . This ion implantation is
Implantation is performed in the silicide or in the vicinity of the silicide / silicon interface, and then impurity annealing is performed at about 850 ° C.

FIG. 9 shows a case where the above method is applied to manufacture of a CMOS type cumulative circuit. Therefore, it has an Nch region (left half in the figure) and a Pch region (right half in the diagram) (similar to the conventional example and the third and fourth embodiments).

9A, an N-type well region (right half of FIG. 9) is formed on a P-type silicon substrate 1, and a field oxide film 2, a gate oxide film 3 and a gate electrode 4 are formed. Here, the oxide film 6 may be deposited in the step (b) below. Next, cover the Nch type region with a resist 26b,
First, the impurity (boron) P ⁺ which becomes the source / drain of the Pch-type MOSFET is, for example, BF ₂ ⁺ , 30 ke
V is injected under the condition of 1 × 10 ¹⁴ / cm ² . Then, the resist 26b is removed.

Next, as shown in FIG. 9B, O ₃ -TEOS is formed on the entire surface.
The oxide film 6 is deposited to about 700 Å (at least 1000 Å or less) by LPCVD using. The Pch-type region is covered with the resist 26a, and phosphorus is used, for example, at 45 °, 70 keV, 2 × 10 ¹³ / cm ² to form an LDD layer.
Implantation (N ⁻ ) is carried out by ion implantation with a large angle of inclination. Further, subsequently, impurities (arsenic) to be the source / drain are, for example, As ⁺ , 110k
Implantation (N ⁺ ) is performed under the conditions of eV and 1 × 10 ¹⁵ / cm ² .

FIG. 9 (c) Next, 2000Å-3 on the entire surface
After depositing an oxide film of about 000Å, the sidewalls 8a are formed by anisotropic etching. After that, a refractory metal 28 is deposited on the entire surface by about 400 Å, and silicon is reacted with the refractory metal by annealing to form a silicide.

FIG. 9D. Next, after selectively removing the unreacted refractory metal by selective etching, Nch
Side, Pch side is covered with resist on each side, Nch side,
An N-type impurity and a P-type impurity are implanted into the Pch side under implantation conditions so that the junction becomes deeper than that obtained in the steps (a) and (b).

In FIG. 10B, the Pch-type impurities are implanted (BF ₂ ⁺³⁰ keV, 1 ×) in the step (a) as described above.
10 ¹⁴ / cm ² condition), and the carrier concentration of the source / drain is 1 × 10 ¹⁹ / cm 2.
^{Since 3} overlaps the end of the gate electrode, there is no particular problem.
The junction depth Xj is as shallow as 0.09 μm.

FIG. 10C shows the Pch in the above step (b).
Type impurities (BF ₂ ⁺ , 60 keV, 2 × 10 ¹⁴ /
cm ² condition). In this case, the source / drain carrier concentration of 1 × 10 ¹⁹ / cm ³ is outside the end of the gate electrode, and the junction depth Xj is as shown in FIG.
Similar to the above, it is about 0.09 μm or has a slight offset, the driving force is reduced, and further, characteristic fluctuations occur due to continuous current flow.

[0059]

As described above, according to the present invention, in the first to fourth embodiments, the shallow N ⁺ layer formed using the first sidewall of the gate electrode as a mask is used to form a fine MOS transistor.
The short channel effect, which is a problem in the FET, can be effectively suppressed, and since only the deep N ⁺ layer formed by using the second sidewall as a mask is silicided in the source / drain portion, the silicide bottom surface and It is possible to form a good junction in which a junction leakage current does not occur because the distance from the junction is sufficient. The second sidewall is sufficiently separated from the edge of the gate electrode (0.3 to
0.5 μm), so even if the junction depth at that portion is deep, M
It does not affect the short channel effect of the OSFET.

Further, in comparison with the case where the sidewall length is simply lengthened to extend the N ⁻ layer and the shallow N ⁺ layer is not formed, this increases the parasitic resistance due to the N ⁻ layer. , The driving force of the MOSFET is lowered, but the problem of the increase of the N ⁻ layer parasitic resistance can be avoided by forming the shallow N ⁺ layer. Furthermore, the junction capacitance can be reduced by reducing the dose amount of the deep N ⁺ layer.

Further, as in the present invention, by using the Si nitride film as a stopper for the etching of the second sidewall, the Nch source / drain and the P-channel are formed.
Junctions having different depths can be formed without increasing the photolithography process for forming the ch source / drain regions.

In the fifth embodiment, the source / drain forming implantation dose makes the junction depth sufficiently shallow,
Moreover, since the control is performed within a range that does not reduce the driving force, it is possible to realize a MOSFET having a sufficiently short channel effect and a high driving force even in a fine MOSFET. Furthermore, since the source / drain is salicided outside the relatively long sidewall and the junction is deep only in that region, increase in junction leakage current is suppressed without increasing the short channel effect of the transistor. it can. Moreover, the source / drain implantation is performed at a relatively low dose, and the increase in the sheet resistance of the source / drain is suppressed by salicide to realize a sufficiently low resistance. Moreover, in the step of reacting silicon with the refractory metal (silicidation step), the impurity concentration in the silicon is not as high as in the conventional case, so that the silicidation step can be performed stably with good reproducibility.

In manufacturing the CMOS of the sixth embodiment, the source / drain (low dose compared to the prior art) impurity implantation in the Pch region is prevented from becoming an offset while making the junction shallow, and a MOSFET having no characteristic fluctuation is realized. it can. In addition, LDD on the Nch side, through a relatively thin oxide film that does not etch, LDD implant,
Since the source and drain implants are performed simultaneously, the mask
The steps can be simplified, and the sidewall etching can be performed only once after the formation of a relatively thick oxide film, which is the next step, and the process can be simplified. Further, since the source / drain impurity implantation having a lower dose amount than in the past is performed through the thin Nch oxide film, the driving force of the Nch MOSFET can be increased.

[Brief description of drawings]

FIG. 1 is a structure of a first embodiment of the present invention.

FIG. 2 is a manufacturing method of the first embodiment of the present invention.

FIG. 3 is a manufacturing method of the second embodiment of the present invention.

FIG. 4 is a manufacturing method (No. 1) of the third embodiment of the present invention.

FIG. 5 is a manufacturing method (2) of the third embodiment of the present invention.

FIG. 6 is a manufacturing method (part 1) of the fourth embodiment of the present invention.

FIG. 7 is a manufacturing method (2) of the fourth embodiment of the present invention.

FIG. 8 is a manufacturing method of a fifth embodiment of the present invention.

FIG. 9 is a manufacturing method of a sixth embodiment of the present invention.

FIG. 10 shows the experimental results of the fifth and sixth embodiments of the present invention.

FIG. 11 shows a conventional example.

FIG. 12 is an explanatory diagram of problems.

[Explanation of symbols]

 1 substrate 2 field oxide film 3 gate oxide film 4 gate electrode 5 source / drain layer (5a shallow layer, 5b deep layer) 6 first sidewall 8 second sidewall

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7377-4M H01L 29/78 301 L

Claims (6)

[Claims] 1. A structure of a field effect transistor section in a semiconductor device having a field effect transistor, wherein a first sidewall is formed on a side wall of a gate electrode and a second sidewall is formed on a side surface thereof. The first
A source / drain layer formed by using the main part of the sidewall as a mask, and a source / drain layer deeper than the source / drain layer by the first sidewall formed by using the second sidewall as a mask. Then
A semiconductor device having a silicided layer formed on at least an upper portion of a source / drain layer formed by the second sidewall. 2. The semiconductor device according to claim 1, wherein the second sidewall is removed in the final structure. 3. A step of: (a) forming a gate electrode of a field effect transistor on a semiconductor substrate and forming a first sidewall on a side wall of the gate electrode; (b) forming the first sidewall of the first sidewall. Forming a second sidewall on the side surface; (c) forming a layer to be a source / drain of the field effect transistor by using the main portion of the first sidewall as a mask; (d) Forming a source / drain layer deeper than the source / drain layer by the first sidewall by using the second sidewall as a mask; (e) at least the source / drain layer by the second sidewall; A method of manufacturing a semiconductor device, which comprises the step of siliciding the upper part, and the above steps. 4. (a) A gate electrode of a field effect transistor is formed on a semiconductor substrate, and a total width of first and second sidewalls formed on a side wall of the gate electrode is 0.3 μm or less. A step of forming an insulating film on the entire surface so that (b) the layer serving as the source / drain layer of the field-effect transistor is masked with the first sidewall, and the dose amount of the impurity implantation for forming is 7 × 10. Implanting in the range of ¹³ / cm ² to 1 × 10 ¹⁵ / cm ² , (c) forming a second sidewall on the sidewall of the gate electrode outside the first sidewall, and (d) ) Forming a silicide layer of refractory metal on the upper surfaces of the gate electrode and the source / drain regions,
And a step of forming a source / drain layer deeper than the source / drain layer formed in the above step, using the side wall as a mask, and the above steps. 5. In manufacturing a CMOS type semiconductor device having a P-channel (Pch) region and an N-channel (Nch) region on the same substrate, (a) after forming a gate electrode of a field effect transistor in the both regions. First, on the Pch region side, a step of forming a source / drain layer on the Pch region side under the same method and conditions as in (a) and (b) of claim 4, (b) after the process, on the Nch region side Forming a source / drain layer and forming a second sidewall outside the first sidewall of the gate electrode, (c) both the Nch and Pch regions, the gate electrode and the source in that region A step of forming a silicide layer of a refractory metal on the upper surface of the drain layer, and a method of manufacturing a semiconductor device including the above steps. 6. A method for manufacturing a CMOS semiconductor device having a P-channel (Pch) region and an N-channel (Nch) region on the same substrate, comprising: (a) after forming a gate electrode of a field effect transistor in the both regions. A step of forming a source / drain layer in a Pch region under the same method and conditions as in (a) and (b) of claim 4 using the gate electrode as a mask, (b) a side wall of the gate electrode Insulation film with a thickness of 1000 Å or less is deposited on the entire surface including 1 side wall formation,
A step of performing impurity implantation for forming the source / drain layer and the LDD type layer of the field effect transistor only on the Nch region side through the insulating film, (c) outside the first sidewall of the gate electrode 2 side walls to form a side wall
Forming an insulating film of 000 to 3000 Å and forming the second side wall, and then forming a silicide layer of refractory metal on at least the upper surface of the source / drain layer. Of manufacturing a semiconductor device.