JPH053134B2 - - Google Patents
Info
- Publication number
- JPH053134B2 JPH053134B2 JP59125239A JP12523984A JPH053134B2 JP H053134 B2 JPH053134 B2 JP H053134B2 JP 59125239 A JP59125239 A JP 59125239A JP 12523984 A JP12523984 A JP 12523984A JP H053134 B2 JPH053134 B2 JP H053134B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor device
- applying
- signal
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 34
- 239000011159 matrix material Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 239000004020 conductor Substances 0.000 description 4
- 239000011093 chipboard Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、半導体装置に係り、特に、全面バン
プ（突起電極）あるいは高密度なフリツプチツプ
方式のボンデイング技術を採用した大規模集積回
路（以下、単に、LSIという）等の半導体装置に
適用して有効な技術に関するものである。Detailed Description of the Invention [Technical Field] The present invention relates to semiconductor devices, and in particular to large-scale integrated circuits (hereinafter simply referred to as LSIs) that employ full-surface bumps (protruding electrodes) or high-density flip-chip type bonding technology. The present invention relates to techniques that are effective when applied to semiconductor devices such as
フリツプチツプ方式のボンデイング技術を採用
したLSIチツプ等の半導体装置では、バンプ（突
起電極）は、半導体チツプの周囲に配置されてい
るが、例えば、第１図に示されるように、たがい
に隣り合うバンプは信号電圧印加用バンプ（以
下、単に信号用バンプという）Ｓとして使用され
ており、その一部が接地電圧印加用バンプ（以
下、単に接地用バンプという）Ｇとして使用され
ている。
In semiconductor devices such as LSI chips that employ flip-chip bonding technology, bumps (protruding electrodes) are arranged around the semiconductor chip. For example, as shown in FIG. is used as a signal voltage application bump (hereinafter simply referred to as a signal bump) S, and a portion thereof is used as a ground voltage application bump (hereinafter simply referred to as a ground bump) G.
しかしながら、このような半導体チツプでは、
特に、高速な入出力を行う場合、たがいに隣り合
う信号用バンプ間でのクロストークが発生し、
LSI等の半導体装置の機能に誤動作を起す原因と
なるおそれがあることが、発明者の検討の結果、
明らかとなつた。 However, in such semiconductor chips,
In particular, when performing high-speed input/output, crosstalk occurs between adjacent signal bumps.
As a result of the inventor's investigation, it has been determined that there is a risk of causing malfunctions in the functions of semiconductor devices such as LSI.
It became clear.
本発明の目的は、フリツプチツプ方式のボンデ
イング技術を採用したLSIチツプ等の半導体装置
において、半導体チツプの信号線をシールドする
ことにより、信号線間のクロストークノイズを低
減する技術手段を提供することにある。
An object of the present invention is to provide a technical means for reducing crosstalk noise between signal lines by shielding the signal lines of a semiconductor chip in a semiconductor device such as an LSI chip that employs flip-chip bonding technology. be.
本発明の前記ならびにその他の目的と新規な特
徴は、本明細書の記述及び添付図面によつて明ら
かになるであろう。 The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的な
ものの概要を説明すれば、下記のとおりである。
Outline of typical inventions disclosed in this application is as follows.
すなわち、フリツプチツプ方式のボンデイング
技術を採用したLSIチツプ等の半導体装置におい
て、半導体チツプの信号用バンプの間又は周囲の
接地用バンプを配置することにより、各信号線を
シールドして信号線間のクロストークノイズを低
減するようにしたものである。 In other words, in semiconductor devices such as LSI chips that employ flip-chip bonding technology, grounding bumps are placed between or around the signal bumps of the semiconductor chip to shield each signal line and prevent cross-overs between signal lines. This is designed to reduce talk noise.
以下、本発明の構成について、実施例とともに
説明する。 Hereinafter, the configuration of the present invention will be explained along with examples.
なお、全図において、同一の機能を有するもの
は同一符号を付け、その繰り返しの説明は省略す
る。 In all the figures, parts having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted.
〔実施例 〕
第２図は、本発明をフリツプチツプ方式のボン
デイング技術を採用したLSIチツプ等の半導体装
置に適用した実施例の構成を説明するための図
であり、その要部の平面図である。[Embodiment] FIG. 2 is a diagram for explaining the configuration of an embodiment in which the present invention is applied to a semiconductor device such as an LSI chip that employs flip-chip bonding technology, and is a plan view of the main part thereof. .
本実施例の半導体装置は、第２図に示すよう
に、半導体チツプLSIの隣り合う信号用バンプＳ
の間に接地用バンプＧを配置したものである。 As shown in FIG. 2, the semiconductor device of this embodiment has adjacent signal bumps S of a semiconductor chip LSI.
A grounding bump G is placed between them.
このように信号用バンプＳを接地用バンプＧで
包囲することにより、この接地用バンプＧのシー
ルド効果によつて外部から信号線に入るノイズを
遮断するので、超高速な入出力を行う場合におい
ても、近接した信号線間のクロストークノイズを
低減することができる。 By surrounding the signal bump S with the grounding bump G in this way, the shielding effect of the grounding bump G blocks noise entering the signal line from the outside, so when performing ultra-high-speed input/output. Also, crosstalk noise between adjacent signal lines can be reduced.
〔実施例 〕
第３図は、本発明をフリツプチツプ方式のボン
デイング技術を採用したLSIチツプ等の半導体装
置に適用した実施例の構成を説明するための図
であり、その半導体チツプの要部の平面図であ
る。[Embodiment] FIG. 3 is a diagram for explaining the configuration of an embodiment in which the present invention is applied to a semiconductor device such as an LSI chip that employs flip-chip bonding technology. It is a diagram.
本実施例の半導体装置は、前記実施例の信
号用バンプＳと接地用バンプＧの配置を変えたも
のであり、第３図に示すように、信号用バンプＳ
の周囲に接地用バンプＧを配置したものである。 In the semiconductor device of this embodiment, the arrangement of the signal bumps S and the ground bumps G of the previous embodiment is changed, and as shown in FIG.
Grounding bumps G are arranged around the .
このように構成することにより、前記実施例
のものよりも、一層信号用バンプＳに対するシー
ルド効果を持たせることができる。 With this configuration, it is possible to provide a greater shielding effect for the signal bumps S than in the embodiments described above.
〔実施例 〕
第４図及び第５図は、本発明をフリツプチツプ
方式のボンデイング技術を採用したLSIチツプ等
の半導体装置に適用した実施例の構成を説明す
るための図であり、第４図は、平面図、第５図
は、第４図のＡ−Ａ切断線における断面図であ
る。なお、第４図においては半導体チツプＣは省
略してある。[Embodiment] FIGS. 4 and 5 are diagrams for explaining the configuration of an embodiment in which the present invention is applied to a semiconductor device such as an LSI chip that employs flip-chip bonding technology. , a plan view, and FIG. 5 is a sectional view taken along the line AA in FIG. 4. Note that the semiconductor chip C is omitted in FIG.
本実施例の半導体装置は、第４図及び第５図
に示すように、前記実施例の接地用バンプＧを
一体化した導体で形成し、これにより信号用バン
プＳの周囲を包囲するように構成したものであ
る。MBは配線が施されたシリコンからなるマザ
ーチツプ基板Ｃは半導体チツプである。 As shown in FIGS. 4 and 5, in the semiconductor device of this embodiment, the ground bump G of the above embodiment is formed of an integrated conductor, so that the signal bump S is surrounded by this conductor. It is composed of MB is a mother chip made of silicon with wiring provided, and C is a semiconductor chip.
このように構成することにより、さらに、信号
用バンプＳに対するシールド効果を向上させるこ
とができる。 With this configuration, the shielding effect for the signal bumps S can be further improved.
以上説明したように、本願で開示した新規な技
術手段によれば、次のような効果を得ることがで
きる。
As explained above, according to the novel technical means disclosed in this application, the following effects can be obtained.
(1) 半導体装置の隣り合う信号用バンプＳの間
に、接地用バンプＧを配置することにより、接
地用バンプＧのシールド効果によつて外部から
信号線に入るノイズを遮断するので、超高速な
入出力を行う場合においても、近接した信号線
間のクロストークノイズを低減することができ
る。(1) By placing a grounding bump G between adjacent signal bumps S of a semiconductor device, the shielding effect of the grounding bump G blocks noise entering the signal line from the outside, resulting in ultra-high speed operation. Even when performing input/output, crosstalk noise between adjacent signal lines can be reduced.
(2) 半導体装置の信号用バンプＳの周囲に接地用
バンプＧを配置することにより、一層信号用バ
ンプＳに対するシールド効果を持たせることが
できる。(2) By arranging the grounding bumps G around the signal bumps S of the semiconductor device, it is possible to provide a further shielding effect for the signal bumps S.
(3) 前記(2)の半導体装置の接地用バンプＧを一体
化した導体で形成し、これにより信号用バンプ
Ｓの周囲を包囲するように構成することによ
り、さらに、信号用バンプＳに対するシールド
効果を向上させることができる。(3) By forming the grounding bump G of the semiconductor device in (2) above with an integrated conductor and configuring it to surround the signal bump S, it is possible to further provide a shield for the signal bump S. The effect can be improved.
(4) 前記(1)乃至(3)のそれぞれの技術手段により、
超高速な入出力を行う場合においても、半導体
装置の近接する信号線間のクロストークノイズ
を低減させることができるので、半導体装置の
信頼度を向上させることができる。(4) By each of the technical means mentioned in (1) to (3) above,
Even when performing ultra-high-speed input/output, crosstalk noise between adjacent signal lines of a semiconductor device can be reduced, so reliability of the semiconductor device can be improved.
以上、本発明を実施例にもとずき具体的に説
明したが、本発明は、前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲にお
いて種々変更可能であることはいうまでもな
い。 Although the present invention has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor.
第１図は、フリツプチツプ方式のボンデイング
技術を採用したLSIチツプ等の半導体装置の信号
用バンプに対する問題点を説明するための図であ
り、半導体装置の要部の平面図、第２図は、本発
明をフリツプチツプ方式のボンデイング技術を採
用したLSIチツプ等の半導体装置に適用した実施
例の構成を説明するための図であり、その半導
体チツプの要部の平面図、第３図は、本発明をフ
リツプチツプ方式のボンデイング技術を採用した
LSIチツプ等の半導体装置に適用した実施例の
構成を説明するための図であり、その半導体チツ
プの要部の平面図、第４図及び第５図は、本発明
をフリツプチツプ方式のボンデイング技術を採用
したLSIチツプ等の半導体装置に適用した実施例
の構成を説明するための図であり、第４図は、
その導体チツプの要部の平面図、第５図は、第４
図のＡ−Ａ切断線における断面図である。
図中、LSI，Ｃ……半導体チツプ、Ｓ……信号
用バンプ、Ｇ……接地用バンプ、MB……マザー
チツプ基板である。
Figure 1 is a diagram for explaining problems with signal bumps in semiconductor devices such as LSI chips that employ flip-chip bonding technology. FIG. 3 is a diagram for explaining the configuration of an embodiment in which the invention is applied to a semiconductor device such as an LSI chip that employs flip-chip bonding technology; FIG. Adopts flip-chip bonding technology
FIG. 4 is a diagram for explaining the configuration of an embodiment applied to a semiconductor device such as an LSI chip, and the plan view of the main part of the semiconductor chip, FIGS. FIG. 4 is a diagram for explaining the configuration of an embodiment applied to a semiconductor device such as an adopted LSI chip, and FIG.
The plan view of the main part of the conductor chip, FIG.
It is a sectional view taken along the line AA in the figure. In the figure, LSI, C: semiconductor chip, S: signal bump, G: grounding bump, MB: mother chip board.
Claims (1)
の複数の突起電極を行列状に規則的に配置してな
るフリツプチツプ型の半導体装置において、行方
向に隣り合う信号電圧印加用突起電極の中間、及
び列方向に隣り合う信号電圧印加用突起電極の中
間にそれぞれ接地電圧印加用突起電極を配置して
なることを特徴とする半導体装置。 ２ 上記の一つの信号電圧印加用突起電極に対し
て斜め方向に隣接しかつ上記接地電圧印加用突起
電極と共に行列状の規則的配列を成す接地電圧印
加用突起電極を配置してなることを特徴とする特
許請求の範囲第１項記載の半導体装置。[Scope of Claims] 1. In a flip-chip semiconductor device in which a plurality of protruding electrodes of substantially the same shape are regularly arranged in a matrix on a semiconductor chip, signal voltage applying protrusions adjacent in the row direction 1. A semiconductor device characterized in that a protruding electrode for applying a ground voltage is arranged between the electrodes and between protruding electrodes for applying a signal voltage adjacent in the column direction. 2. Protruding electrodes for applying a ground voltage are arranged diagonally adjacent to the one protruding electrode for applying a signal voltage and forming a regular array in a matrix together with the protruding electrode for applying a ground voltage. A semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12523984A JPS615549A (en) | 1984-06-20 | 1984-06-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12523984A JPS615549A (en) | 1984-06-20 | 1984-06-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS615549A JPS615549A (en) | 1986-01-11 |
| JPH053134B2 true JPH053134B2 (en) | 1993-01-14 |
Family
ID=14905233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12523984A Granted JPS615549A (en) | 1984-06-20 | 1984-06-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS615549A (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6339191B1 (en) | 1994-03-11 | 2002-01-15 | Silicon Bandwidth Inc. | Prefabricated semiconductor chip carrier |
| US5842877A (en) * | 1996-12-16 | 1998-12-01 | Telefonaktiebolaget L M Ericsson | Shielded and impedance-matched connector assembly, and associated method, for radio frequency circuit device |
| US6724084B1 (en) | 1999-02-08 | 2004-04-20 | Rohm Co., Ltd. | Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device |
| JP4497683B2 (en) * | 2000-09-11 | 2010-07-07 | ローム株式会社 | Integrated circuit device |
| EP1328015A3 (en) * | 2002-01-11 | 2003-12-03 | Hesse & Knipps GmbH | Method of bonding a flip chip |
| EP1796160A1 (en) * | 2004-08-20 | 2007-06-13 | Rohm Co., Ltd. | Semiconductor device, power supply apparatus using the same, and electronic device |
| JP5119225B2 (en) | 2009-09-11 | 2013-01-16 | 株式会社日立製作所 | Semiconductor mounting substrate and semiconductor device |
| US20120217653A1 (en) * | 2009-11-10 | 2012-08-30 | Nec Corporation | Semiconductor device and noise suppressing method |
| JP2015060909A (en) * | 2013-09-18 | 2015-03-30 | オリンパス株式会社 | Semiconductor device |
| WO2018042518A1 (en) * | 2016-08-30 | 2018-03-08 | 株式会社日立製作所 | Semiconductor device and printed circuit board |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS574241B2 (en) * | 1977-12-29 | 1982-01-25 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS574241U (en) * | 1980-06-10 | 1982-01-09 |
-
1984
- 1984-06-20 JP JP12523984A patent/JPS615549A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS574241B2 (en) * | 1977-12-29 | 1982-01-25 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS615549A (en) | 1986-01-11 |
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