JPH05316083A - Equalizing method and adaptive equalizer in transmission line fluctuated in mobile radio system - Google Patents

Abstract

PURPOSE:To compensate the deterioration in the transmission characteristic due to inter-code interference by providing a transversal filter for each state transition and implementing filter coefficient control to minimize each estimate error. CONSTITUTION:A quasi-synchronization detection signal is inputted to a sampling circuit 11-1, from which a reception signal sample value I is outputted. The value I is inputted to arithmetic operation circuits 11-21-11-24 calculating an estimate error corresponding to each state transition and each circuit 11 receives a code series P corresponding to a bus of each state transition and a code series S corresponding to each state transition outputted from a Viterbi algorithm circuit 11-3. A value O resulting from multiplying -1 with square of estimate error to be obtained is fed to the circuit 11-3 as an error corresponding to each state transition and a discrimination signal attended with signal discrimination is obtained. A control circuit 12-4 in the circuit 11 uses a training signal and an output of a delay circuit 12-6 to estimate the initial tap coefficient of the transversal filter 12-1 and revises the tap coefficient in real time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an adaptive equalizer for compensating and equalizing transmission characteristic deterioration due to intersymbol interference in digital communication such as mobile radio.

[0002]

2. Description of the Related Art As one of adaptive equalizers, maximum likelihood sequence estimation (Maximum Likelihood Sequence) is performed.
nce Estimation: MLSE) is known. This adaptive equalizer calculates the likelihood corresponding to a possible signal sequence, and selects the signal sequence having the largest value in signal determination. However, as the signal sequence becomes longer, the number of all possible signal sequences grows exponentially. Therefore, in order to reduce the number of sequences and suppress the calculation amount, there is known a Viterbi type equalizer that performs state estimation by a Viterbi algorithm.

FIG. 1 is a block diagram showing the configuration of a conventional Viterbi equalizer, which is described in the following document.

(A. Baier, G. Heinric
h, and U. Wellens, “Bit Sync
hornization and Timing Se
nsitivity in Adaptive Vit
erbi Equalizers for Narro
wband-TDMA Digital Mobile
Radio Systems ", Proc. IEEE
Vehicular Technology Conf
Rence '88, pp. 377-384, June
1988).

In FIG. 1, the quasi-synchronous detection signal is input from the input terminal 10 to the sampling circuit 111 and the received signal sample value is output. The received signal sample value is input to the correlator 11 and the subtraction circuit 12. The received signal sample value y (i) is the received wave r (t)

[Equation 1] Is a sample value of the quasi-synchronous detection signal y (t). Here, f represents the carrier frequency and Re represents the real part. The received signal sample value y (i) includes a modulated wave with a symbol rate of 1 / T, and the sampling period is T.

The correlator 11 which receives the received signal sample value y (i) estimates the impulse response of the transmission line from the known signal contained in the transmitted signal. For example, the impulse response of the transmission path can be estimated by taking a correlation with the training signal added to the beginning of the data signal shown in FIG. The correlator 11 sets the estimated value of the impulse response as the tap coefficient of the transversal filter 13. The tap coefficient is not updated in the burst data signal section.

In the subtraction circuit 12, the received signal sample value y
Subtract the transversal filter output from (i) and output as the estimation error. The square calculation circuit 110 multiplies the square of the estimation error by −1, outputs it as a branch metric, and sends it to the Viterbi algorithm circuit 15 via the switch circuit 14. In the Viterbi algorithm circuit 15, a finite number of states make transitions every cycle T, but here, four transitions are shown as an example. A code sequence corresponding to each state transition is input to the signal generation circuit 16. Signal generation circuit 16
Generates a signal sequence of complex symbols corresponding to each input code sequence, and the switch circuit 17 sequentially selects each signal sequence and sends it to the transversal filter 13. The transversal filter 13 has a common tap coefficient for all state transitions, converts a signal sequence different for each state transition into each signal estimation value, and outputs it. When a signal sequence of complex symbols that matches the transmission signal is input to the transversal filter 13, a signal estimation value that is substantially equal to the reception signal is output. The switch control circuit 18 includes a switch circuit 14 and a switch circuit 17.
Are controlled at the same timing.

2 of the estimation error output from the subtraction circuit 12
The value obtained by multiplying the power by -1 is evaluated as the branch metric of the state transition selected by the switch circuit 17,
It is input to the Viterbi algorithm circuit 15. The Viterbi algorithm circuit 15 makes a signal decision and outputs the decision signal from the output terminal 19.

Next, the Viterbi algorithm for state estimation will be described by taking BPSK modulation as an example. The received signal sample value y (i) in the multipath propagation path can be expressed as follows.

[0010]

[Equation 2] However, K is a natural number, h (i) is an impulse response of the transmission path, and a (k) is a complex symbol of the BPSK signal, and takes values of +1 and -1 by modulation. n (i) is almost white Gaussian noise. In the above equation, h (i) represents the impulse response of the two-wave model, and its temporal spread is 1
When T

[Equation 3] Becomes Since intersymbol interference occurs, a (i) and a (i-
The value of y (i) is the weighted combination of h (0) and h (1) in 1). At this time, the transmission path is described in two states. However, there are two states when the temporal spread of the impulse response of the transmission path is 1T, and generally, when the spread is (K-1) T, the constraint length is K and the transmission path is 2 ^K-. Described in the state of ¹ . The sth state at the time point i−1 is σ _i−1 ^s . Here, since 0 < s < 1, it becomes σ _i−1 ⁰ and σ _i−1 ^{1 and the} state transitions when the time point advances from (i−1) to i. The transition is a complex symbol candidate α (i) = ± for a (i)
Since it depends on the value of 1, two transitions occur from one state. Since the transition destination is again σ _i ⁰ or σ _i ¹ , the trellis diagram as shown in FIG. 3 is obtained. As shown in this figure, one state branches into two states, and two states merge into one state. That is, α (i) =-
When it is 1, σ _i ⁰ is the transition destination state, and when α (i) = 1, σ _i ¹ is the transition destination state. Use the transition metric J _i (σ _i ^s , σ _i-1 ^s ) corresponding to the transition from σ _{i -1} ^s'to σ _i ^s to select one transition from the two transitions to be merged at the transition destination ..

The transition metric at the transition from the state σ _i-1 ^s'to σ _i ^s is the branch metric BR for each transition.
Using (σ _i ^s , σ _i-1 ^s' )

[Equation 4] It is calculated by. However

[Equation 5] Is. J _i-1 (σ _i-1 ^s' ) is the path metric at the time point (i-1) and corresponds to the likelihood. The transition signal sequence in the state transition σ _i-1 ^s' → σ _i ^s is {α (i-1),
α (i)}, whose element α (i-1) is a complex symbol candidate of a (i-1) corresponding to the state at time (i-1), and α (i) is a corresponding to transition. It is a complex symbol candidate of (i). The Viterbi algorithm compares J _i (σ _i ^s , σ _i-1 ^s' ) corresponding to two marginal transitions, selects the larger transition, and sets the transition metric of the selected transition at time i.
Let J _i (σ _i ^s ) be the path metric at. And the time series (path) of the state linked to the selected transition
If only these are left as the maximum likelihood series candidates, as many paths as the number of states survive. This path is called the survival path. If all surviving paths merge at some point in the past,
Since the state at that time can be determined, signal determination is performed.
However, if the merge is not performed, the signal determination is postponed. The above operation is repeated. Note that due to memory limitations, the time series of states is stored only up to the past (D−K + 1) T, and if the surviving paths do not merge at the past (D−K + 1) T, the path with the maximum likelihood at the present time, That is, signal determination is performed based on the path with the maximum path metric. The signal determined at this time is DT delayed from the present time,
This DT is called a judgment delay time (G. Ungerboe
ck, “Adaptive maximum like
lihood receiver for carri
er-modulated data-transmi
session systems, "IEEE Trans.
Commun, vol. COM-22, pp. 624-
636, 1974). However, D > K.

By the way, in this conventional configuration, the tap coefficient of the transversal filter 13, that is, the filter characteristic is not updated in the data signal section of the burst.
For example, the deterioration of the equalization characteristic cannot be avoided in a wireless transmission line in which the transmission line characteristic greatly varies, such as mobile radio.

In order to suppress the deterioration of the equalization characteristic, an attempt has been made to improve the follow-up characteristic to the fluctuation of the transmission channel characteristic by estimating the impulse response of the transmission channel even in the burst data signal section. This configuration is shown in FIG.
(J. G. Proakis, Digital Comm
unication, McGraw, Hill, 198
3).

The quasi-synchronous detection signal is input to the sampling circuit from the input terminal 40, and the received signal sample value y (i) is output. Note that y (i) includes a modulated wave with a symbol period T, and the sampling period is T. In the Viterbi algorithm circuit 45, a finite number of states transit every T,
In the same figure, there are four transitions. A code sequence corresponding to each state transition is input to the signal generation circuit 47. The signal generation circuit 47 generates a signal sequence of complex symbols corresponding to the input code sequence. The generated signal sequence of complex symbols is sequentially selected by the switch circuit 48 and input to the transversal filter 410. The transversal filter 410 having a common tap coefficient for all state transitions converts different input signal sequences for each state transition into respective signal estimation values and outputs them.
When the transversal filter 410 receives a signal sequence of a modulated wave that matches the transmission signal, a signal estimation value that is substantially equal to the reception signal is output. The signal estimation value is input to the subtractor 42, and the estimation error is obtained from the difference between the signal estimation value and the received signal sample value y (i). The squaring circuit 43 calculates the square of the estimation error, multiplies by -1, and outputs the result. This value is evaluated as a branch metric of the state transition selected by the switch circuit 44, and the Viterbi algorithm circuit 45
Entered in. The Viterbi algorithm circuit 45 performs signal determination and outputs the signal determination result from the output terminal 46.
The control circuit 412 receives the transversal filter 41 from the output of the signal generation circuit 47, which receives the signal determination result, and the output of the delay circuit 411, which receives the received signal sample value.
Estimate and set a filter coefficient of zero. Control circuit 4 here
Reference numeral 12 corresponds to a control unit that sets a pre-filter coefficient for the tap coefficient of the transversal filter 410. The delay circuit 410 delays the input signal by the determination delay time DT of the Viterbi algorithm circuit 45. However, D
Is a natural number. The switch control circuit 49 controls the switch circuits 44 and 48 at the same timing.

Next, the operation of the control circuit 412 to which the conventional RLS algorithm is applied will be described. The RLS algorithm will be described later. This block diagram is shown in FIG. The received signal sample value delayed by DT is input from the input terminal 50. The subtraction circuit 51 subtracts the prior signal estimation value from this signal and outputs the prior estimation error α _d (i). The multiplication circuit 52 multiplies α _d (i) by the gain vector K _d (i) and outputs a correction vector. The adder circuit 53 adds the pre-filter coefficient vector and the modified vector to update the post-filter coefficient vector. The delay circuit 54 delays the posterior filter coefficient vector by 1T, outputs it as a prefilter coefficient vector from the output terminal 56, and sets it as the tap coefficient of the transversal filter 410. In addition,
This tap coefficient corresponds to the impulse response of the transmission line. The inner product calculation circuit 55 calculates the inner product of the signal sequence of the complex symbol of the signal determination result input from the input terminal 57 and the pre-filter coefficient vector, and outputs the pre-signal estimation value. The gain generation circuit 58 generates K _d (i) from the signal sequence of the complex symbol of the signal determination result.

The gain generation circuit 58 is an inverse matrix calculation circuit 5
9 and a matrix calculation circuit 60. Inverse matrix operation circuit 59
Generates an inverse matrix P _d (i) described later. Matrix operation circuit 6
0 multiplies the vector C _d (i) is a determination signal as a vector element to be described later to the inverse matrix P _d (i). Then RL
The S algorithm will be described.

First, the signal sequence of the complex symbol of the signal determination result from the input terminal 57 is represented by a K-dimensional vector C _d (i) as shown below.

[0018]

[Equation 6] Here, a _d (i) is the signal determination result of a (i). Next, the posterior filter coefficient vector X _d (i) at time i
Is represented by a K-dimensional vector as follows.

[0019]

[Equation 7] Here, ^* represents a complex conjugate, and w (i) represents the value of the tap coefficient of the transversal filter 410, that is, the impulse response of the transmission path. The pre-filter coefficient vector at time point i is X _d (i-1).

In the method of least squares

[Equation 8] In represented posteriori estimation error e weighted sum of squares of _d (i) to estimate the Xd (i) so as to minimize. The RLS algorithm is an algorithm for sequentially performing this. X
The update algorithm of _d (i) is as follows. (Si
mon Haykin; “Adaptive Filter”
ering Theory ”, Prentice-Ha
ll, 1986)

[Equation 9] Where ^H is the complex conjugate transpose and P _d (i) is C _d (i)
Is an inverse matrix of the autocorrelation matrix of, and λ is a forgetting factor (a positive number of 1 or less). Where Kalman gain vector K _d (i)
Is equal to P _d (i) C _d (i).

By the way, in this configuration, since the transmission path is estimated based on the received signal sample value delayed by DT, the impulse response of the transmission path in the past of DT is estimated. Therefore, this delay cannot follow high-speed transmission path fluctuations that cannot be ignored, and the equalization characteristics are deteriorated.

Further, in the conventional configuration, the deterioration of the equalization characteristic is inevitable when the reception level is greatly reduced in the fading transmission line.

By the way, in TDMA, a burst having the structure shown in FIG. 2 is transmitted. This burst is composed of a training signal for initializing the equalizer and a data signal following it. If the transmission path is represented by a two-wave model with a delay time T as shown in FIG.
Actually, two bursts of the preceding wave and the delayed wave are weighted by the equation (3), noise is added, and the noise is received. Therefore, the preceding wave at each time point undergoes intersymbol interference due to the past code delayed by the time T.

Here, as an example in which a Viterbi equalizer that receives such a burst signal and performs equalization processing does not operate well, a non-minimum phase system in which the level of the preceding wave is lower than the level of the delayed wave is used. think of. That is,

[Equation 10] And

[Equation 11] Then, the trellis diagram at the last time point N when the burst length is N is shown in FIG. Assuming that the transmission line characteristic estimation circuit operates correctly and the transmission line characteristic is accurately estimated, the branch metric BR (σ _N ^s ,
σ _N-1 ^t ) is

[Equation 12] Becomes When the level of the combined received wave is low in the non-minimum phase system, the noise level often becomes larger than | h ₀ | ² . In the two state transitions branching from the same state, the branch metric does not accurately reflect the difference between the symbol sequence candidates represented by a (N) -α (N). That is, in FIG. 7, the branch metrics of the state transitions B1 and B2 from the state σ _N-1 ⁰ to the state σ _N ⁰ and the state σ _N ¹ are almost the same. Similarly, the state σ _N-1 ¹
From σ _N ⁰ and state σ _N ¹ the branch metrics of state transitions B3 and B4 are also approximately the same. Therefore, the selected branch is B1 and B2 or B3 and B.
However, the branch metric values are B1 and B2 or B.
There is almost no difference between 3 and B4, and the difference between the path metrics corresponding to both is not significant.

In the conventional equalizer, the metric calculation is terminated at this point, and the path having the maximum metric is selected and used as the decision signal. Therefore, there is a high probability that a signal decision error will occur in the final symbol of the burst. .. Further, conventionally, in order to avoid this drawback, a method of inserting a known signal into the last symbol of the burst has been adopted, but a decrease in burst transmission efficiency cannot be avoided because of transmission of the known signal.

Next, the relationship between the sampling clock and the equalization characteristic will be described. The received signal waveform without waveform distortion and noise is shown in FIG. When the timing offset of the sampling clock is 0, sampling is performed at the time of sampling 1 in FIG. Also, the timing offset is T / 2
In this case, sampling is performed at the time of sampling 2 in FIG. In order for the equalizer to operate properly, the received signal waveform must be accurately reproduced from the sample value series. However, in sampling at every symbol interval T, if there is a timing offset, waveform reproduction becomes inaccurate as described below. The received waveform of FIG. 8 is Nyquist roll-off waveform shaping, and normally the roll-off rate is a value from 0 to 1, and therefore includes a component of 1 / 2T to 1 / T in the frequency domain. .. Therefore, T
In each sampling, aliasing distortion occurs at the Nyquist frequency of 1 / 2T. This distortion depends on the sampling timing. In order to see the situation, when the waveform is reproduced by the sampling function of the sampling period T, it becomes as shown in FIG. 9 for sampling 1 and as shown in FIG. 10 for sampling 2. The original waveform is reproduced in the case of sampling 1, but the original waveform cannot be accurately reproduced if there is a T / 2 timing offset as in the case of sampling 2. Also, at the timing offset of T / 2, the average received power is apparently small.

As described above, the conventional Viterbi equalizer has a drawback that the equalization characteristic is significantly deteriorated due to the timing offset of the sampling clock because the sampling period coincides with the symbol period.

In the above-mentioned conventional configuration, since the transmission path is estimated based on the delayed received signal sample value,
The transmission line impulse response in the past was estimated. Therefore, this delay cannot follow high-speed transmission path fluctuations that cannot be ignored, and the equalization characteristics are deteriorated.

Further, the deterioration of the equalization characteristic is unavoidable when the reception level is significantly lowered on the fading transmission line.

Further, there is a high probability that a signal determination error will occur in the last symbol of the burst. Further, conventionally, in order to avoid this drawback, a method of inserting a known signal into the last symbol of the burst has been adopted, but a decrease in burst transmission efficiency cannot be avoided because of transmission of the known signal.

Further, since the sampling period is coincident with the symbol period, there is a drawback that the equalization characteristic is significantly deteriorated by the timing offset of the sampling clock.

[0032]

SUMMARY OF THE INVENTION The present invention provides an equalization method and an adaptive equalizer that eliminate the above-mentioned conventional drawbacks and can obtain excellent equalization characteristics even when the transmission line characteristics fluctuate. The purpose is to do.

[0033]

In order to solve the above-mentioned problems, the present invention takes a quasi-synchronous detection signal as an input and outputs a received signal sample value at a constant sampling cycle; and makes a transition at a predetermined cycle. A signal generation step of inputting a code sequence corresponding to each state transition and a code sequence corresponding to each state transition path, and outputting a signal sequence corresponding to each state transition and a signal sequence corresponding to each state transition path;
Outputting a signal estimation value for each state transition using an adaptive filter made up of a transversal filter having a signal sequence corresponding to each state transition as an input and using a pre-filter coefficient vector as a tap coefficient; and the received signal The branch metric obtained for each state transition using the square of the estimation error obtained by subtracting the signal estimation value for each state transition from the sample value is input, and the signal determination result using the Viterbi algorithm and the Outputting a code sequence corresponding to the state transitions and estimating a state by outputting a code sequence corresponding to each of the state transition paths; a signal sequence corresponding to each of the state transition paths, and a basis of the signal estimation value The inner product with the pre-filter coefficient vector is obtained to obtain an operation value, and this operation is performed from the received signal sample value delayed by a predetermined delay. A step of calculating a priori estimation error by subtracting, and performing an inverse matrix operation from the signal sequence corresponding to the path of each state transition, calculating a Kalman gain vector, the priori estimation error, the Kalman gain vector A control step of updating the pre-filter coefficient vector by adding a calculated value as a correction term to a pre-coefficient vector of the transversal filter, which includes a step of obtaining the correction term as a calculated value, which comprises a step of multiplying. Provided is an equalization method in a transmission path that fluctuates in mobile radio.

Further, according to the present invention, a code sequence corresponding to each state transition, in which a quasi-synchronous detection signal is inputted and a receiving means which comprises a sampling circuit for outputting a received signal sample value at a constant sampling cycle and which makes a transition at a predetermined cycle, is provided. A signal sequence corresponding to each state transition and a signal sequence corresponding to each state transition path, and a signal generation unit for outputting a signal sequence corresponding to each state transition path; connected to the signal generation unit An adaptive filter means comprising a transversal filter having a tap coefficient, which receives a signal sequence corresponding to each of the state transitions and outputs a signal estimation value for each state transition; Obtained by the branch metric operation circuit for each state transition using the square of the estimation error obtained by subtracting the signal estimation value for each state transition. Enter the branch metric, a signal decision result using the Viterbi algorithm, said each state transition and the corresponding code sequence, a state estimation means for outputting a code sequence corresponding to the path of each state transition;
From the received signal sample value with a predetermined delay, the inner product calculation value obtained by the inner product calculation of the signal series corresponding to the path of each state transition and the tap coefficient is subtracted to obtain a pre-estimation error, A multiplication value obtained by multiplying the estimation error by a Kalman gain vector obtained by performing a matrix operation of a signal sequence corresponding to each state transition path is added to the tap coefficient as a correction term, and this tap coefficient is updated. An adaptive equalizer comprising: a control means for executing the RLS algorithm;

[0035]

According to the present invention, when a transversal filter is provided for each state transition and coefficient control is performed by using the RLS algorithm so that the estimation error in each state transition is minimized, the transmission line characteristic varies. However, excellent equalization characteristics can be obtained.

[0036]

FIG. 11 shows the overall construction of the embodiment, and FIG. 12 shows the construction of the embodiment of the estimation error calculation circuit.

In FIG. 11, the quasi-synchronous detection signal is input to the sampling circuit 11-1 from the input terminal 11-0, and the received signal sample value is output. The sampling period is T. Received signal sample value I, the estimated error calculating circuit 11 ₁ for calculating an estimation error corresponding to each state transition
Is input to the ～11-2 _4. The number of the estimation error calculation circuits is the same as the number of state transitions, and here, there are four transitions. Each estimated error calculating circuit 11-2 ₁ ～11-
2 ₄ inputs the code sequence S corresponding to each state transition output from the Viterbi algorithm circuit 11-3 and the code sequence P corresponding to the path of each state transition, and the obtained estimation error is 2
A value 0 obtained by multiplying the power by -1 is sent to the Viterbi algorithm circuit 11-3 as an error corresponding to each state transition.
The Viterbi algorithm circuit 11-3 performs signal determination and outputs a determination signal from the output terminal 11-4.

In FIG. 12, in the subtraction circuit 12-0,
Transversal filter 1 from received signal sample value I
The square calculation circuit 12-2, which subtracts the signal estimation value which is the output of 2-1 and outputs the estimation error, adds -1 to the square of the estimation error.
The value 0 multiplied by is output to the Viterbi algorithm circuit 11-3. The signal generation circuit 12-3 receives the code sequence S corresponding to the state transition from the Viterbi algorithm circuit 11-3 and generates it as a symbol sequence. The transversal filter 12-1 is a filter that converts a symbol sequence corresponding to a state transition into a signal estimation value by performing a convolution operation. This signal estimation value is sent to the subtraction circuit 12-0. The signal generation circuit 12-5 receives the code sequence P corresponding to the state transition path from the Viterbi algorithm circuit 11-3 and generates it as a symbol sequence. The delay circuit 12-6 delays the received signal sample value I by a predetermined delay and outputs it. However, since it is not delayed in the training signal section, it is output as it is. The control circuit 12-4 is
Although the tap coefficient of the transversal filter 12-1 is initially estimated using the training signal and the output of the delay circuit 12-6, the symbol sequence corresponding to the state transition path and the output of the delay circuit 12-6 are also output in the data signal section. Based on this, the tap coefficient of the transversal filter 12-6 is updated in real time. Here, the RLS algorithm is applied to the control circuit 12-4, and the conventional circuit configuration shown in FIG. 5 is applied.

The Viterbi algorithm circuit 11-3 also constitutes state estimation means, the adaptive filter corresponds to the transversal filter 12-1, and the control means is the control circuit 12.
Corresponds to -4. The receiving means is the sampling circuit 11-1.
The signal generating means corresponds to the signal generating circuits 12-3, 12
Corresponds to -5. The branch metric calculation means
It corresponds to the subtraction circuit 12-0 and the square operation circuit 12-2.
Further, with the configuration of performing divided and processing time for each state transition, the estimated error calculating circuit 11-2 ₁ ～11-2 ₄
Can be aggregated into one.

Next, the code sequence corresponding to the state transition path will be described with reference to FIG. In the figure, the modulation method BP
The case is SK and the number of states is 2, which is the same as in FIG. There are two ways to select the code sequence corresponding to the state transition path: (i) a survival path connected to a branching state, and (ii) a code sequence including a state transition and a survival path. (I)
In the case of, in the state transitions B1 and B2 branching from the state σ _i ⁰ , the code sequence corresponding to the state transition path is path 0, that is, the code sequence corresponding to the surviving path connected to σ _i ⁰ . Similarly, the state transitions B3 and B branching from the state σ _i ¹
In the case of 4, the surviving path connected to σ _i ¹ is the code sequence corresponding to path 1. In this case, the delay circuit 12-6 is
The received signal sample value must be delayed by 1T.
On the other hand, in the case of (ii), the code sequence corresponding to the path of the state transition B1 is a code sequence including B1 and path 0, and the code sequence obviously differs depending on the state transition. In this case, the delay circuit 12-6 must output the received signal sample value I without delaying it.

As is clear from the above description, when the code sequence corresponding to the state transition path is the surviving path connected to the branching state, the transmission path estimation may be performed according to the number of states, and the calculation amount is reduced. it can.

FIG. 14 is a diagram for explaining the effect of the present invention obtained by the apparatus of the embodiment shown in FIGS. 11 and 12, and shows the average bit error rate characteristic (BER) with respect to the average E _b / N ₀ in digital mobile communication. This is the result obtained by computer simulation. The simulation conditions were a QPSK modulation method, a transmission rate of 40 kb / s, a maximum Doppler frequency of 160 Hz, and a two-wave Rayleigh model with a two-wave delay time difference of 1 T was used as a propagation path model. Also, □
The mark indicates the characteristic according to the constitution of the present invention, and the mark ● indicates the characteristic according to the conventional constitution. In the present invention, since the impulse response of the transmission line at the present time is estimated, it is possible to follow the fluctuation of the transmission line, and as shown in the figure, it is understood that the equalization characteristic is improved as compared with the conventional method.

FIG. 15 is a block diagram showing the structure of another embodiment of the present invention. Here, an example in which there are two branch diversity branches and the number of state transitions is four is shown. In the figure, a quasi-synchronous detection signal for each diversity branch is input from the input terminal 15-0 and the input terminal 15-2. Sampling circuit 15-1 and sampling circuit 15-
3 samples the quasi-synchronous detection signal for each diversity branch at the sampling cycle T, and outputs the received signal sampling value for each diversity branch. Each received signal sample values I _1, I ₂ is the estimation error operation circuit 15-4 ₁ to 1 for calculating an estimation error corresponding to each state transition in each diversity branch
5-4 _4, is input to 15-4 ₅ ～15-4 _8. In each diversity branch, the number of estimation error calculation circuits is the same as the number of state transitions. Each estimation error calculation circuit 15-4
₁ ～15-4 _4, 15-4 ₅ ～15-4 ₈ includes a code sequence S corresponding to each state transition output from the Viterbi algorithm circuit 15-6, code sequence P corresponding to the path of each state transition Is input and the value 0 obtained by multiplying the square of the obtained estimation error by -1 is output to the adder circuits 15-5 ₁ to 15-5 ₄ . Adding circuit 15-5 ₁ ～15-5 ₄ Viterbi algorithm a value obtained by multiplying by -1 square sum of the estimation error for each diversity branch for each state transition, as a branch metric corresponding to each state transition It is sent to the circuit 15-6. The Viterbi algorithm circuit 15-6 performs signal determination and outputs a determination signal from the output terminal 15-7. Here the estimated error calculating circuit 15-4 ₁ ～15-4 _4, 15
4 ₅ ～15-4 ₈ is a circuit configuration similar to that shown in FIG. 12 described above.

Since the diversity reception system is extended in this manner, the transmission line characteristics fluctuate at high speed, and excellent equalization characteristics can be obtained even in the case of a transmission line with a lot of noise.

In the embodiment configuration of the invention shown in FIG. 11,
Only the configuration of the estimation error calculation circuit 11-2 is modified, and an example of the configuration of the estimation error calculation circuit 16-0 is shown in FIG.

The difference between the estimation error calculation circuit 16-0 and the estimation error calculation circuit 11-2 is that the signal generation circuit 1 is provided between the signal generation circuit 16-10 and the transversal filter 16-5.
6-9 and the control circuit 16-4 between the signal conversion circuit 16-
7, 16-8 is inserted.

In the following, this signal conversion circuit 16-7, 1
6-8 will be described in detail.

It is assumed that the condition is a non-minimum phase system in which the constraint length K is 2 and the transmission path is represented by a two-wave model with a delay time T, and the level of the preceding wave is low. Therefore, if the metric calculation is completed at the last time point N of the burst, the probability of a decision error occurring at the last symbol of the burst increases as described above. On the other hand, in the present embodiment, by using the symbol series output from the signal conversion circuits 16-7 and 16-8, the equalization process is extended by T and the signal determination is performed. This signal determination will be described separately when there is no signal after the burst and when there is a next burst immediately after the burst and a known signal is at the beginning of the burst.

First, the case where there is no signal after the burst will be described.

Since the transmission signal is not sent at the extended time point N + 1, a correct value can be obtained even if the transition signal sequence is generated based on the state transition trellis and the branch metric is calculated as in the conventional equalizer. I can't.

Therefore, at time N + 1, the expected signal α
(N + 1) = 0 is generated by the signal conversion circuits 16-7 and 16-8. The branch metric is calculated with this symbol sequence as {α (N), 0}. Further, it is assumed that the Viterbi algorithm operation circuit 11-3 is provided with a new state σ _{N + 1} ² and is merged with this new state at the time point N + 1. This operation is shown in FIG.

[0052] Condition sigma _N state transition B5 from ⁰ to the state σ _{N + 1} ^2, and state sigma state from _{N ¹} σ _{N +} ^{1 2} corresponds to the state transition B6 for branch metric BR (sigma
_{N + 1} ² , σ _N ^s ) is

[Equation 13] Becomes This branch metric has (σ _N ^s , σ _N-1
^t ), the difference a (N) -α (N) between the actual signal a (N) and the estimated signal α (N) at time N is calculated as BR (σ in Equation (12).
_{Since N} ^s , σ _N-1 ^t ) appears more clearly, the difference in α (N) is reflected in the path metrics. Therefore, from the state transitions B5 and B6, the transition metric J _{N + 1} (σ _{N + 1}
² , the symbol error at the end of the burst can be reduced by selecting the signal with the maximum value of ² , σ _N ^s ) and making the signal determination.

Secondly, a case where there is a next burst immediately after the burst and a known signal is present at the head of the burst will be described.

Assuming that each state is merged with the state corresponding to the known signal of the next burst, the assumed signal sequence α (N +
1) using a known signal, the signal conversion circuits 16-7, 16-
The branch metric corresponding to the state transition is calculated as the estimated signal sequence {α (N), α (N + 1)} generated in 8. This operation is shown in FIG. Note that here, as an example, a case of α (N + 1) = − 1 is shown. State transition B7 from state σ _N ⁰ to state σ _{N + 1} ⁰ , and state σ _N
^{If the} signal determination is performed by selecting the one having the maximum transition metric from the state transitions B8 from ¹ to the state σ _{N + 1} ⁰ , the symbol error at the end of the burst can be reduced.

Note that, here, from the last symbol of the burst to the branch metric which is extended by one symbol, the impulse response of the transmission path is (K-1) T.
When there is a time spread of, it is necessary to extend the state by K−1 symbols and perform state estimation.

Although the embodiment described above is for BPSK modulation, the present invention can be similarly applied to other PSK modulation and QAM modulation.

FIG. 19 is a diagram for explaining the effect of the present invention, which is the result of computer simulation of the average bit error rate characteristics with respect to the average E _b / N ₀ in digital mobile communication. The simulation conditions are as follows: modulation method is QPSK method, transmission rate is 40 kb / s, RLS algorithm is applied to channel estimation, and forgetting factor λ is 0.9.
And the complex amplitude of the preceding wave is 0.5 as a propagation path model,
A static two-wave model was used in which the complex amplitude of the delayed wave was 1.0. Also, it is assumed that no signal comes after the burst.
Here, □ indicates characteristics when a known signal is not inserted in the last symbol of the burst (conventional technology), and X indicates characteristics when a known signal is inserted in the last symbol of the burst (conventional technology). .. In addition, the mark ◯ shows the characteristics according to the embodiment of the present invention.

As shown in the figure, in the configuration of this embodiment, the equalization characteristic is improved as compared with the case where the known signal is not inserted in the last symbol of the burst in the related art, and the known symbol is known in the last symbol of the burst. It is possible to obtain equalization characteristics equivalent to the case of inserting a signal. Therefore, the last symbol of the burst can be used for transmitting information, and the transmission efficiency of the burst can be increased accordingly.

The block configuration shown in FIG. 20 shows another configuration example of the configuration of the estimation error calculation circuit 11-2 with the sampling cycle of the sampling circuit 11-1 set to a fractional interval in FIG. The received signal sample value is input from 20-1. Hereinafter, a case where the sampling period is T / 2 will be described as an example. The Viterbi algorithm circuit 11-3 corresponding to the state estimating means outputs the code sequence S corresponding to each state transition and the code sequence P corresponding to the path of each state transition, and outputs them to the signal generating circuits 20-5 and 20-6. You are typing. In the signal generation circuits 20-5 and 20-6,
A symbol sequence corresponding to the input code sequence is generated.
Since the modulated wave reproducing circuits 20-7 and 20-8 generate modulated waves in each sampling cycle, the signal generating circuit 20-
Filter the output of 5, 20-6. Here, the signal generating circuits 20-5 and 20-6 and the modulated wave reproducing circuit 20-
Reference numerals 7 and 20-8 correspond to signal generating means. The reproduced modulated wave for each sampling period which is the output of the modulation / reproduction circuit 20-7 is a fractionally-spaced transversal filter 20-13.
Entered in. Fractionally spaced transversal filter 2
0-13 performs a convolution operation of the tap coefficient and the reproduced modulated wave, and outputs a signal estimation value. When a reproduced modulated wave that matches the transmission signal is input to the fractionally-spaced transversal filter 20-13, a signal estimation value that is substantially equal to the reception signal is output. The signal estimated value is the subtraction circuit 20-
The estimated error signal α ( _if ) is obtained for each sampling period from the difference from the received signal sample value. However, i = 0, 1/2, 1, 3/2 ... The square calculation circuit 20-10 calculates the square of the estimation error signal, multiplies by -1, and outputs the result. The metric circuit 20-11 is for converting from the square of the estimation error signal output twice per symbol to one branch metric per symbol. Various methods are conceivable as the method, such as combining α (i) and α (i-1 / 2) with appropriate weighting. Here, for example, − {| α (i) | ² + | α (i−1 / 2) | ² } is calculated and output as the branch metric at time i. The output of the metric circuit 20-11 is input to the Viterbi algorithm circuit 11-3 shown in FIG. The control circuit 20-12 uses the output of the modulated wave regenerating circuit 20-8 and the received signal sample value delayed by the delay circuit 20-14 to perform transmission by the RLS algorithm so as to minimize the magnitude of the estimation error signal. Path estimation is performed and the pre-filter coefficient vector is set as a tap coefficient in the fractionally-spaced transversal filter 20-13. Here, the control circuit 20-12 corresponds to a control means.

FIG. 21 shows a block diagram of the fractionally-spaced transversal filter 20-13. The figure shows the case where the sampling period is T / 2, the delay time of the delayed wave is 1T or less, and the number of taps is three. The output of the modulated wave reproducing circuit 20-8 is b ( _if ). Input terminal 21-0 to b
( _If ) is input. The delay elements 21-1 and 21-2 delay the input by T / 2. The multiplication circuit 21-3 has b
(I _f ) and b ( _if −I / 2) in the multiplication circuit 21-4,
B ( _if- 1) is set in the multiplication circuit 21-5. Also, the pre-filter coefficient vector is tap coefficients w0, w
1 and w2 are set in the multiplication circuit 21-3, the multiplication circuit 21-4, and the multiplication circuit 21-5. The multiplication results of the respective multipliers are added up by the adder 21-6, and the output terminal 21
It is output from -7.

Next, the modulated wave reproducing circuits 20-7, 20-8
The operation will be described by taking as an example the case where a root roll-off filter is used for the transmission filter and the reception filter. At this time, the modulated wave reproducing circuits 20-7 and 20-8
Acts as a roll-off filter and its output b ( _if )
Is the output of the roll-off filter sampled at T / 2. When b ( _if ) is expressed by an equation

[Equation 14] Becomes However, h _R (t) is the impulse response of the cosine roll-off filter. h _R (t) satisfies the Nyquist condition,

[Equation 15] Is. Therefore, when i _f is an integer, b (i _f ) is α
It becomes _d (i). However, when i _f is a half integer, (1
It must be calculated using equation (4). At this time, it depends on α _d (i) of the infinite past and the infinite future, so it is impossible to obtain the exact value, but in order to reduce the amount of calculation considering that h _R (t) is attenuated as it moves away from the origin. It is approximated as follows using only adjacent complex amplitudes.

[0062]

[Equation 16] Next, regarding the relationship between fractional interval sampling and equalization characteristics,
22 to 24 will be described as an example of a reception signal waveform having no sampling period T / 2, waveform distortion and noise. When the timing offset of the sampling clock is 0, sampling is performed at the time of sampling 1 in FIG. When the timing offset is T / 4, sampling is performed at the time of sampling 2 in FIG. When the waveform is reproduced with the sampling function of sampling period T / 2,
FIG. 23 shows the case of sampling 1 and FIG. 24 shows the case of sampling 2. It can be seen that the original waveform can be accurately reproduced even if there is a timing offset. This is because even if aliasing occurs at the Nyquist frequency 1 / T due to the T / 2 sampling interval, aliasing distortion does not occur because the sampled received wave does not include frequency components of 1 / T or higher. In this way, the sample values sampled by the fractional intervals do not deteriorate even with the timing offset. Therefore, in the configuration of the above-described embodiment that can generate the regenerated modulated wave for each fractional interval and the received signal sample value sampled by the fractional interval, and to compare the two for each fractional interval, excellent equalization characteristics even when there is a timing offset. can get.

Computer simulation was performed to confirm the effect of the present invention. The result is shown in FIG. The modulation method is OPSK modulation with a roll-off rate of 0.5, the transmission line model is a one-wave static model, and E ₀ / N ₀ = 8 dB. The RLS algorithm is applied to the channel estimation, and the forgetting factor is set to 0.8 in the conventional technique and 0.9 in the present invention. The ● and ○ marks are the results of this example and the conventional example, respectively.

As is clear from this result, the deterioration due to the timing offset can be suppressed as compared with the conventional technique.

The estimation error calculation circuit 26-0 shown in FIG.
11 shows another configuration example of the estimation error calculation circuit 11-2 in the block diagram of the apparatus shown in FIG.

The difference between the estimation error calculating circuit 26-0 and the estimation error calculating circuit 20-0 shown in FIG. 20 is that the signal generating circuit 26 is provided between the signal generating circuit 26-9 and the modulated wave reproducing circuit 26-13. The signal converting circuits 26-11 and 26-10 are inserted between the -8 and the modulated wave reproducing circuit 26-12.

This signal conversion circuit 26-10, 26-11
Is exactly the same as the signal conversion circuits 16-7 and 16-8 in FIG. Therefore, the symbol error at the end of the burst can be reduced.

The control circuit 97 shown in FIG. 27 shows a circuit configuration example of the control circuit 12-4 shown in FIG. 12 which is a component of the estimation error calculation circuit 11-2 in the apparatus of the embodiment shown in FIG.

The control circuit 27-0 has the same parts as those of the control circuit 412 shown in FIG.

The control circuit 27-0 shown in FIG. 27 estimates the transmission path by the above-mentioned RLS algorithm.

Here, the symbol series corresponding to the state transition from the input terminal 57 is represented by a k-dimensional vector C _m (i).

[0072]

[Equation 17] Here, a _m (i) is a complex symbol candidate corresponding to each state transition.

RLS algorithm formulas (9-a) to (9-
Since d) includes matrix calculation, the substantial numerical calculation amount increases substantially in proportion to the square of the tap number M. But,
Since the signal vector C _m (i) input from the input terminal 57 is a signal containing no noise output from the signal generation circuit 12-5, its autocorrelation matrix P _m (i) is the received signal sample value y ( It does not depend on i) and is constant after a sufficient time has passed.

Therefore, the inverse matrix P according to equation (9-d)
Instead of updating calculation of _{m (i), P m (} i) = with the P _0, the formula (9-a) and K from the equation _{(9-d) m (i} ) = P
_{Using m} (i) C _m (i), instead of equation (3),

[Equation 18] Can be used. Where K _m (i) is the Kalmangen vector. Note that P ₀ is a fixed matrix, which can be theoretically obtained in advance by the ensemble average of the modulated signal. Further, the value of P _m (i) at the end of training may be used as P ₀ .

FIG. 27 shows a circuit configuration using a fixed matrix instead of the inverse matrix calculation. The control circuit 27-0 uses the fixed matrix P _{0 as} the inverse matrix operation circuit array of the control circuit 412 of FIG.
It has been replaced with.

As is clear from the above description, the amount of calculation can be reduced.

The control circuit 28-0 shown in FIG. 28 shows another circuit configuration of the control circuit 12-4 shown in FIG. 12 which is a constituent element of the estimation error calculation circuit 11-2 in the apparatus of the embodiment shown in FIG. ..

In the control circuit 28-0, the same parts as those of the control circuit 412 shown in FIG. 5 are designated by the same reference numerals.

The control circuit 28-0 shown in FIG. 28 is different from the control circuit 27-0 shown in FIG. 27 in that the matrix calculation circuit 28-1 is provided between the delay circuit 54 and the inner product calculation circuit 55. Instead of the filter coefficient vector, the pre-filter coefficient vector multiplied by the transition matrix is output from the output terminal 56.

The principle of the transmission path estimation algorithm in the control circuit 28-0 will be described below.

[Formula 19] The signal z (t) represented by is described as an example. Note that s (t) is a signal before being deteriorated by noise, and n ₂ (t) is additional noise.

Here, when the sampling value of z (t) when the sampling period is T is z (i) and s (kT) is estimated based on z (i), the conventional minimum two The difference between multiplication and this algorithm is explained. Note that the data substantially stored in the algorithm is from the present time to the past ζ, and the data after that is forgotten. This ζ is called a time constant.

In the conventional least squares method, s (t) is set for the time constant ζ.
Is assumed to be constant and {s (k)) is estimated by averaging {z (i)} in the section of kT−ζ ≦ t ≦ kT. FIG. 29 shows the state of estimation by the least square method with ζ = 5T. In the figure, the dotted line is the locus of s (t), and the ∘ mark indicates the value of z (i). Here, the parallel line of the horizontal axis having the value of the estimated value s _{e ′} (kT) of s (kT) is shown by a one-dot chain line. As is clear from the figure,
s _{e ′} (kT) is the average value of {z (i)} in the section of kT−ζ ≦ t ≦ kT. When estimating s {(k + 1) T}, {z in the section of (k + 1) T-ζ ≦ t ≦ (k + 1) T
(I)} is averaged. Repeat this operation for s (h
Estimate T), h = k + 2, .... From this figure, ζ
It can be seen that if s is reduced, it is possible to follow the temporal variation of s (t). However, if ζ is set too small,
Since it causes numerical divergence, there is a limit to the followability.

The present algorithm is such that s (t) during the time constant ζ.
Is a linear function with respect to time, kT-ζ ≦ t ≦
s (kT) is estimated by performing linear approximation in the kT section. ζ =
FIG. 30 shows the state of estimation by the present algorithm with 5T. In the figure, it is the locus of the dotted line s (t), and the circle indicates z
Indicates the value of (i). The straight line estimated here is shown by a dashed line. The value of this straight line at t = kT is the estimated value s _{e ′} (kT) of s (kT). When estimating s {(k + 1) T}, the section of (k + 1) T-ζ ≦ t ≦ (k + 1) T is linearly approximated, and the value at t = (k + 1) T of this straight line is used as the estimated value. Hereinafter, this operation is repeated and s (hT), h = k
Estimate +2, ... By comparing FIG. 29, it can be said that the present algorithm can accurately estimate when the fluctuation is faster than the conventional least squares method, and is excellent in followability.

Further, the present algorithm can predict a signal at a future time point by extrapolating the estimated straight line. That is, the present time and kT, increase per an estimate s _e (kT), T the time of the time when the (linear gradient) is defined as s _e ⁽¹⁾ (kT), 1T future s _e (kT) + S
_It can be predicted as _e ⁽¹⁾ (kT). However, it is assumed here that the slope of the straight line does not change. Hereinafter, this is expressed using a matrix. Quadratic vector s (k)

[Equation 20] S (k) of 1T future, that is, s (k + 1)
To predict

[Equation 21] It is equivalent to multiplying the 2 × 2 matrix Φ _s shown in from the left. This calculation does not change the slope, and only the estimated value of the signal is _se
⁽¹⁾ Increase by (kT). Similarly, if Φ _s ^(L) is multiplied, LT
You can predict the future.

This algorithm is applied to channel estimation. In other words, the transmission line impulse response is assumed to change as a linear function with respect to time for estimation. Extending equation (20), the post-filter coefficient vector X
_ext (i) using a 2K dimensional vector,

[Equation 22] Represents. Here, w _m ⁽¹⁾ (i) represents the first-order time derivative of the tap coefficient of the transversal filter 12-1, that is, the first-order time derivative of the transmission path impulse response. Next, the post-filter coefficient vector X _ext (i) is subjected to an inner product operation so that the signal estimated value can be calculated.
When the state transition symbol sequence input from 9 is represented by a 2K dimensional vector C _ext (i),

[Equation 23] Becomes Further, by expanding the equation (21), the transition matrix Φ of 2K × 2K is

[Equation 24] Is shown.

Here, Φ _kp is the k-th row and p-th column matrix element of Φ. In the RLS algorithm, X _m (i-1) corresponds to the pre-filter coefficient vector, but in this algorithm, Φ X _ext (i -1) corresponds to the pre-filter coefficient vector. Due to this change, the post-filter coefficient vector X
The update algorithm of _ext (i) is (9-a) to (9-d)
For the RLS algorithm represented by the formula,

[Equation 25] It can be calculated by replacing Note that P _ext (i) is the inverse matrix of the autocorrelation matrix of C _ext (i).

Next, the post filter coefficient vector X
Describe the simplification of the update algorithm of _ext (i). P _ext (i) does not depend on (1) the received signal sample value y (i), and becomes (2) a constant value after a sufficient time has elapsed. So instead of updating P _ext (i),

[Equation 26] Is approximated by. Note that P ₀ is a fixed matrix, which can be theoretically obtained in advance by the ensemble average of the modulated signal. Further, the value of P _ext (i) after the training may be used as P ₀ .

In such a circuit configuration, unlike the conventional configuration, the transmission path is estimated based on the received signal sample value y (i) which is not delayed, so that the impulse response of the current transmission path is estimated. Since the transmission path estimation is performed by the adaptive algorithm which is capable of performing and has excellent followability, the followability is improved and the equalization characteristic can be significantly improved.

Although the algorithm has been described here by assuming that the transmission path impulse response varies linearly with time, X _ext (i ), C _ext (i) and the transition matrix Φ can be easily accommodated.

FIG. 31 shows the control circuit 28-0 shown in FIG.
FIG. 12 is a diagram for explaining the effect of the apparatus shown in FIG. 11 having the estimation error calculation circuit 11-2 using the above, in which the average bit error rate characteristic (BER) with respect to the average E _b / N ₀ in digital mobile communication is obtained by computer simulation. It is the result. The simulation condition is that the modulation method is QPS.
K system, transmission speed is 40 kb / s, maximum Doppler frequency is 1
60Hz, 2T delay time difference 1T as a propagation path model
The two-wave Rayleigh model of Further, the square marks show the characteristics according to the constitution of the present invention, and the ● marks show the characteristics according to the conventional constitution. In the present invention, since the impulse response of the current transmission path is estimated and the transmission path is estimated by the adaptive algorithm having excellent followability, it is possible to follow the fluctuation of the transmission path at high speed, and as shown in the figure, the conventional method is used. It can be seen that the equalization characteristic is significantly improved compared to.

Although the embodiment using the different adaptive filters for the state transitions has been described above, the embodiment using the common adaptive filter for each state transition is shown in FIG. It is a block diagram showing.

Here, the description will be made by taking the two-branch diversity as an example, but the same applies to the case of three or more branches.

[0093] In the figure, the input terminal 32-1 _1, 32
The quasi-synchronous detection signal from 1 ₂ is the sampling circuit 32-
2 _1, input to 32-2 _2, the received signal sample values y
₁ (i) and y ₂ (i) are output, and the correlators 32-3 are respectively output.
_1, 32-3 ₂ and subtracting circuit 32-5 _1, 32-5 ₂
Entered in. Correlator 32-3 _1, 32-3 ₂ estimates the impulse response of the transmission path of each branch by a known signal included in the transmission signal is set at the impulse response of each branch. The filter characteristic of the transversal filter is not updated in the burst data signal section.

[0094] each subtraction circuit 32-5 _1, at 32-5 _2,
Each received signal sample values y ₁ (i), and subtracts each filter output from the y ₂ (i), 2 square circuit 32-6 ₁ obtained for each estimated error for each branch is input to 32-6 ₂ ..
The estimation error squared by each of the squaring circuits 32-6 ₁ and 32-6 ₂ and multiplied by -1 is input to the combining circuit 32-7 and summed, and the sum of squares of the absolute value of the estimation error is added by -1. Is input to the Viterbi algorithm circuit 32-11 via the same switch circuit 32-10 as the conventional one.
In the Vitaville algorithm circuit 32-11, a finite number of states make transitions every cycle T, but here, four transitions are shown as an example. The signal generation circuit 32-12, to which the code sequence corresponding to each state transition is input, generates the signal sequence corresponding to each input code sequence, and the switch circuit 32-9.
The transversal filter 32-4 ₁ for each branch are sequentially select each signal sequence, and sends it to 32-4 _2.
The switch control circuit 32-8 controls the switch circuit 32-9 and the switch circuit 32-10 at the same timing.

[0095] In this embodiment, the transversal filter 33-4 ₁ of each diversity branch, 33-4 _2,
A common tap coefficient is used for all state transitions, and different signal sequences for each state transition are converted into respective signal estimation values and output. The process of outputting the signal estimation value is
For example, it is performed by convolving the complex amplitude of the signal sequence with the tap coefficient of the transversal filter.

The value obtained by multiplying the sum of squares of the estimation error output from the synthesis circuit 33-7 by -1 is the switch circuit 33-1.
It is evaluated as an error of the state transition selected by 0 and input to the Viterbi algorithm circuit 33-11. The Viterbi algorithm circuit 33-11 performs signal determination and outputs the determination signal from the output terminal 33-13.

With such a structure, it is possible to suppress the deterioration due to the decrease in the level of the received signal as compared with the conventional technique.

FIG. 33 shows an embodiment in which the signal conversion circuit 33-13 is inserted between the signal generation circuit 32-12 and the switch circuit 32-9. The signal conversion circuit 33-13 operates similarly to the signal conversion circuits 16-7 and 16-8 in FIG. Similar to the embodiment shown in FIG. 16, this embodiment can suppress the signal determination error of the last symbol of the burst.

[0099] Figure 34 is a transversal filter 32-4 ₁ in the embodiment of FIG. 32, 32-4 ₂ type fractionally spaced transversal filter 34-4 _1, replaced by 34-4 _2, the signal generating circuit 32-12 A modulated wave reproducing circuit 34-15 is inserted between the switch circuit 32-9 and the switch circuit 32-9, and between the squaring circuits 32-6 ₁ and 32-6 ₂ and the adding circuit 32-7.
This is an embodiment in which the metric circuits 34-7 ₁ and 34-7 ₂ are inserted. However, sampling circuit 34-2 _1, 34
The sampling period of −2 ₂ is shorter than the symbol period T, and the metric circuits 34-7 ₁ and 34-7 ₂ operate similarly to the metric circuit 20-11 of FIG. With such a configuration, it is possible to suppress the deterioration due to the timing offset as described in FIG.

FIG. 35 shows the modulated wave reproducing circuit 3 shown in FIG.
This is an embodiment in which the signal conversion circuit 35-15 is inserted between the 4-15 and the signal generation circuit 35-14. The present embodiment can suppress the deterioration due to the timing offset and suppress the signal determination error of the last symbol of the burst.

FIG. 36 is a block diagram showing the structure of another embodiment of the present invention. It should be noted that although two-branch diversity is described here as an example, the same applies to the case of three or more branches.

[0102] In the figure, the input terminal 36-1 _1, 36-
The quasi-synchronous detection signal from 1 ₂ is the sampling circuit 36-
2 _1, input to 36-2 _2, the received signal sample values y
_{1 (i), y 2 (} i) are output, respectively the estimated error calculating circuit 36-3 _1, is input to 36-3 _2. Estimated error calculating circuit 36-3 _1, 36-3 ₂ configuration, FIG. 12, FIG. 1
6, the case of FIG. 20 is possible. Each estimated error calculating circuit 36-3 _1, 36-3 _second delay circuit 12-6,16-
3, 20-14 delay the DT time. Estimated error calculating circuit 36-3 _1, the determination signal output from the Viterbi algorithm circuit 36-7 is input to the input terminal P of 36-3 _2,
The branch metric is output from the output terminal O. In the adder circuit 36-4, the sum of branch metrics for each diversity branch is input to the Viterbi algorithm circuit 36-7 via the switch circuit 36-5. In the Viterbi algorithm circuit 36-7, a finite number of states make a transition for each cycle T. Here, four transitions are shown as an example. The code sequence corresponding to each state transition is input to the estimation error calculation circuit via the switch circuit 36-9. Here, the switch control circuit 36-6 controls the switch circuits 36-5 and 36-9 at the same timing.

In the present embodiment, the transversal filter of each diversity branch has a common tap coefficient for any state transition, and a signal sequence different for each state transition is converted into each signal estimation value and output. ..

The process of outputting the signal determination value is performed, for example, by performing a convolution operation on the complex amplitude of the tap coefficient of the transversal filter.

With such a structure, it is possible to suppress the deterioration due to the decrease in the level of the received signal, as compared with the prior art. Further, the estimated error calculating circuit 36-3 _1, 36
When employing the structure shown in FIG. 16 -3 _2, it is possible to further suppress the signal decision error of the last symbol of a burst, when employing the configuration shown in FIG. 20, it is possible to suppress degradation due to timing offset, Figure 26 By adopting the configuration shown in, it is possible to suppress the signal determination error of the last symbol of the burst and suppress the deterioration due to the timing offset.

FIG. 37 shows a signal conversion circuit 37- between the switch circuit 17 and the signal generation circuit 16 of the prior art shown in FIG.
9 is an example in which 9 is inserted. With this configuration,
It is possible to suppress the signal determination error of the last symbol of the burst.

FIG. 38 shows a modulated wave reproducing circuit 38 between the switch circuit 17 and the signal generating circuit 16 of the prior art shown in FIG.
-10 is inserted, and the square operation circuit 110 and the switch circuit 1
4 is an embodiment in which a metric circuit 38-5 is inserted between 4 and 4. However, the sampling period of the sampling circuit 38-2 is shorter than the symbol period. With such a configuration, deterioration due to the timing offset can be suppressed.

FIG. 39 shows an embodiment in which a signal converting circuit 39-10 is inserted in the modulated wave reproducing circuit 38-10 and the signal generating circuit 38-9 having the configuration shown in FIG. With such a configuration, it is possible to suppress the deterioration due to the timing offset and suppress the signal determination error of the last symbol of the burst.

FIG. 40 shows a signal conversion circuit 40- between the conventional switch circuit 48 and the signal generation circuit 47 shown in FIG.
9 is an example in which 9 is inserted. With this configuration,
It is possible to suppress the signal determination error of the last symbol of the burst.

FIG. 41 shows a modulated wave reproducing circuit 41 between the switch circuit 48 and the signal generating circuit 47 of the prior art shown in FIG.
-10 is inserted, and the square operation circuit 43 and the switch circuit 44 are inserted.
In this embodiment, a metric circuit 41-5 is inserted between the two. However, the sampling period of the sampling circuit 41-2 is less than the symbol period. With such a configuration, deterioration due to the timing offset can be suppressed.

FIG. 42 shows an embodiment in which the signal conversion circuit 42-10 is inserted between the modulated wave reproduction circuit 41-10 and the signal generation circuit 41-9 in the configuration shown in FIG. With such a configuration, it is possible to suppress the deterioration due to the timing offset and suppress the signal determination error of the last symbol of the burst.

In the embodiments shown in FIGS. 36, 40, 41 and 42, the control circuit shown in FIG. 43 can be used in order to enhance the followability to the fluctuation of the transmission line.

In FIG. 43, the input terminal (C) 43-1
Is connected to a signal generation circuit, and the signal sequence of the signal determination result in the Viterbi algorithm circuit is input. The input terminal (R) 43-2 is connected to the delay circuit, and the received signal sample value delayed by DT is input. Output terminal (F) 43-
11 is connected to a transversal filter.

The subtraction circuit subtracts the prior signal estimation value from the DT-delayed received signal sample value signal input from the input terminal 43-2 and outputs the prior estimation error α _ext (i) to the multiplier 43-5. .. The multiplier 43-5 multiplies the pre-estimation error α _ext (i) by the gain vector K _ext (i) and outputs a correction vector. The adder circuit 43-6 adds the pre-filter coefficient vector and the modified vector, and updates the post-filter coefficient vector. Delay circuit 43-7
Delays the post-filter coefficient vector by 1T and sends it to the matrix operation circuit 43-8. The matrix operation circuit 43-8 is
The post-filter coefficient vector delayed by 1T is multiplied by the transition matrix Φ described above, and output as a pre-filter coefficient vector.

By the way, this pre-filter coefficient vector is estimated based on the DT-delayed received signal sample value, and corresponds to the DT-delayed transmission impulse response. Therefore, this pre-filter coefficient vector is fetched into the matrix operation circuit 43-10, multiplied by Φ ^D to predict the current transmission impulse response and output to the output terminal 43-11 to set the filter coefficient of the transversal filter. .

The inner product calculating circuit 43-9 has an input terminal 43-
1 calculates the inner product of the signal sequence of the signal determination result input from 1 and the pre-filter coefficient vector output from the matrix operation circuit 43-8, and the subtraction circuit 43 as the pre-signal estimation value.
-4. Further, the gain generation circuit 43-12 is
Gain vector K _ext (i) from the signal sequence of the signal determination result
Is generated and sent to the multiplier 43-5.

With such a circuit configuration, the impulse response of the current transmission line can be predicted, and the transmission line is estimated by an adaptive algorithm having excellent followability. Therefore, the followability is improved and the equalization characteristic is improved. Can be greatly improved.

[0118]

As described above, according to the present invention, a transversal filter is provided for each state transition, and coefficient control is performed by using the RLS algorithm so that the estimation error in each state transition is minimized. As a result, it is possible to obtain a method and an adaptive equalizer for compensating and equalizing the deterioration of transmission characteristics due to intersymbol interference.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a conventional Viterbi equalizer.

FIG. 2 is a diagram showing a configuration example of a burst.

FIG. 3 is a trellis diagram in a two-wave model of the BPSK method.

FIG. 4 is a block diagram showing another configuration example of a conventional Viterbi equalizer.

5 is a block diagram showing a configuration example of a conventional control circuit shown in FIG.

FIG. 6 is a diagram showing a transmission path represented by a two-wave model with a delay time T.

FIG. 7 is a trellis diagram in a BPSK two-wave model at the end of a burst.

FIG. 8 is a diagram showing how a received signal is sampled at symbol periods.

9 is a diagram showing a reproduction reception waveform of sampling 1 shown in FIG.

10 is a diagram showing a reproduction reception waveform of sampling 2 shown in FIG.

FIG. 11 is a block diagram showing the overall configuration of the device of the present invention.

12 is a block diagram showing a specific configuration of the estimation error calculation circuit shown in FIG.

FIG. 13 is a trellis diagram in the two-wave model of the BPSK method in the code sequence corresponding to the state transition path.

FIG. 14 is a diagram comparing the average bit error rate characteristic with a conventional example in order to explain the effect of the invention obtained by the device of the embodiment shown in FIGS. 11 and 12;

FIG. 15 is a block diagram showing another configuration example of the device of the present invention.

16 is a block diagram showing another configuration example of the estimation error calculation circuit in the block configuration diagram shown in FIG.

FIG. 17 is a trellis diagram for explaining the operation of the apparatus of the embodiment shown in FIG.

FIG. 18 is another trellis diagram for explaining another operation of the apparatus of the embodiment shown in FIG.

19 is a diagram showing an average bit error rate characteristic when the signal generating means in the apparatus of the embodiment shown in FIG. 11 is limited.

20 is a block diagram showing another configuration example of the estimation error calculation circuit in the device of the embodiment shown in FIG.

FIG. 21 is a block diagram showing a configuration example of the fractionally-spaced transverse filter shown in FIG. 20.

FIG. 22 is a diagram showing how a received signal is sampled at a T / 2 cycle with respect to the relationship between fractional interval sampling and equalization characteristics.

FIG. 23 is a reproduction reception waveform diagram of sampling 1 shown in FIG. 22.

FIG. 24 is a reproduction reception waveform diagram of sampling 2 shown in FIG. 22.

FIG. 25 is a diagram showing bit error rate characteristics when the signal generating means in the apparatus of the embodiment shown in FIG. 11 is limited otherwise.

FIG. 26 is a block diagram showing still another configuration example of the estimation error calculation circuit in the device of the embodiment shown in FIG.

27 shows a configuration example of the control circuit 12-4 shown in FIG. 12 in the estimation error calculation circuit 11-2 in the apparatus of the embodiment shown in FIG.

28 shows another exemplary configuration of the control circuit 12-14 shown in FIG.

29 is an explanatory diagram of an algorithm used in the control circuit 28-0 illustrated in FIG. 28.

FIG. 30 is another explanatory diagram of the algorithm used in the control circuit 28-0 shown in FIG. 28.

31 is a diagram showing an average bit error rate characteristic in the device shown in FIG. 11 having the estimation error calculation circuit 11-2 when the control circuit 28-0 shown in FIG. 28 is used.

FIG. 32 is a block diagram showing the overall configuration of the device of the present invention, showing an embodiment in which a common adaptive filter is used for each state transition.

FIG. 33 shows a signal conversion circuit 33-1 according to the embodiment shown in FIG.
3 is a block configuration diagram showing an embodiment in which 3 is added. FIG.

34 is a block configuration diagram showing an embodiment using a fractionally-spaced transversal filter, a modulated wave reproducing circuit, and a metric circuit in the embodiment shown in FIG. 32.

FIG. 35 is a block diagram showing an embodiment in which a signal conversion circuit is added to the embodiment shown in FIG. 34.

[Fig. 36] Fig. 36 is a block diagram showing another configuration example of the present invention, which describes two-branch diversity as an example.

37 is a block configuration diagram showing an embodiment in which a signal conversion circuit is added to the configuration example of the conventional Viterbi equalizer shown in FIG.

38 is a block configuration diagram showing an embodiment in which a modulated wave reproducing circuit and a metric circuit are added to the configuration example of the conventional Viterbi equalizer shown in FIG.

39 is a block diagram showing an embodiment in which a signal conversion circuit is added to the embodiment shown in FIG.

40 is a block configuration diagram showing an embodiment in which a signal conversion circuit is added to the configuration example of the conventional Viterbi equalizer shown in FIG.

41 is a block configuration diagram showing an embodiment in which a modulated wave reproducing circuit and a metric circuit are added to the configuration example of the conventional Viterbi equalizer shown in FIG.

42 is a block diagram showing an embodiment in which a signal conversion circuit is added to the embodiment shown in FIG. 41.

FIG. 43 is a block diagram showing another circuit configuration of the control circuit shown in FIGS. 36, 40, 41, and 42.

[Explanation of symbols]

11-0 ... Input terminal, 12-3 ... Signal generating circuit, 12-
5 ... Signal generation circuit, 12-1 ... Transversal filter, 12-0 ... Subtraction circuit, 12-2 ... Square operation circuit, 1
2-4 ... Control circuit.

 ─────────────────────────────────────────────────── --Continued from the front page (31) Priority claim number Japanese Patent Application No. 3-129984 (32) Priority date Hei 3 (1991) May 31 (33) Priority claiming country Japan (JP) (31) Priority Claim No. Japanese Patent Application No. 3-297934 (32) Priority Date No. 3 (1991) October 18 (33) Country of priority claim Japan (JP) (31) Priority claim number Japanese Patent Application No. 4-50929 (32) Priority Hihei 4 (1992) March 9 (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 4-50930 (32) Priority Day Hei 4 (1992) March 9 (33) ) Japan claiming priority (JP)

Claims (19)

[Claims] 1. A step of receiving a quasi-coherent detection signal as an input and outputting a received signal sample value at a constant sampling period; a code sequence corresponding to each state transition and a path of each state transition, which transits at a predetermined period. A signal generation step of inputting a corresponding code sequence and outputting a signal sequence corresponding to each state transition and a signal sequence corresponding to a path of each state transition;
Outputting a signal estimation value for each state transition using an adaptive filter made up of a transversal filter having a signal sequence corresponding to each state transition as an input and using a pre-filter coefficient vector as a tap coefficient; and the received signal The branch metric obtained for each state transition using the square of the estimation error obtained by subtracting the signal estimation value for each state transition from the sample value is input, and the signal determination result using the Viterbi algorithm and the Outputting a code sequence corresponding to the state transitions and estimating a state by outputting a code sequence corresponding to each of the state transition paths; a signal sequence corresponding to each of the state transition paths, and a basis of the signal estimation value This pre-filter coefficient vector is subjected to inner product calculation to obtain a calculation value, and this calculation is performed from the received signal sample value with a predetermined delay. A step of calculating a pre-estimation error by subtracting, and performing an inverse matrix operation from the signal sequence corresponding to the path of each state transition, calculating a Kalman gain vector, the pre-estimation error, the Kalman gain vector A control step of updating the pre-filter coefficient vector by adding a calculated value as a correction term to a pre-coefficient vector of the transversal filter, which includes a step of calculating the correction term as a calculated value, Equalization method in a variable transmission line in mobile radio 2. The step of outputting the received signal sample value at the constant sampling cycle is a step of outputting the received signal sample value at the constant sampling cycle for each diversity, and each step used in the step of estimating the state. The branch metric for each state transition is 2 of the estimation error obtained by subtracting the signal estimation value for each state transition from the received signal sample value for each diversity branch.
The equalization method in a transmission line which fluctuates in mobile radio according to claim 1, which is calculated using a sum of multiplications. 3. A code sequence corresponding to each state transition and each state, which makes a transition at a predetermined cycle with a receiving unit formed of a sampling circuit which inputs a quasi-synchronous detection signal and outputs a received signal sample value at a constant sampling cycle A signal sequence corresponding to each state transition, and a signal generation means for outputting a signal sequence corresponding to each state transition path; and a signal sequence corresponding to each state transition path; connected to the signal generation means; Adaptive filter means comprising a transversal filter having a tap coefficient, which inputs a signal sequence corresponding to a state transition and outputs a signal estimation value for each state transition; from the received signal sample value to each state transition The branch obtained by the branch metric operation circuit for each state transition using the square of the estimation error obtained by subtracting the signal estimate of State estimation means for inputting a metric and outputting a signal determination result using a Viterbi algorithm, a code sequence corresponding to each state transition, and a code sequence corresponding to a path of each state transition; From the received signal sample value, the signal series corresponding to the path of each state transition, and the inner product calculation value obtained by the inner product calculation value obtained by the inner product calculation of the tap coefficient is subtracted to obtain the pre-estimation error. The RLS algorithm for updating the tap coefficient is executed by adding the multiplication value obtained by multiplying the Kalman gain vector obtained by performing the matrix operation of the signal sequence corresponding to the path of each state transition as the correction term to the tap coefficient. An adaptive equalizer comprising: 4. The receiving means comprises a sampling circuit that performs sampling at a constant sampling period for each diversity branch, and the branch metric calculation circuit calculates each received signal sample value for each diversity branch for each diversity branch. The adaptive equalizer according to claim 3, wherein a branch metric for each state transition is calculated and output using a sum of squares of an estimation error obtained by subtracting a signal estimation value for each state transition. 5. The signal generating means outputs a symbol sequence corresponding to the state transition output by the state estimating means until the last time of the burst, and the constraint length defining the state of state estimation is K, and the burst length of the burst is set to K. The adaptive equalizer according to claim 3, which outputs an expected symbol sequence from the time of the last symbol to the time of K-1 times the symbol period T. 6. The signal generating means outputs a symbol sequence corresponding to the state transition output by the state estimating means until the last point of the burst, and the constraint length defining the state of state estimation is K, and the burst length of the burst is determined. The adaptive equalizer according to claim 4, which outputs an expected symbol sequence from the time of the last symbol to the time of K-1 times the symbol period T. 7. The receiving means is a sampling circuit having a sampling cycle of less than a symbol cycle, the signal generating means is a circuit for converting the code sequence into a modulated wave sequence, and the adaptive filter means is a fractional interval type. The branch metric operation circuit is a transversal filter, and the branch metric operation circuit outputs 2 of the estimation error obtained for each sampling period.
The adaptive equalizer according to claim 3, wherein the adaptive equalizer is a circuit that outputs a branch metric for each symbol period from the power. 8. The receiving means is a sampling circuit having a sampling period of less than a symbol period for each diversity branch, and the signal generating means is a circuit for converting the code sequence into a modulated wave sequence, and the adaptive filter. The means is a division interval type transversal filter, and the branch metric operation circuit is a circuit that outputs a branch metric for each symbol period from the sum of squares of the estimation error obtained for each sampling period for each diversity branch. An adaptive equalizer according to claim 3, wherein the adaptive equalizer is provided. 9. The signal generation means outputs a modulated wave sequence corresponding to the state transition output by the state estimation means until the last point of the burst, and the constraint length defining the state for state estimation is set to K and the burst The adaptive equalizer according to claim 7, which outputs an assumed modulated wave sequence from the time of the last symbol to the time of K-1 times the symbol period T. 10. The signal generation means outputs a modulated wave sequence corresponding to the state transition output by the state estimation means until the last time point of the burst, and the constraint length defining the state of state estimation is set as K and the burst 9. The adaptive equalizer according to claim 8, which outputs an assumed modulated wave sequence from the time of the last symbol to the time of K−1 times the symbol period T. 11. The Kalman gain vector in the control means performs an inverse matrix operation on an autocorrelation matrix of a vector formed from a signal sequence corresponding to each state transition path, and from the multiplication of the inverse matrix and the vector. An adaptive equalizer according to claim 3 obtained. 12. The adaptive equalizer according to claim 3, wherein the Kalman gain vector in the control means is obtained by multiplying a fixed matrix by a vector generated from a signal sequence corresponding to each state transition path. 13. The adaptive equalizer according to claim 3, wherein the tap coefficient of the transversal filter of the adaptive filter means is a pre-filter coefficient vector. 14. The adaptive equalizer according to claim 3, wherein the tap coefficient of the transversal filter of the adaptive filter means is a pre-filter coefficient vector multiplied by a transition matrix. 15. An estimation error obtained by generating a signal sequence corresponding to a state that transits in a predetermined cycle and subtracting a signal estimation value corresponding to each state transition from a received signal sample value for each diversity branch. State estimation means for performing state estimation using the sum of squares of, and outputting a signal determination result; and an adaptive filter for converting a signal sequence corresponding to each state transition into the signal estimated value, corresponding to each diversity branch. A diversity type equalizer, comprising: a control unit that correlates the received signal sample values corresponding to each diversity branch and controls the coefficient of the adaptive filter. 16. An estimation error obtained by generating a signal sequence corresponding to a state transiting at a predetermined cycle, and subtracting a signal estimation value corresponding to each state transition from a received signal sample value for each diversity branch. State estimation means for performing state estimation using the sum of squares of, and outputting a signal determination result; and an adaptive filter for converting a signal sequence corresponding to each state transition into the signal estimated value, corresponding to each diversity branch. Control means for controlling the coefficient of the adaptive filter that minimizes the estimation error based on the signal sequence input to each of the adaptive filters and the estimation error corresponding to each diversity branch by the least square method. Diversity type equalizer characterized by. 17. A transmission line characteristic estimating means for outputting a transmission line characteristic estimated value using a received signal sample value, the received signal sample value, and the transmission line characteristic estimated value,
A branch metric calculator that calculates a branch metric using a transition signal sequence corresponding to a state transition obtained by state estimation, and a state estimation by a Viterbi algorithm using the branch metric, and outputs the transition signal sequence. In an equalizer equipped with a state estimation means for outputting a signal determination result, the transition signal sequence output by the state estimation means is output as an estimated signal sequence until the last point of the burst to define the state of signal estimation. Equipped with an estimated signal sequence generating means for adding an expected signal sequence and outputting as an estimated signal sequence from the time of the last symbol of the burst with the constraint length of K to the time of K−1 times the symbol period. The branch metric calculation means branches the estimated signal sequence in place of the transition signal sequence. Tsu equalizer, which is a configuration used to click calculation. 18. A modulated wave generation circuit for generating a plurality of reproduced modulated waves, a fractional interval type transversal filter for converting the reproduced modulated waves into a signal estimated value, and subtracting the signal estimated value from a received signal sample value. Error detecting means for outputting an estimated error signal obtained by the above, and controlling the coefficient of the fractionally-spaced transversal filter so as to minimize the magnitude of the estimated error signal by using the estimated error signal and the reproduced modulated wave. By performing state estimation using the control means and the metric converted from the estimation error signal, a signal determination result is output and a plurality of code sequences corresponding to each state transition in state estimation are generated as the modulated wave. An adaptive equalizer, comprising: a state estimating means for outputting to a circuit. 19. A signal sequence corresponding to a state that transits at a predetermined cycle is generated, a signal estimation value corresponding to each state transition is subtracted from a received signal sample value to obtain an estimation error, and the estimation error is used. State estimating means for estimating a state and outputting a signal determination result, a transversal filter for converting a signal sequence corresponding to each state transition into the signal estimated value, a received signal sample value given a predetermined delay and the signal Control means for controlling the filter coefficient of the transversal filter to a value that minimizes the estimation error by an RLS algorithm that replaces the pre-filter coefficient vector with the pre-filter coefficient vector multiplied by the transition matrix based on the determination result; An adaptive equalizer characterized by comprising.