JPH05315580A - Semiconductor photodetector and manufacture thereof - Google Patents
Semiconductor photodetector and manufacture thereofInfo
- Publication number
- JPH05315580A JPH05315580A JP4113333A JP11333392A JPH05315580A JP H05315580 A JPH05315580 A JP H05315580A JP 4113333 A JP4113333 A JP 4113333A JP 11333392 A JP11333392 A JP 11333392A JP H05315580 A JPH05315580 A JP H05315580A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- recess
- compound semiconductor
- substrate
- buffer layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体光検知装置および
その製造方法に係り、特に二次元に配置した光検知素子
と、該光検知素子の所定位置を選択して、該光検知素子
で得られた信号を外部回路へオンオフするスィッチング
素子とを、同一半導体基板上に形成したモノリシリック
型の二次元の半導体光検知装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor photodetection device and a method for manufacturing the same, and more particularly to a photodetection device arranged two-dimensionally and a predetermined position of the photodetection device selected to obtain the photodetection device. The present invention relates to a monolithic two-dimensional semiconductor photodetector in which a switching element for turning on / off the received signal to an external circuit is formed on the same semiconductor substrate.
【0002】半導体光検知装置、特に赤外光を検知する
赤外線検知素子では、二次元に光検知素子を配置した面
型受光装置(二次元IRCCD)の開発が進められてい
る。このような二次元IRCCDには、赤外光を光電変
換し、二次元に配置された光検知素子と、この光検知素
子で光電変換されて得られた信号を、外部回路にオンオ
フするスィッチング素子とが必要とされている。For semiconductor photodetectors, particularly infrared detectors for detecting infrared light, development of a surface type photodetector (two-dimensional IR CCD) in which photodetectors are two-dimensionally arranged is under way. In such a two-dimensional IRCCD, infrared light is photoelectrically converted, and a two-dimensionally arranged photo-sensing element and a switching element for turning on and off a signal obtained by the photo-electric conversion by the photo-sensing element to an external circuit. And are needed.
【0003】[0003]
【従来の技術】従来のIRCCDは図3(a)に示すよう
に、水銀・カドミウム・テルル(Hg1-xCdx Te)のよう
な化合物半導体基板1にpn接合を設けて形成した光検
知素子2のアレイと、該光検知素子2で光電変換して得
られた信号を処理し、かつシリコン(Si)基板3に形成
した電荷転送素子(CCD)の入力ダイオード4とを、
インジウム(In)よりなる金属バンプ5でバンプ接続し
た構造を採っている。ここで図の6は両者の基板1,3 の
絶縁膜である。2. Description of the Related Art As shown in FIG. 3 (a), a conventional IR CCD is a photodetector formed by providing a pn junction on a compound semiconductor substrate 1 such as mercury cadmium tellurium (Hg 1-x Cd x Te). An array of elements 2 and an input diode 4 of a charge transfer element (CCD), which processes a signal obtained by photoelectric conversion by the light detection element 2 and is formed on a silicon (Si) substrate 3,
The structure is such that bumps are connected by metal bumps 5 made of indium (In). Here, 6 in the figure is an insulating film of both substrates 1 and 3.
【0004】[0004]
【発明が解決しようとする課題】ところで、このような
構造のIRCCDは、通常液体窒素温度の極低温で動作
させており、このIRCCDが非動作時の室温に成った
時、この動作温度と室温との温度サイクル中に膨張、お
よび収縮の応力が前記した化合物半導体1とSi基板3に
掛かることになる。By the way, the IR CCD having such a structure is normally operated at a very low temperature of liquid nitrogen, and when the IR CCD reaches a room temperature when it is not operating, the operating temperature and the room temperature are lowered. The expansion and contraction stresses are applied to the compound semiconductor 1 and the Si substrate 3 during the temperature cycle of.
【0005】そして前記化合物半導体基板1はSi基板3
に対して熱膨張率が大であるので、前記した応力が大と
成り、この両者の基板1,3 に掛かる応力の相違によって
両者の基板1,3 を接続するInの金属バンプ5が位置ずれ
したり、亀裂を生じたり、或いは甚だしい場合には、金
属バンプ5が両者の基板1,3 より剥離するような問題が
発生する。The compound semiconductor substrate 1 is a Si substrate 3
Since the coefficient of thermal expansion is large, the above-mentioned stress becomes large, and due to the difference in the stress applied to the two substrates 1 and 3, the metal bump 5 of In connecting the two substrates 1 and 3 is displaced. In the case where the metal bumps 5 are cracked, cracked, or are severe, the problem that the metal bumps 5 are peeled off from the substrates 1 and 3 of both substrates occurs.
【0006】このため、両者の基板1,3 の面積を大きく
して、大面積のIRCCDを形成すると、両者の基板の
熱膨張量の相違が拡大するので、大面積にするには限度
がある。従って、大面積のIRCCDを形成するため
に、上記した金属バンプ接合を用いずに、IRCCDを
形成する技術が要望されている。For this reason, if the areas of the substrates 1 and 3 are increased to form an IRCD having a large area, the difference in the amount of thermal expansion between the two substrates expands. .. Therefore, in order to form an IRCD having a large area, there is a demand for a technique of forming the IRCD without using the above metal bump bonding.
【0007】そこで、このような問題を解決するため
に、図3(b)に示すように、p型のSi基板3に高濃度にn
型の不純物原子をイオン注入法等を用いて導入してn+
層よりなるソース領域11とドレイン領域12を形成し、そ
の上にSiO2膜13を介してポリSi膜よりなるゲート電極14
を形成してMOS型のスィッチング素子を形成する。Therefore, in order to solve such a problem, as shown in FIG. 3B, the p-type Si substrate 3 is doped with a high concentration of n.
-Type impurity atoms are introduced by an ion implantation method or the like to obtain n +
A source region 11 and a drain region 12 made of layers are formed, and a gate electrode 14 made of a poly-Si film is formed on the source region 11 and the drain region 12 with a SiO 2 film 13 interposed therebetween.
To form a MOS type switching element.
【0008】一方、ソース領域11上のSiO2膜13を開口し
てソース領域11上にn型のCdTe層15をMOCVD(Metal
Organic Chemical Vapor Deposition; 有機金属気相成
長方法) 法、或いは分子線エピタキシャル成長法等を用
いて形成後、該CdTe層15上にn型HgCdTe層16とp型HgCd
Te層17をMOCVD法、或いは分子線エピタキシャル成
長法等を用いて形成し、光検知素子2を形成している。On the other hand, the SiO 2 film 13 on the source region 11 is opened to form an n-type CdTe layer 15 on the source region 11 by MOCVD (Metal).
Organic Chemical Vapor Deposition) method, molecular beam epitaxial growth method or the like, and then n-type HgCdTe layer 16 and p-type HgCd are formed on the CdTe layer 15.
The Te layer 17 is formed by using the MOCVD method, the molecular beam epitaxial growth method, or the like to form the photodetector element 2.
【0009】そしてこの光検知素子2で光電変換して得
られた信号を、ソース領域11に伝達し、ゲート電極14に
電圧をオンオフすることで、ソース領域11に伝達された
信号を、ドレイン領域12に伝達し、該ドレイン領域12と
導通している配線層( 図示せず) を通じて外部回路に導
出している。Then, a signal obtained by photoelectrically converting the light detecting element 2 is transmitted to the source region 11 and a voltage is turned on / off to the gate electrode 14, so that the signal transmitted to the source region 11 is transferred to the drain region. It is transmitted to 12 and is led to an external circuit through a wiring layer (not shown) which is electrically connected to the drain region 12.
【0010】ところで、上記したシリコン基板3にMO
S型スィッチング素子を形成するには、該素子が良好な
電気的特性と成るように、(100)面の面方位を有す
るSi基板3が使用されている。By the way, the above-mentioned silicon substrate 3 is provided with MO.
To form an S-type switching element, a Si substrate 3 having a plane orientation of (100) plane is used so that the element has good electrical characteristics.
【0011】然し、このような(100)面の面方位を
有するSi基板3上にCdTe層15をエピタキシャル成長する
と、(111)面の面方位を有するCdTe層15が成長する
ことが文献〔"Molecular beam epitaxial growth of Cd
Te and HgCdTe on Si (100)"、Appl.Phys.Lett.55(18),
30 October 1989 page 1879 〜1881、by R.Sporken等〕
に記載されている。However, when the CdTe layer 15 is epitaxially grown on the Si substrate 3 having such a (100) plane orientation, the CdTe layer 15 having the (111) plane orientation grows in the literature ["Molecular beam epitaxial growth of Cd
Te and HgCdTe on Si (100) ", Appl.Phys.Lett.55 (18),
30 October 1989 page 1879-1881, by R. Sporken, etc.)
It is described in.
【0012】この(111)面の面方位を有するCdTe層
15は、双晶のような結晶欠陥が発生し易く、そのため、
このCdTe層15上に形成して光検知素子2の形成材料とな
るn型、或いはp型のHgCdTe層16,17 にも、当然双晶の
ような結晶欠陥が発生し易くなり、リーク電流が発生す
る等の不都合が生じ、受光特性の悪い光検知素子となる
問題点を生じる。CdTe layer having the (111) plane orientation
In No. 15, crystal defects such as twins are likely to occur, and therefore,
The n-type or p-type HgCdTe layers 16 and 17, which are formed on the CdTe layer 15 and are used as the material for forming the photodetector 2, are naturally prone to crystal defects such as twins, and a leak current is generated. Inconveniences such as occurrence occur, and there arises a problem that it becomes a light detecting element having poor light receiving characteristics.
【0013】本発明は上記した問題点を除去し、CdTe層
およびHgCdTe層が(100)面と成るようにして結晶欠
陥の少ないHgCdTe層が得られるようにして受光特性の良
好な光検知素子が得られるような半導体光検知装置、お
よびその製造方法の提供を目的とする。The present invention eliminates the above-mentioned problems and makes it possible to obtain a HgCdTe layer having few crystal defects by making the CdTe layer and the HgCdTe layer have (100) planes, and to provide a photodetector having excellent light receiving characteristics. An object of the present invention is to provide a semiconductor photodetection device and a method of manufacturing the same.
【0014】[0014]
【課題を解決するための手段】本発明の半導体光検知装
置は、請求項1に示すように半導体基板の所定領域に凹
部を設けるとともに、該凹部の周囲にMOS型スィッチ
ング素子のリング状のソース領域を設け、該ソース領域
より所定位置の前記半導体基板にドレイン領域を設け、
該基板上に絶縁膜を介してゲート電極を設け、前記凹部
内に亜鉛を含む化合物半導体層、或いはガリウムを含む
化合物半導体層と亜鉛を含む化合物半導体層を積層して
成る面方位選択層、不純物原子を添加したカドミウムを
含む化合物半導体層よりなるバッファ層を設け、該バッ
ファ層上に光検知素子形成用の互いに導電型の異なる水
銀を含む化合物半導体層を積層して設けたことを特徴と
するものである。According to another aspect of the present invention, there is provided a semiconductor photodetecting device, wherein a recess is provided in a predetermined region of a semiconductor substrate and a ring-shaped source of a MOS type switching element is provided around the recess. A region is provided, and a drain region is provided on the semiconductor substrate at a predetermined position from the source region,
A gate electrode is provided on the substrate via an insulating film, and a plane orientation selection layer formed by stacking a compound semiconductor layer containing zinc, or a compound semiconductor layer containing gallium and a compound semiconductor layer containing zinc in the recess, and an impurity A buffer layer comprising a compound semiconductor layer containing cadmium to which atoms are added is provided, and a compound semiconductor layer containing mercury having different conductivity types for forming a photo-detecting element is laminated on the buffer layer. It is a thing.
【0015】また請求項2に示すように、前記面方位選
択層の厚さを凹部の深さより薄く設け、該面方位選択層
とバッファ層の和の厚さを、凹部の深さと同等、或いは
それ以上の厚さに設けることを特徴とする。Further, as described in claim 2, the thickness of the plane orientation selection layer is set smaller than the depth of the recess, and the sum of the thickness of the plane orientation selection layer and the buffer layer is equal to or equal to the depth of the recess. It is characterized in that it is provided with a thickness greater than that.
【0016】また請求項3に示すように、本発明の半導
体光検知装置の製造方法は、半導体基板の所定領域に凹
部を形成し、該凹部の周囲に不純物原子を所定のパター
ンで導入してMOS型スィッチング素子のリング状のソ
ース領域を形成し、該ソース領域より所定位置の前記半
導体基板に不純物原子を導入してドレイン領域を形成す
ると共に、該基板上に絶縁膜を介してゲート電極を形成
し、前記凹部内に亜鉛を含む化合物半導体層、或いはガ
リウムを含む化合物半導体層と亜鉛を含む化合物半導体
層を積層して成る面方位選択層を形成後、該面方位選択
層上に不純物原子を添加したカドミウムを含む化合物半
導体層より成るバッファ層を形成し、該バッファ層上に
光検知素子形成用の互いに導電型の異なる水銀を含む化
合物半導体層を積層して形成することを特徴とするもの
である。According to a third aspect of the present invention, in the method of manufacturing a semiconductor photodetecting device of the present invention, a recess is formed in a predetermined region of a semiconductor substrate, and impurity atoms are introduced in a predetermined pattern around the recess. A ring-shaped source region of a MOS type switching device is formed, impurity atoms are introduced into the semiconductor substrate at a predetermined position from the source region to form a drain region, and a gate electrode is formed on the substrate via an insulating film. After forming a compound semiconductor layer containing zinc or a compound semiconductor layer containing gallium and a compound semiconductor layer containing zinc in the recess, a plane orientation selection layer is formed, and impurity atoms are formed on the plane orientation selection layer. Forming a buffer layer composed of a compound semiconductor layer containing cadmium added thereto, and depositing a compound semiconductor layer containing mercury having different conductivity types for forming a photodetection element on the buffer layer. It is characterized in that to form.
【0017】[0017]
【作用】本発明の半導体装置は、(100)面の面方位
を有するSi基板に、凹部を形成するとともに、該凹部の
周囲のSi基板にリング状の高濃度n型層を形成してソー
ス領域と該ソース領域より隔たった位置にドレイン領域
を形成する。そして該Si基板上にSiO2膜を形成してSiO2
膜内にポリSiゲート電極を埋設してMOS型のスィッチ
ング素子を形成する。According to the semiconductor device of the present invention, a recess is formed in a Si substrate having a (100) plane orientation, and a ring-shaped high-concentration n-type layer is formed in the Si substrate around the recess to form a source. A drain region is formed at a position separated from the region and the source region. The SiO 2 to form an SiO 2 film on the Si substrate
A poly-Si gate electrode is embedded in the film to form a MOS type switching element.
【0018】一方、このSi基板の凹部上のSiO2膜を除去
し、該凹部内にSi基板とCdTe層の略中間の格子定数を有
する面方位選択層としてのZnTe層を形成する。ここで
(100) 面のSiの格子定数は5.43Åであり、(10
0)面のZnTeの格子定数は6.10Åであり、(100)面
のCdTeの格子定数は6.481 Åの値を示す。On the other hand, the SiO 2 film on the recess of the Si substrate is removed, and a ZnTe layer as a plane orientation selection layer having a lattice constant approximately in the middle of the Si substrate and the CdTe layer is formed in the recess. Here, the lattice constant of Si on the (100) plane is 5.43Å, and (10
The lattice constant of ZnTe in the (0) plane is 6.10Å, and the lattice constant of CdTe in the (100) plane is 6.481Å.
【0019】このZnTe層は、前記した文献により(10
0)面の面方位を有するSi基板に(100)面の面方位
を有するZnTe層が形成できる。然し、この面方位選択層
のZnTe層はn型の導電型の結晶が得られ難い。This ZnTe layer is described in (10)
A ZnTe layer having a (100) plane orientation can be formed on a Si substrate having a (0) plane orientation. However, it is difficult to obtain an n-type conductivity type crystal in the ZnTe layer of this plane orientation selection layer.
【0020】そのため、このZnTe層には、その上に形成
予定の光検知素子で得られた光電流が流入しないので、
凹部の周囲に形成されたスィッチング素子のソース領域
に光電流は流入しない。そのため、ZnTe層の面方位選択
層は凹部の深さより薄く形成し、このZnTe層の上に(1
00)の面方位の高濃度のn型のCdTe層をバッファ層と
して凹部の深さより厚く形成し、該バッファ層のCdTe層
の上に形成予定の光検知素子より流入される光電流を、
該CdTe層と接触している周囲のソース領域に流入するよ
うにする。そしてこのCdTe層の上に(100)の面方位
のn型、およびp型のHgCdTe層を形成して光検知素子を
形成する。Therefore, the photocurrent obtained by the photodetection element to be formed thereon does not flow into this ZnTe layer,
No photocurrent flows into the source region of the switching element formed around the recess. Therefore, the plane orientation selection layer of the ZnTe layer is formed thinner than the depth of the recess, and (1
00) plane-oriented high-concentration n-type CdTe layer is formed to be thicker than the depth of the recess as a buffer layer, and the photocurrent flowing from the photodetector to be formed on the CdTe layer of the buffer layer is
It flows into the surrounding source region that is in contact with the CdTe layer. Then, an n-type and p-type HgCdTe layer having a (100) plane orientation is formed on this CdTe layer to form a photodetecting element.
【0021】このようにすると、CdTe層、HgCdTe層が共
に双晶のような結晶欠陥の発生し難い(100)の面方
位を有する結晶が得られ、高性能な光検知素子が得られ
る。また光検知素子で得られた光電流は、n型のCdTe層
のバッファ層に集められ、更にその光電流はCdTe層の周
囲にリング状に設けられた高濃度のSiのn+ 層よりなる
ソース領域に容易に流入する。このようにしてn型の導
電型が得られ難いが、(100)の面方位が得られ易い
ZnTe層を面方位選択層として形成し、その上に(10
0)の面方位のn型のCdTe層を形成して、このCdTe層を
バッファ層としてその上に結晶欠陥の少ないp型、およ
びn型のHgCdTe層を形成することが可能となる。By doing so, both the CdTe layer and the HgCdTe layer have a (100) plane orientation in which crystal defects such as twins are unlikely to occur, and a high-performance photodetector can be obtained. Further, the photocurrent obtained by the photodetector is collected in the buffer layer of the n-type CdTe layer, and the photocurrent is composed of a high-concentration Si n + layer provided in a ring shape around the CdTe layer. Easily flows into the source region. In this way, it is difficult to obtain the n-type conductivity type, but it is easy to obtain the (100) plane orientation.
A ZnTe layer is formed as a plane orientation selection layer, and (10
It is possible to form an n-type CdTe layer having a plane orientation of 0) and use this CdTe layer as a buffer layer to form p-type and n-type HgCdTe layers with few crystal defects thereon.
【0022】またn型のCdTe層の周囲にはリング状のソ
ース領域が接触して設けてあるので、CdTe層に集められ
た光電流はソース領域に向かって容易に流入する。Further, since the ring-shaped source region is provided in contact with the periphery of the n-type CdTe layer, the photocurrent collected in the CdTe layer easily flows into the source region.
【0023】[0023]
【実施例】本発明の半導体光検知装置の実施例を図1(a)
の断面図、図1(b)の斜視図に示す。[Embodiment] An embodiment of a semiconductor photodetector of the present invention is shown in FIG.
A cross-sectional view and a perspective view of FIG. 1 (b) are shown.
【0024】図1(a)および図1(b)に示すように、抵抗率
が10〜20Ω-cm で面方位が(100)面のp型のSi基板
3に、深さが5μm で、直径が20μm の凹部21を50μm
のピッチで設ける。そしてこの該凹部21の周囲にMOS
型のスィッチング素子18のリング状で不純物原子濃度が
1018/cm3のn+ 層のソース領域11と、該ソース領域11よ
り所定の位置にドレイン領域12を設け、該基板上にSiO2
膜よりなる絶縁膜13を介してポリSiより成るゲート電極
14を設ける。As shown in FIGS. 1 (a) and 1 (b), a p-type Si substrate 3 having a resistivity of 10 to 20 Ω-cm and a plane orientation of (100) has a depth of 5 μm. The recess 21 with a diameter of 20 μm is
Provide at the pitch of. A MOS is formed around the recess 21.
Ring-shaped switching element 18 of
A source region 11 of an n + layer of 10 18 / cm 3 and a drain region 12 are provided at a predetermined position from the source region 11, and SiO 2 is formed on the substrate.
Gate electrode made of poly-Si via insulating film 13 made of a film
Provide 14
【0025】そして前記凹部21内に、該凹部の深さより
薄い厚さのZnTe、或いはGaAs層とZnTe層を積層した面方
位選択層22と、その上にn型の不純物原子、つまりInを
添加したCdTe層よりなるバッファ層23を設ける。この面
方位選択層22とバッファ層23の和の厚さは凹部21の深さ
と同等か、或いはそれ以上の厚さとする。In the recess 21, ZnTe having a thickness smaller than the depth of the recess, or a plane orientation selection layer 22 in which a GaAs layer and a ZnTe layer are stacked, and an n-type impurity atom, that is, In, are added thereon. A buffer layer 23 made of the CdTe layer is provided. The total thickness of the plane orientation selection layer 22 and the buffer layer 23 is equal to or greater than the depth of the recess 21.
【0026】そして該バッファ層23上に光検知素子形成
用のn型HgCdTe層16とp型HgCdTe層17を積層して設け
る。このような本発明の半導体光検知装置によると、結
晶欠陥の少ないn型HgCdTe層16とp型HgCdTe層17を積層
して設けているので、高信頼度の光検知素子が得られ
る。On the buffer layer 23, an n-type HgCdTe layer 16 and a p-type HgCdTe layer 17 for forming a photodetector are laminated and provided. According to such a semiconductor photodetector of the present invention, since the n-type HgCdTe layer 16 and the p-type HgCdTe layer 17 having few crystal defects are provided in a laminated manner, a highly reliable photodetector can be obtained.
【0027】またn型のCdTe層のバッファ層23の周囲に
はリング状の高濃度のソース領域11が形成されているの
で、光検知素子で得られた光電流がバッファ層23に集め
られ、容易に該バッファ層に接触して周囲に設けられて
いるソース領域11に流入するので高性能な半導体光検知
装置が得られる。In addition, since the ring-shaped high-concentration source region 11 is formed around the buffer layer 23 of the n-type CdTe layer, the photocurrent obtained by the photodetector is collected in the buffer layer 23, The semiconductor photodetector with high performance can be obtained because it easily contacts the buffer layer and flows into the source region 11 provided in the periphery.
【0028】このような本発明の半導体光検知装置の製
造方法に付いて述べる。図2(a)に示すように抵抗率が10
〜20Ω-cm で面方位が(100)面のp型のSi基板3に
深さが5 μm で、直径が20μm の凹部21を50μm のピッ
チでイオンエッチング法等で形成する。A method of manufacturing such a semiconductor photodetector of the present invention will be described. As shown in Fig. 2 (a), the resistivity is 10
Recesses 21 having a depth of 5 μm and a diameter of 20 μm are formed at a pitch of 50 μm on the p-type Si substrate 3 having a surface orientation of (100) by 20 Ω-cm by an ion etching method or the like.
【0029】次いで図2(b)に示すように、該凹部21の周
囲に燐原子を1018/cm3の不純物濃度でイオン注入してM
OS型スィッチング素子のリング状のn+ 型のソース領
域11を形成するとともに、該ソース領域11より所定位置
の前記Si基板3に、燐原子を同様にイオン注入してドレ
イン領域12を形成する。Next, as shown in FIG. 2 (b), phosphorus atoms are ion-implanted around the recess 21 at an impurity concentration of 10 18 / cm 3 to form M.
A ring-shaped n + type source region 11 of the OS type switching element is formed, and phosphorus atoms are similarly ion-implanted into the Si substrate 3 at a predetermined position from the source region 11 to form a drain region 12.
【0030】次いで該基板上にCVD法、或いはスパッ
タ法によりSiO2膜よりなる絶縁膜13を形成し、該絶縁膜
上にCVD法でポリSi膜を形成し、該ポリSi膜を所定の
パターンにエッチングしてゲート電極14を形成し、その
上に更に絶縁膜13を形成する。Next, an insulating film 13 made of a SiO 2 film is formed on the substrate by a CVD method or a sputtering method, a poly Si film is formed on the insulating film by a CVD method, and the poly Si film is formed into a predetermined pattern. Then, a gate electrode 14 is formed by etching, and an insulating film 13 is further formed thereon.
【0031】次いで図2(c)に示すように前記凹部21上の
絶縁膜13をエッチングにより除去した後、該凹部21内に
ZnTeよりなる面方位選択層22をMOCVD法、或いは分
子線エピタキシャル成長法により凹部21の深さより薄い
寸法、つまり1μm の厚さで形成する。このZnTeよりな
る面方位選択層22の面方位は(100)面となる。Next, as shown in FIG. 2C, the insulating film 13 on the recess 21 is removed by etching, and then the recess 21 is filled with the insulating film 13.
The plane orientation selection layer 22 made of ZnTe is formed by MOCVD or molecular beam epitaxial growth to have a dimension smaller than the depth of the recess 21, that is, a thickness of 1 μm. The plane orientation of the plane orientation selection layer 22 made of ZnTe is the (100) plane.
【0032】次いで図2(d)に示すように、前記面方位選
択層22の上にInを添加してn型層としたCdTe層より成る
バッファ層23を7μm の厚さにMOCVD法、或いは分
子線エピタキシャル成長方法により形成する。このCdTe
層は(100)面であり、結晶欠陥は発生し難い。Then, as shown in FIG. 2 (d), a buffer layer 23 made of a CdTe layer, which is an n-type layer formed by adding In to the plane orientation selection layer 22, is formed by MOCVD to a thickness of 7 μm, or It is formed by the molecular beam epitaxial growth method. This CdTe
The layer has a (100) plane, and crystal defects are unlikely to occur.
【0033】該バッファ層23上にInを不純物原子として
添加してn型のHgCdTe層16を1μmの厚さに成膜し、そ
の上に砒素(As)を不純物原子として添加してp型のHgCd
Te層17を10μm の厚さに成膜して光検知素子を形成す
る。この両者のHgCdTe層16,17はいずれも(100)面
となるので結晶欠陥は発生し難く、高信頼度の光検知素
子が得られる。On the buffer layer 23, In is added as an impurity atom to form an n-type HgCdTe layer 16 with a thickness of 1 μm, and arsenic (As) is added as an impurity atom to form a p-type HgCdTe layer 16. HgCd
The Te layer 17 is deposited to a thickness of 10 μm to form a photodetector element. Since both of these HgCdTe layers 16 and 17 have (100) planes, crystal defects are less likely to occur, and a highly reliable photodetector can be obtained.
【0034】なお、本実施例は、面方位選択層としてZn
Te層のみを用いたが、Si基板に設けた凹部21内にGaAs層
を形成し、その上にZnTe層を積層して形成しても良い。In this embodiment, Zn is used as the plane orientation selection layer.
Although only the Te layer is used, a GaAs layer may be formed in the recess 21 provided in the Si substrate, and a ZnTe layer may be stacked on the GaAs layer.
【0035】[0035]
【発明の効果】以上述べたように、本発明の半導体光検
知装置によると、光検知素子を形成するHgCdTe層に双晶
のような結晶欠陥が発生し難いので高信頼度の光検知素
子が得られる。As described above, according to the semiconductor photodetection device of the present invention, since a crystal defect such as twin is unlikely to occur in the HgCdTe layer forming the photodetection device, a highly reliable photodetection device can be obtained. can get.
【0036】また凹部を設けることで、またその周囲に
設けたリング状の高濃度不純物層のソース領域を設ける
ことで、n型の導電型の結晶が形成し難いZnTe層で有っ
ても、このZnTe層を凹部の深さより薄く形成して、その
上にn型のCdTe層を形成することで、前記ZnTe層を、
(100)面の面方位のCdTe層を形成するための面方位
選択層として適用することができ、高性能で高信頼度の
半導体光検知装置が得られる効果がある。Further, by providing the concave portion and the source region of the ring-shaped high-concentration impurity layer provided around the concave portion, even if the ZnTe layer is difficult to form n-type conductivity type crystals, This ZnTe layer is formed to be thinner than the depth of the recess, and an n-type CdTe layer is formed thereon to form the ZnTe layer,
It can be applied as a plane orientation selection layer for forming a CdTe layer having a plane orientation of the (100) plane, and has an effect of obtaining a semiconductor photodetector with high performance and high reliability.
【図1】 本発明の半導体光検知装置の断面図と斜視図
である。FIG. 1 is a sectional view and a perspective view of a semiconductor photodetector of the present invention.
【図2】 本発明の装置の製造方法を示す断面図であ
る。FIG. 2 is a cross-sectional view showing the method of manufacturing the device of the present invention.
【図3】 従来の装置の説明図である。FIG. 3 is an explanatory diagram of a conventional device.
2 光検知素子 3 Si基板 11 ソース領域 12 ドレイン領域 13 絶縁膜( SiO2膜) 14 ゲート電極 16 n 型HgCdTe層 17 p 型HgCdTe層 18 スィッチング素子 21 凹部 22 面方位選択層 23 バッファ層2 Photodetector 3 Si substrate 11 Source region 12 Drain region 13 Insulating film (SiO 2 film) 14 Gate electrode 16 n-type HgCdTe layer 17 p-type HgCdTe layer 18 Switching device 21 Recess 22 Face orientation selection layer 23 Buffer layer
フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 31/10 Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 31/10
Claims (3)
設けるとともに、該凹部(21)の周囲にMOS型スィッチ
ング素子のリング状のソース領域(11)を設け、 該ソース領域(11)より所定位置の前記半導体基板(3) に
ドレイン領域(12)を設け、該基板(3) 上に絶縁膜(13)を
介してゲート電極(14)を設け、 前記凹部(21)内に亜鉛を含む化合物半導体層、或いはガ
リウムを含む化合物半導体層と亜鉛を含む化合物半導体
層を積層して成る面方位選択層(22)、不純物原子を添加
したカドミウムを含む化合物半導体層よりなるバッファ
層(23)を設け、 該バッファ層(23)上に光検知素子形成用の互いに導電型
の異なる水銀を含む化合物半導体層(16,17) を積層して
設けたことを特徴とする半導体光検知装置。1. A semiconductor substrate (3) is provided with a recess (21) in a predetermined region, and a ring-shaped source region (11) of a MOS type switching element is provided around the recess (21). A drain region (12) is provided on the semiconductor substrate (3) at a predetermined position from (11), a gate electrode (14) is provided on the substrate (3) through an insulating film (13), and inside the recess (21). A compound semiconductor layer containing zinc, or a plane orientation selection layer (22) formed by stacking a compound semiconductor layer containing gallium and a compound semiconductor layer containing zinc, and a buffer layer including a compound semiconductor layer containing cadmium to which impurity atoms are added (23) is provided, and a compound semiconductor layer (16, 17) containing mercury having different conductivity types for forming a photodetection element is laminated on the buffer layer (23) to provide a semiconductor photodetection. apparatus.
を凹部(21)の深さより薄く設け、前記面方位選択層(22)
とバッファ層(23)の和の厚さを、凹部(21)の深さと同
等、或いはそれ以上の厚さに設けることを特徴とする半
導体光検知装置。2. The plane orientation selection layer (22) according to claim 1, wherein the plane orientation selection layer (22) has a thickness smaller than the depth of the recess (21).
The semiconductor photodetecting device is characterized in that the total thickness of the buffer layer (23) and the buffer layer (23) is equal to or greater than the depth of the recess (21).
形成し、該凹部(21)の周囲に不純物原子を所定のパター
ンで導入してMOS型スィッチング素子のリング状のソ
ース領域(11)を形成し、 該ソース領域(11)より所定位置の前記半導体基板(3) に
不純物原子を導入してドレイン領域(12)を形成すると共
に、該基板(3) 上に絶縁膜(13)を介してゲート電極(14)
を形成し、 前記凹部(21)内に亜鉛を含む化合物半導体層、或いはガ
リウムを含む化合物半導体層と亜鉛を含む化合物半導体
層を積層して成る面方位選択層(22)を形成後、 該面方位選択層(22)上に不純物原子を添加したカドミウ
ムを含む化合物半導体層より成るバッファ層(23)を形成
し、 該バッファ層(23)上に光検知素子形成用の互いに導電型
の異なる水銀を含む化合物半導体層(16,17) を積層して
形成することを特徴とする半導体光検知装置の製造方
法。3. A ring-shaped source region of a MOS type switching device in which a recess (21) is formed in a predetermined region of a semiconductor substrate (3) and impurity atoms are introduced around the recess (21) in a predetermined pattern. (11) is formed, impurity atoms are introduced into the semiconductor substrate (3) at a predetermined position from the source region (11) to form a drain region (12), and an insulating film () is formed on the substrate (3). Gate electrode through (13) (14)
And forming a plane orientation selection layer (22) formed by stacking a compound semiconductor layer containing zinc, or a compound semiconductor layer containing gallium and a compound semiconductor layer containing zinc in the recess (21), A buffer layer (23) made of a compound semiconductor layer containing cadmium to which impurity atoms are added is formed on the orientation selection layer (22), and mercury having different conductivity types for forming a photodetecting element is formed on the buffer layer (23). A method for manufacturing a semiconductor photodetecting device, which is characterized in that the compound semiconductor layers (16, 17) containing are laminated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4113333A JPH05315580A (en) | 1992-05-06 | 1992-05-06 | Semiconductor photodetector and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4113333A JPH05315580A (en) | 1992-05-06 | 1992-05-06 | Semiconductor photodetector and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05315580A true JPH05315580A (en) | 1993-11-26 |
Family
ID=14609587
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4113333A Withdrawn JPH05315580A (en) | 1992-05-06 | 1992-05-06 | Semiconductor photodetector and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05315580A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007532007A (en) * | 2004-04-06 | 2007-11-08 | キネテイツク・リミテツド | Production of cadmium mercury telluride |
-
1992
- 1992-05-06 JP JP4113333A patent/JPH05315580A/en not_active Withdrawn
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007532007A (en) * | 2004-04-06 | 2007-11-08 | キネテイツク・リミテツド | Production of cadmium mercury telluride |
US8021914B2 (en) | 2004-04-06 | 2011-09-20 | Qinetiq Limited | Manufacture of cadmium mercury telluride |
KR101110592B1 (en) * | 2004-04-06 | 2012-02-17 | 키네티큐 리미티드 | Manufacture of cadmium mercury telluride |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5380669A (en) | Method of fabricating a two-color detector using LPE crystal growth | |
US4965649A (en) | Manufacture of monolithic infrared focal plane arrays | |
US6657194B2 (en) | Multispectral monolithic infrared focal plane array detectors | |
US7695996B2 (en) | Photodetecting device | |
EP0475525B1 (en) | Plural-wavelength infrared detector devices | |
JP6290245B2 (en) | Pixelated imager with MOTFET and method of manufacturing the same | |
EP0635892B1 (en) | Bake-stable HgCdTe photodetector and method for fabricating same | |
US20030102432A1 (en) | Monolithic infrared focal plane array detectors | |
US5279974A (en) | Planar PV HgCdTe DLHJ fabricated by selective cap layer growth | |
US5936268A (en) | Epitaxial passivation of group II-VI infrared photodetectors | |
US11851785B2 (en) | Aluminum nitride passivation layer for mercury cadmium telluride in an electrical device | |
JPH04246860A (en) | Photoelectric conversion device | |
US5296384A (en) | Bake-stable HgCdTe photodetector and method for fabricating same | |
JPH05315580A (en) | Semiconductor photodetector and manufacture thereof | |
JP3577368B2 (en) | Hybrid type infrared detector | |
JPH03270177A (en) | Semiconductor photodetection device and its manufacture | |
JP2525780B2 (en) | Stacked solid-state imaging device | |
JPH02502326A (en) | Infrared radiation detection device | |
JP2001274451A (en) | Semiconductor image pickup element and method of manufacturing it | |
JPS63273365A (en) | Infrared-ray detector | |
KR101016514B1 (en) | Image Sensor and Method for Manufacturing thereof | |
JPH01233777A (en) | Infrared radiation detector | |
JPH1012898A (en) | Infrared sensor | |
JPS61251068A (en) | Solid-state image pickup device | |
JPH0536957A (en) | Manufacture of solid-state image pick up device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990706 |