JPH05291930A - Semiconductor device - Google Patents

Abstract

PURPOSE:To sufficiently suppress a voltage fluctuation due to inductance of wiring. CONSTITUTION:When a level of an input terminal 11 of an output buffer 12 is high, a capacitor 26 is charged via a MOSFET 24 and an instantaneous current flowing to a ground line 17 via a MOSFET 14 is decreased. Thus, undershoot is suppressed. Furthermore, the capacitor 23 charged when a level of the input terminal 11 of the output buffer 12 is low is discharged, when the input terminal 11 is a low level and a MOSFET 22 is conductive and the charge flows to a load capacitor 18 as a charging current. Since an instantaneous current flowing from a power supply line 15 to the load capacitor 18 via a MOSFET 13 is decreased, overshoot is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device applied to an output buffer using, for example, a CMOS inverter circuit.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional semiconductor device. For example, the internal circuit 10 composed of a logic circuit
The output terminal of is connected to the input terminal 11 of the output buffer 12 formed of, for example, a CMOS inverter circuit. That is, the output terminal of the internal circuit 10 is connected to the gates of the P-channel MOSFET 13 and the N-channel MOSFET 14. The source of the P-channel MOSFET 13 is connected to the first power supply V _DD via the power supply line 15, and the drain thereof is connected to the output terminal 16 together with the drain of the N-channel MOSFET 14. This N
The source of the channel MOSFET 14 is connected to the second power supply V _SS via the ground line 17 and is also connected to the output terminal 16 via the load capacitance 18.

In the above structure, when the potential of the output terminal of the internal circuit 10, that is, the input terminal 11 becomes low level, the N-channel MOSFET 14 becomes non-conductive, the P-channel MOSFET 13 becomes conductive, and the P-channel MOS is formed.
The load capacitance 18 is charged through the FET 13 and the output terminal 16 becomes high level. On the other hand, when the input terminal 11 becomes the high level, the P-channel MOSFET 13 becomes non-conductive, the N-channel MOSFET 14 becomes conductive, and the electric charge charged in the load capacitance 18 becomes the N-channel MOSFET.
After being discharged through 14, the output terminal 16 becomes low level.

[0004]

By the way, in the above conventional semiconductor device, when the potential of the input terminal 11 changes from the high level to the low level, the P-channel MOSFE is used.
Since T13 becomes conductive and a large current flows instantly, an overshoot OS as shown in FIG. 5 occurs in the output voltage due to the inductance 15a of the power supply line 15. Further, when the potential of the input terminal 11 changes from the low level to the high level, the N-channel MOSFET 14 becomes conductive and a discharge current flows instantly. Undershoot US occurs.

Thus, when the output voltage overshoots or undershoots, not only the output voltage fluctuates but also the first and second power supplies V _DD and V _SS fluctuate. Fluctuations in the output voltage and the power supply voltage affect other circuits that use these voltages and cause malfunctions, so it is necessary to suppress voltage fluctuations.

The voltage generated by overshoot or undershoot is expressed as Ldi / dt, where L is the inductance of the wiring. Therefore, it is conceivable to reduce the wiring inductance, but there is a limit to reducing the wiring inductance, and it has not been sufficient as a measure for suppressing the voltage fluctuation.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of sufficiently suppressing voltage fluctuation due to the inductance of wiring. Is.

[0008]

According to the present invention, in order to solve the above-mentioned problems, one end of a current path of a first conductivity type MOSFET is connected to a first power supply line, and the current of the first conductivity type MOSFET is increased. The other end of the passage has a second conductivity type MOSF
This second conductivity type M is connected to one end of the current path of ET.
The other end of the current path of the OSFET is connected to a second power supply line, the gates of these first and second conductivity type MOSFETs are used as input terminals, and the connection point of the first and second conductivity type MOSFETs is an output terminal. And a first switch circuit having a current path connected between the first power supply line and the output terminal of the output buffer, the input end of which is connected to the input terminal of the output buffer, When the output terminal of the first switch circuit is provided between the second power supply line and the input terminal of the output buffer is at a high level, it is charged through the first switch circuit and the output buffer When the input terminal is at the low level, a current path is formed between the first capacitor discharged through the first switch circuit and the output terminal of the output buffer and the second power supply line. A second switch circuit having an input terminal connected to the input terminal of the output buffer and an output terminal of the second switch circuit and the second power supply line. A second capacitor that is charged through the second switch circuit when the input terminal is at the high level, and discharged through the second switch circuit when the input terminal of the output buffer is at the low level. is doing.

The first switch circuit has a second conductivity type MOSF in which a current path is connected in series between the first power supply line and the output terminal of the output buffer.
ET and a MOSFET of the first conductivity type, the gates of these MOSFETs are connected to the input terminal of the output buffer, and the connection point of the current path of these MOSFETs is connected to one end of the first capacitance.

Further, the second switch circuit is a second conductivity type MOS in which a current path is connected in series between the output terminal of the output buffer and the second power supply line.
An FET and a MOSFET of the first conductivity type, the gates of these MOSFETs are connected to the input terminal of the output buffer, and the connection point of the current path of these MOSFETs is connected to one end of the second capacitor.

The first switch circuit is composed of first and second analog switches having current paths connected in series between the first power supply line and the output terminal of the output buffer. The input end of the analog switch is connected to the input terminal of the output buffer, and the output end is connected to one end of the first capacitor.

Further, the second switch circuit is composed of first and second analog switches having a current path connected in series between the output terminal of the output buffer and the second power supply line. The input end of the analog switch is connected to the input terminal of the output buffer, and the output end is connected to one end of the second capacitor.

[0013]

That is, according to the present invention, when the input terminal of the output buffer is at the high level, the first capacitor is charged via the first switch circuit and the second capacitor is charged via the second switch circuit. By charging, the instantaneous current flowing through the second power supply line can be reduced and undershoot can be suppressed. When the input terminal of the output buffer is at the low level, the electric charge of the second capacitance is discharged through the second switch circuit and the first switch circuit is operated through the first switch circuit.
By discharging the electric charge of the capacity of, the instantaneous current flowing through the first power supply line can be reduced and the overshoot can be suppressed.

When the first and second switch circuits are analog switches, the on-resistance of the switches does not depend on the source and drain voltages of the MOSFET, so that undershoot and overshoot can be further suppressed.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same parts as those in FIG. 4 are designated by the same reference numerals, and only different parts will be described.

In FIG. 1, for example, an input terminal 1 of an output buffer 12 composed of a CMOS inverter circuit.
1 includes an N-channel MOSFET 21 and a P-channel MO.
The gate of the SFET 22 is connected. The MOSF
The drain of ET21 is connected to the power supply line 15 connected to the first power supply V _DD , and the source is the MOSFET 22.
Is connected to the source of the
_Is connected to the ground line 17 connected to the power supply V _SS . The drain of the MOSFET 22 is connected to the output terminal 16.

Further, the input terminal 11 is connected to the gates of an N-channel MOSFET 24 and a P-channel MOSFET 25. The drain of the MOSFET 24 is connected to the output terminal 16, and the source is the MOSFET.
It is connected to the source of T25 and is also connected to the ground line 17 via a capacitor 26. This MOSF
The back gate of the ET 24 is connected to the ground line 17 together with the back gate of the MOSFET 21. The drain of the P-channel MOSFET 25 is connected to the ground line 17, and the back gate is the P-channel M.
It is connected to the power supply line 15 together with the back gate of the OSFET 22.

In the above configuration, when the potential of the output terminal of the internal circuit 10, that is, the input terminal 11 becomes high level, the MOSFET 14 becomes conductive, so that the output terminal 1
6 becomes low level. At this time, the load capacity is instantly increased to 18
The electric charge stored in the
It tries to flow to the ground line 17 through T14. Since this ground line 17 has an inductance 17a, an undershoot tends to occur due to this inductance 17a.

However, in this case, since the MOSFET 24 becomes conductive, the discharging current of the load capacitance 18 flows as the charging current of the capacitance 26. Therefore, the current flowing through the ground line 17 via the MOSFET 14 is reduced, and the undershoot US is suppressed as shown in FIG. When the potential of the input terminal 11 becomes high level, the MOSFE
T21 becomes conductive. Therefore, the capacitor 23 is charged via the MOSFET 21.

On the other hand, the output terminal of the internal circuit 10, that is,
When the potential of the input terminal 11 becomes low level, the MOS
Since the FET 13 becomes conductive, the output terminal 16 becomes high level. At this time, a charging current instantaneously flows from the first power supply _VDD to the load capacitance 18 via the power supply line 15 and the MOSFET 13. The power line 15 has an inductance 15a
Therefore, the inductance 15a tends to cause an overshoot.

However, in this case, since the MOSFET 22 becomes conductive, the charge stored in the capacitor 23 is discharged,
This discharge current passes through the MOSFET 22 and the load capacitance 18
Flows as a charging current. Therefore, the MOSFET 13
The current flowing through the load capacitance 18 via the load capacitor 18 decreases, and the overshoot OS is suppressed as shown in FIG.

Further, when the potential of the input terminal 11 becomes low level, the MOSFET 25 becomes conductive. For this reason,
The electric charge charged in the capacitor 26 is discharged via the MOSFET 25.

According to the above-mentioned embodiment, when the input terminal 11 of the output buffer 12 is at the high level, the capacitor 26 has the MOSF.
It is possible to reduce the instantaneous current that is charged via the ET 24 and flows through the MOSFET 14 to the ground line 17. Therefore, undershoot can be suppressed. Further, the capacitance 23 charged when the input terminal 11 of the output buffer 12 is at the high level is a
When the FET 22 becomes conductive, it is discharged and flows as a charging current to the load capacitance 18. Therefore, the instantaneous current flowing from the power supply line 15 to the load capacitance 18 via the MOSFET 13 can be reduced, and the overshoot can be suppressed. FIG. 3 shows a second embodiment of the present invention.
The same parts as those of the above are given the same reference numerals, and only different parts will be described.

In FIG. 1, MOSFETs 21, 22, 24 and 25 were used for charging and discharging the capacitors 23 and 26. In this embodiment, however, analog switches S1 and S2 are connected instead of the MOSFETs 21 and 22, and MOSFs are connected.
Analog switches S3 and S4 are connected instead of the ETs 24 and 25. N constituting the analog switch S1
Channel MOSFET 31 and analog switch S
The gate of the P-channel MOSFET 33 that constitutes 2 is
The inverter circuit 3 is connected to the input terminal 11
The gates of the P-channel MOSFET 32 forming the analog switch S1 and the N-channel MOSFET 34 forming the analog switch S2 are connected to each other via the gate 5.

The gates of the N-channel MOSFET 36 forming the analog switch S3 and the P-channel MOSFET 34 forming the analog switch S4 are connected to the input terminal 11 and connected to the analog switch S3 via the inverter circuit 40. Make up P
Channel MOSFET 37 and analog switch S
4 is connected to the gate of N-channel MOSFET 39.

In the case of this embodiment, the analog switch S1
~ S4 is used. The on resistance of the analog switch is constant regardless of the source and drain voltages of the MOSFET. Therefore, more than in the first embodiment,
Undershoot and overshoot can be suppressed. The present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the spirit of the invention.

[0027]

As described above in detail, according to the present invention, it is possible to provide the semiconductor device capable of sufficiently suppressing the voltage fluctuation due to the inductance of the wiring.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram shown for explaining the operation of FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional semiconductor device.

FIG. 5 is a diagram shown to explain the operation of FIG. 4;

[Explanation of symbols]

11 ... Input terminal, 12 ... Output buffer, 15 ... Power supply line, 16 ... Output terminal, 17 ... Ground line, 18 ... Load capacitance, 21-25 ... MOSFET, 23, 26 ... Capacitance, S
1 to S4 ... Analog switch.

Claims (5)

[Claims] 1. One end of a current path of a first conductivity type MOSFET is connected to a first power supply line, and the other end of a current path of this first conductivity type MOSFET is a second conductivity type MOSF.
This second conductivity type M is connected to one end of the current path of ET.
The other end of the current path of the OSFET is connected to a second power supply line, the gates of these first and second conductivity type MOSFETs are used as input terminals, and the connection point of the first and second conductivity type MOSFETs is an output terminal. And a first switch circuit in which a current path is connected between the first power supply line and the output terminal of the output buffer, and the input end of which is connected to the input terminal of the output buffer, The output terminal of the first switch circuit is provided between the second power supply line and the input terminal of the output buffer is at a high level. When the input terminal is low level,
A current path is connected between the first capacitor discharged through the first switch circuit, the output terminal of the output buffer and the second power supply line, and the input end of the output buffer is the input terminal of the output buffer. A second switch circuit connected to the second switch circuit, and an output terminal of the second switch circuit provided between the second power supply line and the input terminal of the output buffer at a high level. When it is charged through the switch circuit and the input terminal of the output buffer is low level,
A semiconductor device comprising: a second capacitor that is discharged through the second switch circuit. 2. The MOSFET of the second conductivity type, wherein the first switch circuit has a current path connected in series between the first power supply line and the output terminal of the output buffer.
And MOSFETs of the first conductivity type, the gates of these MOSFETs are connected to the input terminal of the output buffer, and the connection point of the current path of these MOSFETs is connected to one end of the first capacitance. The semiconductor device according to claim 1. 3. The second conductivity type MOSFET in which a current path is connected in series between the output terminal of the output buffer and the second power supply line in the second switch circuit.
And MOSFETs of the first conductivity type, the gates of these MOSFETs are connected to the input terminal of the output buffer, and the connection point of the current path of these MOSFETs is connected to one end of the second capacitance. The semiconductor device according to claim 1. 4. The first switch circuit is composed of first and second analog switches having a current path connected in series between the first power supply line and the output terminal of the output buffer. The semiconductor device according to claim 1, wherein an input end of the analog switch is connected to an input terminal of the output buffer, and an output end thereof is connected to one end of the first capacitor. 5. The second switch circuit includes first and second analog switches having a current path connected in series between the output terminal of the output buffer and the second power supply line. The semiconductor device according to claim 1, wherein an input end of the analog switch is connected to an input terminal of the output buffer, and an output end thereof is connected to one end of the second capacitor.