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JPH05291744A - Manufacture of multilayer interconnection board and insulating board with multilayer metal layer - Google Patents

Manufacture of multilayer interconnection board and insulating board with multilayer metal layer

Info

Publication number
JPH05291744A
JPH05291744A JP9096792A JP9096792A JPH05291744A JP H05291744 A JPH05291744 A JP H05291744A JP 9096792 A JP9096792 A JP 9096792A JP 9096792 A JP9096792 A JP 9096792A JP H05291744 A JPH05291744 A JP H05291744A
Authority
JP
Japan
Prior art keywords
metal
layer
metal layer
multilayer
interlayer connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9096792A
Other languages
Japanese (ja)
Inventor
Hajime Nakayama
肇 中山
Kenichi Takahashi
健一 高橋
Naoki Fukutomi
直樹 福富
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP9096792A priority Critical patent/JPH05291744A/en
Publication of JPH05291744A publication Critical patent/JPH05291744A/en
Pending legal-status Critical Current

Links

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

PURPOSE:To obtain a multilayer interconnection board having high density and high interlayer connection reliability by pattern-etching only an upper layer metal to form an interlayer connecting metal pole, burying them in an insulating material, exposing a head of the pole by surface polishing, and forming an upper conductor pattern thereon. CONSTITUTION:A three-layer metal foil made of a first metal layer 11 of a copper layer, a second metal layer 12 of a nickel layer and a third metal layer 13 of a copper layer is batch etched to form a first interconnection pattern. Then, the metal 11 is etched to form an interlayer connecting metal pole 16. Epoxy resin varnish is coated-cured to a height of the pole 16 to form an insulating layer 17, and a head of the pole is present only at the interlayer connecting part by surface polishing. After a plated resist pattern 18 is formed, a second interconnection pattern 19 of an upper conductor pattern is formed by an electroless plating method. Thus, the interconnection part can be densified while reliability remains.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は多層配線板の製造法およ
び多層金属層付絶縁基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board and an insulating substrate with a multilayer metal layer.

【0002】[0002]

【従来の技術】多層配線板の製造では層間接続技術が必
須であり、従来の層間接続技法としては、(1)配線パ
ターンおよび絶縁層を貫通する穴をあけた後、めっき等
によって穴内を金属化し層間の導通を得る方法、(2)
配線パターン上に絶縁層を形成した後、層間接続をすべ
き部分の絶縁層を除去し、その後表面金属化と同時に層
間接続を行う方法が行われている。
2. Description of the Related Art Interlayer connection technology is indispensable in the manufacture of multilayer wiring boards. The conventional interlayer connection technology is as follows: (1) After forming a hole through a wiring pattern and an insulating layer, metal is formed in the hole by plating or the like. (2)
After forming an insulating layer on a wiring pattern, a method of removing an insulating layer in a portion where interlayer connection is to be performed and then performing surface metallization and interlayer connection at the same time is performed.

【0003】[0003]

【発明が解決しようとする課題】(1)の方法は一般の
多層配線板の製造で行われている層間接続方法である
が、貫通穴の形成にドリルを用いるため、0.2mm径を
下回るような小径の形成は困難な上、穴位置精度も±3
0μm以上と十分でない。 (2)の方法は主に半導体の多層配線形成に用いられる
方法で、層間接続部の小径化や穴位置精度は、フォトマ
スクによる位置合わせ技術を用いるため(1)の方法に
比べ一桁優れている。しかし、この方法の場合、層間接
続用の穴が残るため、さらに配線を積み上げ多層化して
いく際の絶縁層形成時に穴に気泡が残ったり、層間接続
用穴の上に層間接続用穴を積み上げることが困難なこと
など問題が多い。本発明は、高密度で層間接続信頼性の
高い多層配線板の製造法およびその方法で使用され得る
多層金属層付絶縁基板を提供するものである。
The method (1) is an interlayer connection method which is generally used in the production of multilayer wiring boards. However, since a drill is used to form the through holes, the diameter is less than 0.2 mm. It is difficult to form such a small diameter, and the hole position accuracy is ± 3.
0 μm or more is not enough. The method (2) is mainly used for semiconductor multilayer wiring formation. The diameter of the interlayer connection and the hole position accuracy are superior to the method (1) by one digit because the alignment technology using a photomask is used. ing. However, in the case of this method, since holes for interlayer connection remain, air bubbles remain in the holes when insulating layers are formed when wiring is further stacked and multilayered, and holes for interlayer connection are stacked on the holes for interlayer connection. There are many problems such as difficulty. The present invention provides a method of manufacturing a multilayer wiring board having high density and high reliability of interlayer connection, and an insulating substrate with a multilayer metal layer that can be used in the method.

【0004】[0004]

【課題を解決するための手段】本願の第一の発明は、
(1A)エッチング条件が異なる少なくとも2種以上の
金属層から成る多層金属層を絶縁基板と一体化した多層
金属層付絶縁基板を準備し、(1B)多層金属層を加工
して、第一の配線パターンを形成し、(1C)第一の配
線パターンを構成している多層金属層の上層の金属層
を、後の工程で層間接続用金属柱となる部分を残してそ
れ以外の部分を、下層の金属層とのエッチング条件の違
いを利用して除去し、(1D)層間接続用金属柱の頭部
以外の部分に絶縁層を形成し、(1E)層間接続用金属
柱と導通した第二の配線パターンを形成する、工程を含
むことを特徴とする多層配線板の製造法である。
The first invention of the present application is
(1A) An insulating substrate with a multilayer metal layer in which a multilayer metal layer composed of at least two kinds of metal layers having different etching conditions is integrated with an insulating substrate is prepared. (1B) The multilayer metal layer is processed to A wiring pattern is formed, and (1C) the upper metal layer of the multi-layered metal layer forming the first wiring pattern is left except for a portion which will be a metal pillar for interlayer connection in a later step, and other portions. It is removed by utilizing the difference in etching conditions from the lower metal layer, and (1D) an insulating layer is formed on a portion other than the head of the metal column for interlayer connection, and (1E) is electrically connected to the metal column for interlayer connection. A method for manufacturing a multilayer wiring board, comprising the step of forming a second wiring pattern.

【0005】本願の第二の発明は、(2A)エッチング
条件が異なる少なくとも2種以上の金属層から成る多層
金属層を絶縁基板と一体化した多層金属層付絶縁基板を
準備し、(2B)多層金属層の上層の金属層を、後の工
程で層間接続用金属柱となる部分を残してそれ以外の部
分を、下層の金属層とのエッチング条件の違いを利用し
て除去し、(2C)残った金属層を加工して、第一の配
線パターンを形成し、(2D)層間接続用金属柱の頭部
以外の部分に絶縁層を形成し、(2E)層間接続用金属
柱と導通した第二の配線パターンを形成する、工程を含
むことを特徴とする多層配線板の製造法である。
A second invention of the present application is (2A) preparing an insulating substrate with a multilayer metal layer in which a multilayer metal layer composed of at least two kinds of metal layers having different etching conditions is integrated with the insulating substrate, (2B). The upper metal layer of the multi-layer metal layer is removed by using the difference in etching condition between the metal layer of the lower layer and the other part, leaving the part to be the metal pillar for interlayer connection in a later step, ) The remaining metal layer is processed to form a first wiring pattern, (2D) an insulating layer is formed on a portion other than the head of the interlayer connection metal column, and (2E) conduction with the interlayer connection metal column. The method for producing a multilayer wiring board is characterized by including the step of forming the second wiring pattern described above.

【0006】図1により本願の第一の発明の一実施例を
説明する。50μm厚の銅層の第一の金属層11、3μm
厚のニッケル層の第二の金属層12、15μm厚の銅層
の第三の金属層13より成る3層金属箔の第三の金属層
側表面をK処理(水酸化ナトリウム/リン酸ナトリウム
/亜塩素酸ナトリウムの水溶液による酸化処理)した
後、絶縁基板であるガラス布エポキシ樹脂プリプレーグ
14と積層プレスし、3層金属層を有する積層板を作成
した(図1(a))。絶縁基板としては、ポリイミドフ
ィルム等の合成樹脂フィルム、セラミック板等の無機質
材料も使用できる。絶縁基板としてはセラミック板を使
用する場合、第三の金属層13は厚膜導体であること
も、めっき導体であることもあり(この場合には日立化
成工業株式会社製セラミック配線板、商品名「HMA
C」が使用できる。)、3層金属層はめっき法によって
積み上げるのが一般的な方法となる。
An embodiment of the first invention of the present application will be described with reference to FIG. 50 μm thick copper first metal layer 11, 3 μm
The third metal layer side surface of the three-layer metal foil comprising the second metal layer 12 having a thick nickel layer and the third metal layer 13 having a copper layer having a thickness of 15 μm is K-treated (sodium hydroxide / sodium phosphate / After oxidation treatment with an aqueous solution of sodium chlorite), it was laminated and pressed with a glass cloth epoxy resin prepreg 14 which is an insulating substrate to prepare a laminate having a three-layer metal layer (FIG. 1A). As the insulating substrate, a synthetic resin film such as a polyimide film or an inorganic material such as a ceramic plate can be used. When a ceramic plate is used as the insulating substrate, the third metal layer 13 may be a thick film conductor or a plated conductor (in this case, a ceramic wiring board manufactured by Hitachi Chemical Co., Ltd., trade name "HMA
C "can be used. ) It is a general method to stack the three metal layers by plating.

【0007】次に25μm厚のフィルムレジストを形成
した後、配線パタ−ン部以外に相当するところのレジス
トを露光・現像によって除去した。続いて、塩化第二鉄
エッチング液を用いて3層金属箔68μmを一挙にエッ
チングし、0.2mm幅の3層金属層の第一の配線パター
ンを形成した(図1(b))。ただし、層間接続部分の
パターンは直径0.6mmの円形とした。3層金属箔を加
工して、第一の配線パターンを形成するには、エッチン
グ液による方法の他、放電加工法、レーザ加工法、ルー
ティング加工法及びこれらの組合せ加工法等が使用でき
る。
Next, after forming a film resist having a thickness of 25 μm, the resist corresponding to portions other than the wiring pattern portion was removed by exposure and development. Subsequently, 68 μm of the three-layer metal foil was etched all at once by using a ferric chloride etching solution to form a first wiring pattern of the three-layer metal layer having a width of 0.2 mm (FIG. 1 (b)). However, the pattern of the interlayer connection portion was circular with a diameter of 0.6 mm. In order to process the three-layer metal foil to form the first wiring pattern, an electric discharge machining method, a laser machining method, a routing machining method, a combination machining method thereof or the like can be used in addition to the method using an etching solution.

【0008】次に、再度フィルムレジストを形成した
後、上記円形パターン上に0.2mm径のレジストパター
ン15が残るように露光・現像した後(図1(c))、
ニッケルを溶解せず銅を溶解するアンモニア系エッチン
グ液で上層の50μm厚銅層である第一の金属層11を
エッチングし、直径0.2mm、高さ50μmの層間接続
用金属柱16を形成した(図1(d))。この段階で、
配線パターン厚みは18μmになった。ちなみに、この
エッチング工程では耐アルカリ性の溶剤現像タイプレジ
ストを使用した。層間絶縁信頼性を考慮すると、層間接
続用金属柱16の高さは20μm以上あることが好まし
い。
Next, after forming a film resist again, after exposing and developing so that a resist pattern 15 having a diameter of 0.2 mm remains on the circular pattern (FIG. 1 (c)),
The first metal layer 11, which is a copper layer having a thickness of 50 μm, is etched with an ammonia-based etching solution that does not dissolve nickel but dissolves copper to form metal columns 16 for interlayer connection having a diameter of 0.2 mm and a height of 50 μm. (FIG. 1 (d)). At this stage,
The wiring pattern thickness was 18 μm. By the way, in this etching process, an alkali resistant solvent developing type resist was used. Considering interlayer insulation reliability, the height of the metal columns 16 for interlayer connection is preferably 20 μm or more.

【0009】絶縁層17の形成を、エポキシ樹脂ワニス
を層間接続用金属柱16の高さまで塗布・硬化する方法
で行った(図1(f))。層間接続用金属柱上にもエポ
キシ樹脂層が薄く形成されたが、これは表面研磨で除去
でき、表面が平坦で、層間接続部分のみに金属柱の頭部
が現れた状態が形成できた(図1(g))。絶縁層の形
成は、フィルム材料をラミネートもしくはプレスする方
法などもある。また、金属と絶縁層との密着性を向上さ
せるために、金属表面処理もしくは層間密着促進ワニス
を塗布した後、絶縁層を形成することもできる。層間接
続用金属柱の頭部を出す方法も種々あるが、研磨法がも
っとも容易である上、表面の平坦化にも効果がある。層
間接続用金属柱の頭部は少なくともその一部が露出され
ておればよい。
The insulating layer 17 was formed by a method of applying and curing an epoxy resin varnish up to the height of the metal columns 16 for interlayer connection (FIG. 1 (f)). A thin epoxy resin layer was also formed on the metal columns for interlayer connection, but this could be removed by surface polishing, the surface was flat, and the state where the head of the metal column appeared only in the interlayer connection part was formed ( FIG. 1 (g)). The insulating layer may be formed by laminating or pressing a film material. Further, in order to improve the adhesion between the metal and the insulating layer, the insulating layer can be formed after the metal surface treatment or the interlayer adhesion promoting varnish is applied. There are various methods for exposing the head of the metal column for interlayer connection, but the polishing method is the easiest and is effective for planarizing the surface. At least a part of the head portion of the metal column for interlayer connection may be exposed.

【0010】めっき触媒付与後、めっきレジストパター
ン18を形成した後(図1(h))、無電解めっき法に
よって上部導体パターンである第二の配線パタ−ン19
を形成する(図1(i))。一方、3層以上の配線構造
を形成する場合には、図1(g)の絶縁層17及び層間
接続用金属柱頭11上に、配線パターン用金属層(第三
の金属層13、第二の金属層12に相当する)と層間接
続用金属層(第一の金属層11に相当する)をパネルめ
っきし、その後、第1層配線パターン12、13、及び
層間接続用金属柱11を形成した要領で、順次工程を進
めればよい。
After the plating catalyst is applied and the plating resist pattern 18 is formed (FIG. 1 (h)), the second wiring pattern 19 as the upper conductor pattern is formed by the electroless plating method.
Are formed (FIG. 1 (i)). On the other hand, when forming a wiring structure of three or more layers, a wiring pattern metal layer (third metal layer 13, second metal layer 13 or second metal layer 11) is formed on the insulating layer 17 and the interlayer connection metal pillar 11 in FIG. Panel plating of a metal layer 12) and a metal layer for interlayer connection (corresponding to the first metal layer 11) were performed, and then the first layer wiring patterns 12, 13 and the metal column 11 for interlayer connection were formed. The steps may be sequentially carried out according to the procedure.

【0011】このようにして得られた多層配線板は層間
金属柱頭部は0.2mm径のため、100mil格子の場
合、接続柱頭部端面距離は2.34mmとなった。上部導
体を0.2mm/0.2mm(ライン/スペース)と余裕を
持った設計をしても、ピン間5本、0.1mm/0.1mm
(ライン/スペース)であれば、ピン間10本と、配線
部に信頼性をもたせたまま高密度化が達成できた。また
下部導体もピン間4本の設計ができた。
In the multilayer wiring board thus obtained, the interlayer metal pillar head has a diameter of 0.2 mm, and thus the end surface distance of the connecting pillar head was 2.34 mm in the case of a 100 mil grid. Even if the upper conductor is designed with a margin of 0.2 mm / 0.2 mm (line / space), 5 pins between the pins, 0.1 mm / 0.1 mm
In the case of (line / space), it was possible to achieve high densification while maintaining the reliability of the wiring portion with 10 pins. The lower conductor was also designed with four pins between pins.

【0012】図2により本願の第二の発明の一実施例を
説明する。50μm厚の銅層の第一の金属層21、3μ
m厚のニッケル層の第二の金属層22、15μm厚の銅
層の第三の金属層23より成る3層金属箔の第三の金属
層側表面をK処理(水酸化ナトリウム/リン酸ナトリウ
ム/亜塩素酸ナトリウムの水溶液による酸化処理)した
後、絶縁基板であるガラス布エポキシ樹脂プリプレーグ
24と積層プレスし、3層金属層を有する積層板を作成
した(図2(a))。
An embodiment of the second invention of the present application will be described with reference to FIG. First metal layer 21, 3μ of 50 μm thick copper layer
The third metal layer side surface of the three-layer metal foil consisting of the second metal layer 22 of m-thick nickel layer and the third metal layer 23 of the 15-μm-thick copper layer is K-treated (sodium hydroxide / sodium phosphate). / Oxidation treatment with an aqueous solution of sodium chlorite) and laminated press with a glass cloth epoxy resin prepreg 24 which is an insulating substrate to produce a laminated plate having a three-layer metal layer (FIG. 2A).

【0013】次に、50μm厚の銅層の第一の金属層2
1上にフィルムレジストを形成した後、層間接続用金属
柱に相当するところ以外のレジストを露光・現像によっ
て除去した。ここでは耐アルカリ性の溶剤現像タイプレ
ジストを使用した。ニッケルを溶解せず銅を溶解するア
ンモニア系エッチング液で行い、上層の50μm厚の銅
層の第一の金属層21をエッチングし、直径0.2mm、
高さ50μmの層間接続用金属柱25を形成した(図2
(b))。この段階で、金属層厚みは層間接続用金属柱
25の部分を除いて18μmになった。
Next, the first metal layer 2 which is a copper layer having a thickness of 50 μm
After a film resist was formed on 1, the resist other than the portions corresponding to the metal columns for interlayer connection was removed by exposure and development. Here, an alkali resistant solvent developing type resist was used. An ammonia-based etching solution that does not dissolve nickel but dissolves copper is used to etch the first metal layer 21 of the upper copper layer having a thickness of 50 μm, and the diameter is 0.2 mm.
A metal pillar 25 for interlayer connection having a height of 50 μm was formed (FIG. 2).
(B)). At this stage, the thickness of the metal layer was 18 μm except for the portion of the metal column 25 for interlayer connection.

【0014】次に、数値制御駆動方式の放電加工機によ
って18μm金属層を切削加工し、第一の配線パターン
を形成した。これで得られた配線パターンは0.1mm/
0.1mm(ライン/スペース)であった。この段階で、
層間接続用金属柱を有する配線パターンを形成できた
(図2(c))。次に、絶縁層26の形成は、エポキシ
樹脂ワニスを層間接続用金属柱の高さまで塗布・硬化す
る方法で行った(図2(d))。層間接続用金属柱上に
もエポキシ樹脂層が薄く形成されたが、これは表面研磨
で除去でき、表面が平坦で、層間接続部分のみに金属柱
の頭部が現れた状態が形成できた(図2(e))。
Next, an 18 μm metal layer was cut by an electric discharge machine of a numerical control drive system to form a first wiring pattern. The wiring pattern thus obtained is 0.1 mm /
It was 0.1 mm (line / space). At this stage,
A wiring pattern having metal columns for interlayer connection could be formed (FIG. 2C). Next, the insulating layer 26 was formed by a method of applying and curing an epoxy resin varnish up to the height of the metal columns for interlayer connection (FIG. 2D). A thin epoxy resin layer was also formed on the metal columns for interlayer connection, but this could be removed by surface polishing, the surface was flat, and the state where the head of the metal column appeared only in the interlayer connection part was formed ( FIG. 2 (e)).

【0015】めっき触媒付与後、めっきレジストパター
ン27を形成した後(図2(f))、無電解めっき法に
よって上部導体パターンである第二の配線パタ−ン28
を形成する(図2(g))。このようにして、高密度な
多層配線板を製造することができた。
After the plating catalyst is applied and the plating resist pattern 27 is formed (FIG. 2 (f)), the second wiring pattern 28 which is the upper conductor pattern is formed by the electroless plating method.
Are formed (FIG. 2 (g)). In this way, a high-density multilayer wiring board could be manufactured.

【0016】以上第一及び第二の発明によって、高密度
で層間接続信頼性の高い多層配線板を製造することがで
きる。なお、本方式は絶縁基材の両側で行い、スルーホ
ールによって両側の導通をとれば、さらなる高多層化が
可能である。本発明の多層配線板は、通常の方法で形成
した多層配線板上に組合せて使用しても有効である。こ
の時、すでに形成した配線部との接続は例えばスルーホ
ール接続等による。
According to the first and second inventions described above, it is possible to manufacture a multi-layer wiring board having high density and high reliability of interlayer connection. It should be noted that this method is performed on both sides of the insulating base material, and if both sides are electrically connected by through holes, it is possible to further increase the number of layers. The multilayer wiring board of the present invention is also effective when used in combination with a multilayer wiring board formed by a usual method. At this time, the connection with the already formed wiring portion is, for example, through-hole connection.

【0017】本発明に於て、エッチング条件が異なる少
なくとも2種以上の金属層としては、異なる材質の金属
の組合せ、すなわち異なる金属、または異なる金属との
合金化したものの組合せ等が使用される。第一の金属層
と第三の金属層が同じ材質で、その間に挟まれた第二の
金属層が異なる材質であるものは実用上好ましい。
In the present invention, a combination of metals of different materials, that is, a combination of different metals or an alloy of different metals is used as at least two kinds of metal layers having different etching conditions. It is practically preferable that the first metal layer and the third metal layer are made of the same material, and the second metal layer sandwiched therebetween is made of a different material.

【0018】本発明でエッチング条件とは、エッチング
により配線パタ−ンを加工する条件であり、エッチング
条件が異なるとは、エッチング液による方法、放電加工
法、レーザ加工法、ルーティング加工法及びこれらの組
合せ加工法等のエッチングにより配線パタ−ンが加工で
きる条件が異なるということである。
In the present invention, the etching conditions are conditions for processing the wiring pattern by etching, and different etching conditions mean a method using an etching solution, an electric discharge machining method, a laser machining method, a routing machining method and these methods. This means that the conditions under which a wiring pattern can be processed by etching such as a combination processing method are different.

【0019】多層金属層の上層の金属層を、層間接続用
金属柱となる部分を残してそれ以外の部分を除去する場
合、上層の金属層のみでなく上層の金属層を含む複数の
金属層を同時に除去しても良い。すなわち層間接続用金
属柱が複数の金属層で構成されていても良い。層間接続
用金属柱の頭部以外の部分に絶縁層を形成する場合、層
間接続用金属柱の頭部の少なくとも一部が露出されてお
ればよい。
When the metal layer of the upper layer of the multi-layered metal layer is to be removed except for the portion which becomes the metal pillar for interlayer connection, a plurality of metal layers including not only the metal layer of the upper layer but also the metal layer of the upper layer. May be removed at the same time. That is, the metal column for interlayer connection may be composed of a plurality of metal layers. When the insulating layer is formed on a portion other than the head of the interlayer connecting metal column, at least a part of the head of the interlayer connecting metal column may be exposed.

【0020】[0020]

【発明の効果】本発明により、高密度で層間接続信頼性
の高い多層配線板の製造が可能になった。また、セラミ
ック基板との組合せにより、マルチチップモジュール基
板等への応用も容易になった。
According to the present invention, it is possible to manufacture a multilayer wiring board having a high density and high reliability of interlayer connection. Further, by combining with a ceramic substrate, application to a multi-chip module substrate etc. has become easy.

【図面の簡単な説明】[Brief description of drawings]

【図1】第一の発明の製造工程を示す断面図である。FIG. 1 is a cross-sectional view showing the manufacturing process of the first invention.

【図2】第二の発明の製造工程を示す断面図である。FIG. 2 is a cross-sectional view showing the manufacturing process of the second invention.

【符号の説明】[Explanation of symbols]

11 第一の金属層 12 第二の金属層 13 第三の金属層 14 絶縁基板 15 レジストパターン 16 層間接続用金属柱 17 絶縁層 18 めっきレジストパターン 19 第二の配線パタ−ン 21 第一の金属層 22 第二の金属層 23 第三の金属層 24 絶縁基板 25 層間接続用金属柱 26 絶縁層 27 めっきレジストパターン 28 第二の配線パタ−ン 11 First Metal Layer 12 Second Metal Layer 13 Third Metal Layer 14 Insulating Substrate 15 Resist Pattern 16 Metal Column for Interlayer Connection 17 Insulating Layer 18 Plating Resist Pattern 19 Second Wiring Pattern 21 First Metal Layer 22 Second metal layer 23 Third metal layer 24 Insulating substrate 25 Metal pillar for interlayer connection 26 Insulating layer 27 Plating resist pattern 28 Second wiring pattern

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】(1A)エッチング条件が異なる少なくと
も2種以上の金属層から成る多層金属層を絶縁基板と一
体化した多層金属層付絶縁基板を準備し、 (1B)多層金属層を加工して、第一の配線パターンを
形成し、 (1C)第一の配線パターンを構成している多層金属層
の上層の金属層を、後の工程で層間接続用金属柱となる
部分を残してそれ以外の部分を、下層の金属層とのエッ
チング条件の違いを利用して除去し、 (1D)層間接続用金属柱の頭部以外の部分に絶縁層を
形成し、 (1E)層間接続用金属柱と導通した第二の配線パター
ンを形成する、 工程を含むことを特徴とする多層配線板の製造法。
1. (1A) An insulating substrate with a multilayer metal layer in which a multilayer metal layer composed of at least two kinds of metal layers having different etching conditions is integrated with an insulating substrate, and (1B) processing the multilayer metal layer. Then, the first wiring pattern is formed, and (1C) the metal layer of the upper layer of the multi-layered metal layer forming the first wiring pattern is left, leaving a portion to be a metal pillar for interlayer connection in a later step. Other parts are removed by utilizing the difference in etching conditions from the lower metal layer, and (1D) an insulating layer is formed on the part other than the head of the metal column for interlayer connection, and (1E) metal for interlayer connection. A method of manufacturing a multilayer wiring board, comprising the step of forming a second wiring pattern that is continuous with the pillar.
【請求項2】(2A)エッチング条件が異なる少なくと
も2種以上の金属層から成る多層金属層を絶縁基板と一
体化した多層金属層付絶縁基板を準備し、 (2B)多層金属層の上層の金属層を、後の工程で層間
接続用金属柱となる部分を残してそれ以外の部分を、下
層の金属層とのエッチング条件の違いを利用して除去
し、 (2C)残った金属層を加工して、第一の配線パターン
を形成し、 (2D)層間接続用金属柱の頭部以外の部分に絶縁層を
形成し、 (2E)層間接続用金属柱と導通した第二の配線パター
ンを形成する、 工程を含むことを特徴とする多層配線板の製造法。
2. (2A) An insulating substrate with a multilayer metal layer in which a multilayer metal layer composed of at least two kinds of metal layers different in etching condition is integrated with an insulating substrate is prepared. The metal layer is removed by using the difference in etching conditions between the metal layer below and the metal layer for interlayer connection in the subsequent step, and the remaining metal layer is removed (2C). By processing, a first wiring pattern is formed, (2D) an insulating layer is formed on a portion other than the head of the interlayer connecting metal column, and (2E) a second wiring pattern electrically connected to the interlayer connecting metal column. A method of manufacturing a multilayer wiring board, comprising the steps of:
【請求項3】エッチング条件が異なる少なくとも2種以
上の金属層から成る多層金属層を絶縁基板と一体化した
多層金属層付絶縁基板。
3. An insulating substrate with a multi-layer metal layer, wherein a multi-layer metal layer comprising at least two metal layers having different etching conditions is integrated with the insulating substrate.
JP9096792A 1992-04-10 1992-04-10 Manufacture of multilayer interconnection board and insulating board with multilayer metal layer Pending JPH05291744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9096792A JPH05291744A (en) 1992-04-10 1992-04-10 Manufacture of multilayer interconnection board and insulating board with multilayer metal layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9096792A JPH05291744A (en) 1992-04-10 1992-04-10 Manufacture of multilayer interconnection board and insulating board with multilayer metal layer

Publications (1)

Publication Number Publication Date
JPH05291744A true JPH05291744A (en) 1993-11-05

Family

ID=14013271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9096792A Pending JPH05291744A (en) 1992-04-10 1992-04-10 Manufacture of multilayer interconnection board and insulating board with multilayer metal layer

Country Status (1)

Country Link
JP (1) JPH05291744A (en)

Cited By (11)

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Publication number Priority date Publication date Assignee Title
JPH07221456A (en) * 1994-01-31 1995-08-18 Hitachi Chem Co Ltd Manufacture of multilayer wiring board
WO2000005934A1 (en) * 1998-07-23 2000-02-03 Toyo Kohan Co., Ltd. Clad board for printed-circuit board, multilayered printed-circuit board, and method of manufacture thereof
WO2000052977A1 (en) * 1999-03-03 2000-09-08 Daiwa Co., Ltd. Method of manufacturing multilayer wiring board
WO2000076279A1 (en) * 1999-06-03 2000-12-14 Toyo Kohan Co.,Ltd. Process for producing printed wiring board, ic card and printed wiring substrate
JP2002050870A (en) * 2000-08-01 2002-02-15 Hitachi Chem Co Ltd Connecting substrate, multilayered wiring board and substrate for semiconductor package using it, method of manufacturing semiconductor package and it, method of manufacturing multilayered wiring board using the method, and method of manufacturing substrate for semiconductor package
EP1193755A1 (en) * 1999-06-10 2002-04-03 Toyo Kohan Co., Ltd. Clad plate for forming interposer for semiconductor device, interposer for semiconductor device, and method of manufacturing them
JP2002137328A (en) * 2000-11-02 2002-05-14 Hitachi Chem Co Ltd Method for processing thin plate-like article, method for manufacturing connection substrate using the method, connection substrate, multilayered wiring board and method for manufacturing the same, substrate for semiconductor package and method for manufacturing the same, and semiconductor package and manufacturing method thereof
US6527963B1 (en) 1998-11-18 2003-03-04 Daiwa Co., Ltd. Method of manufacturing multilayer wiring boards
WO2004073369A1 (en) * 2003-02-13 2004-08-26 Daiwa Co., Ltd. Multilayer printed wiring board and process for producing the same
JP2007134410A (en) * 2005-11-08 2007-05-31 Multi:Kk Printed wiring board with resistor circuit and method of manufacturing same
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Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07221456A (en) * 1994-01-31 1995-08-18 Hitachi Chem Co Ltd Manufacture of multilayer wiring board
WO2000005934A1 (en) * 1998-07-23 2000-02-03 Toyo Kohan Co., Ltd. Clad board for printed-circuit board, multilayered printed-circuit board, and method of manufacture thereof
KR100615382B1 (en) * 1998-07-23 2006-08-25 도요 고한 가부시키가이샤 Clad board for printed-circuit board, multilayered printed-circuit board, and method of manufacture thereof
US6730391B1 (en) * 1998-07-23 2004-05-04 Toyo Kohan Co., Ltd. Clad board for printed-circuit board, multilayered printed-circuit board, and method of manufacture thereof
US6579565B2 (en) * 1998-07-23 2003-06-17 Toyo Kohan Co., Ltd. Clad sheet for printed circuit board, a multilayered printed circuit board using thereof and manufacturing method thereof
US6527963B1 (en) 1998-11-18 2003-03-04 Daiwa Co., Ltd. Method of manufacturing multilayer wiring boards
US6555209B1 (en) 1999-03-03 2003-04-29 Daiwa Co., Ltd. Method of manufacturing multilayer wiring board
WO2000052977A1 (en) * 1999-03-03 2000-09-08 Daiwa Co., Ltd. Method of manufacturing multilayer wiring board
WO2000076279A1 (en) * 1999-06-03 2000-12-14 Toyo Kohan Co.,Ltd. Process for producing printed wiring board, ic card and printed wiring substrate
EP1193755A1 (en) * 1999-06-10 2002-04-03 Toyo Kohan Co., Ltd. Clad plate for forming interposer for semiconductor device, interposer for semiconductor device, and method of manufacturing them
EP1193755A4 (en) * 1999-06-10 2007-07-11 Toyo Kohan Co Ltd Clad plate for forming interposer for semiconductor device, interposer for semiconductor device, and method of manufacturing them
JP4408009B2 (en) * 1999-06-10 2010-02-03 東洋鋼鈑株式会社 Manufacturing method of interposer for semiconductor device
JP2002050870A (en) * 2000-08-01 2002-02-15 Hitachi Chem Co Ltd Connecting substrate, multilayered wiring board and substrate for semiconductor package using it, method of manufacturing semiconductor package and it, method of manufacturing multilayered wiring board using the method, and method of manufacturing substrate for semiconductor package
JP2002137328A (en) * 2000-11-02 2002-05-14 Hitachi Chem Co Ltd Method for processing thin plate-like article, method for manufacturing connection substrate using the method, connection substrate, multilayered wiring board and method for manufacturing the same, substrate for semiconductor package and method for manufacturing the same, and semiconductor package and manufacturing method thereof
WO2004073369A1 (en) * 2003-02-13 2004-08-26 Daiwa Co., Ltd. Multilayer printed wiring board and process for producing the same
JP2007134410A (en) * 2005-11-08 2007-05-31 Multi:Kk Printed wiring board with resistor circuit and method of manufacturing same
JP4713305B2 (en) * 2005-11-08 2011-06-29 株式会社マルチ Printed wiring board with resistance circuit and manufacturing method thereof
JP2010199624A (en) * 2010-06-01 2010-09-09 Hitachi Chem Co Ltd Method of manufacturing connection substrate using thin plate type article, connection substrate, method of manufacturing multilayer wiring board, multilayer wiring board, method of manufacturing substrate for semiconductor package, method of manufacturing substrate for semiconductor package and semiconductor package, and semiconductor package

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