JPH05299610A - Semiconductor integrated circuit device and formation thereof - Google Patents

Abstract

PURPOSE:To improve reliability in operation of a circuit arranged on the main surface of a well region within a well isolating region and also realize high speed operation of a circuit arranged on the main surface of a well region outside the well isolating region in a semiconductor integrated circuit device of a double (or triple)-well structure. CONSTITUTION:In a semiconductor integrated circuit device of a double-well structure, impurity concentration at the surface of a well region 2M within the well isolating region 31 is set equal to or higher than the impurity concentration at the surface of a well region 2 outside the well isolating region 31. Moreover, the well region 2M is given the dielectric strength against a substrate 1. Moreover, the well region 2M is formed on the self-alignment basis for the well isolating region 31.

Description

Detailed Description of the Invention

[0001]

The present invention relates to relates to a semiconductor integrated circuit device, in particular, SRAM (S tatic R andom A ccess M em
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having an ory).

[0002]

2. Description of the Related Art An SRAM as a volatile semiconductor memory device is described in JP-A-3-234055. In this kind of SRAM, a memory cell for storing 1 [bit] of information is arranged at each intersection of a complementary data line and a word line.

[0003] The memory cell flip-flop circuits and two transfer MOSFET (M etal O xide S emicon
composed of a ductor F ield E ffect T ransistor) . The transfer MOSFET connects one semiconductor region to the input / output terminal of the flip-flop circuit and connects the other semiconductor region to the complementary data line. This transfer MOSFET is
Connect the gate electrode to the word line and conduct with this word line,
Non-conduction is controlled. The flip-flop circuit is configured as an information storage unit and includes two driving MOSFETs and two driving MOSFETs.
It is composed of individual load MOSFETs. Driving MOSF
The ET connects the drain region to one semiconductor region of one transfer MOSFET and connects the source region to the reference voltage line (source line). The gate electrode of the driving MOSFET is connected to one semiconductor region of the other transfer MOSFET. The load MOSFET is one transfer MOSF
The drain region is connected to one semiconductor region of ET, and the source region is connected to the power supply voltage wiring (source line).

Both the transfer MOSFET and the drive MOSFET of the memory cell are of n-channel conductivity type. The load MOSFET of the memory cell is of p-channel conductivity type. That is, the memory cell is a completely complementary M
OSFET (full CMOS: C omplementary M etal O
consisting of xide S emiconductor F ield E ffect T ransistor).

The transfer MOSFET is a so-called LDD ( L i
The ghtly D oped D rain structure is adopted. In the transfer MOSFET adopting the LDD structure, an n-type semiconductor region having a low impurity concentration is formed on the channel forming region side of the n-type semiconductor region having a high impurity concentration in the drain region. That is,
The transfer MOSFET adopting the LDD structure can relax the electric field strength near the drain region, reduce the generation of hot carriers, and prevent the deterioration of the threshold voltage with time. Any improvement in information read characteristics can be achieved.

The driving MOSFET is a so-called DDD ( D oubl
e D iffused D rain) structure is employed. In the driving MOSFET adopting the DDD structure, the diffusion dimension of the region corresponding to the current path of the n-type semiconductor region set to the low impurity concentration of the source region and the drain region is the physical diffusion speed of the impurity. Since the size can be set to a minute size determined by the difference, the parasitic resistance added to the current path can be reduced.
That is, the driving MOSFET adopting the DDD structure can improve the drivability and can improve the information retention characteristic (data retention characteristic) of the memory cell.

The load MOSFET is the drive M
Placed on top of OSFET, so-called SOI (S ilicon O
n I nsulator or Thin Film Transistor) structure is employed. In the load MOSFET, a channel forming region is arranged on the surface of the gate electrode with a gate insulating film interposed.
The source region is connected to one end of the channel forming region and the drain region is connected to the other end. The gate electrode is formed of a lower polycrystalline silicon film, and the channel forming region, the source region and the drain region are formed of an upper polycrystalline silicon film.

A plurality of the memory cells are regularly arranged in a matrix to form a memory cell array. Peripheral circuits are arranged around the outer periphery of the memory cell array. The peripheral circuits mainly include a direct peripheral circuit that directly controls the circuit operation of the memory cell and an indirect peripheral circuit that controls the circuit operation of the direct peripheral circuit. The direct peripheral circuit includes a decoder circuit, a driver circuit, a sense amplifier circuit and the like. The indirect peripheral circuit includes an input / output circuit and an address buffer circuit. The peripheral circuit is mainly composed of complementary MOSFETs for the purpose of low power consumption and high-speed circuit operation.

[0009]

The inventor of the present invention has found that the SRAM
Prior to the development of, the following problems were discovered.

(1) The SRAM is composed of a p-type semiconductor substrate, and has a double well structure in which a p-type well region is formed on the main surface of the n-type well isolation region for the purpose of preventing undershoot. The memory cell array is arranged on the main surface of the p-type well region in the n-type well isolation region. The double well structure is so called because the cross-sectional structure of the n-type well isolation region is composed of double diffusion regions including the p-type well region. When the regions are arranged, this n-type well region is called a triple well structure. The double well structure described above can form a potential barrier region at the pn junction between the p-type semiconductor substrate, the n-type well isolation region, and the p-type well region. That is, α rays are incident on the p-type semiconductor substrate,
When minority carriers are generated by the incidence of α rays, the minority carriers are prevented from invading the p-type well region in which the memory cell array is arranged, so that an SRAM with high α-ray soft error resistance can be constructed.

When an n-type semiconductor substrate is used for the SRAM, the p-type semiconductor substrate on which the n-type semiconductor substrate and the memory cell array are arranged.
Since only one pn junction can be formed with the type well region, if minority carriers are generated in the n-type semiconductor substrate,
Intrusion of minority carriers into the p-type well region is predicted, and α
It is considered that the line soft error resistance is slightly reduced.

Each of the p-type well region inside the n-type well isolation region and the p-type well region outside the n-type well isolation region is
In the SRAM manufacturing process, they are formed in the same process in order to avoid an increase in the number of manufacturing process steps.

However, the impurity concentration on the surface of the p-type well region in the n-type well isolation region is lowered (eroded) by the impurity concentration on the surface of the n-type well isolation region.
The impurity concentration on the surface of the type well region is lower than the impurity concentration on the surface of the p-type well region outside the n-type well isolation region. For this reason, the threshold voltage of each of the transfer MOSFET and the drive MOSFET of the memory cell is lowered, and the noise margin is deteriorated (because the information stored in the memory cell is more likely to be inverted by noise). The information retention characteristic of the SRAM deteriorates.

In order to solve the above problem, if the impurity concentration on the surface of the p-type well region is set to be high overall, the impurity concentration on the surface of the p-type well region outside the n-type well isolation region becomes high. .. Therefore, the n-channel MOSFET of the peripheral circuit arranged on the main surface of the p-type well region
On the contrary, the threshold voltage rises and the switching operation speed decreases, so that the circuit operation speed of the SRAM deteriorates.

(2) n described in the above problem (1)
Since the type well isolation region is diffused deeper than the respective diffusion depths of the p type well region and the n type well region, the impurity concentration on the surface of the n type well isolation region is lowered. For this reason,
In the region where the impurity concentration on the surface of the n-type well isolation region is lowered, the p-type well region and the p-type well region in the n-type well isolation region are formed.
Withstand voltage between the semiconductor substrate and the semiconductor substrate deteriorates.

(3) In the load MOSFET of the memory cell of the SRAM, a channel forming region, a source region and a drain region are arranged on the surface of the gate electrode with a gate insulating film interposed. The gate electrode is formed by depositing a polycrystalline silicon film and then performing patterning by anisotropic etching for the purpose of fine processing. As the gate insulating film, a silicon oxide film deposited by a CVD method or a laminated film mainly containing the silicon oxide film is used mainly for the purpose of making the film thickness uniform.

However, the shape of the corner between the upper surface and the side surface of the gate electrode of the load MOSFET is formed into a sharp shape by anisotropic etching. In particular,
Since the load MOSFET adopts the SOI structure and the gate electrode is formed on the region where the underlying stepped shape exists, when the end of the gate electrode is located in the underlying stepped shape, the corner of the surface of the gate electrode is formed. The part is formed in a sharp shape having an acute angle. Therefore, electric field concentration occurs at the corners of the surface of the gate electrode, or the film quality of the gate insulating film formed along the corners of the surface of the gate electrode deteriorates, and the dielectric strength of the gate insulating film of the load MOSFET is increased. Is significantly deteriorated.

In the worst case, a short circuit occurs between the gate electrode of the load MOSFET and the source or drain region. That is, one load M of the memory cell
The power supply voltage is supplied to the information storage node connected to the drain region of the OSFET, and the power supply voltage is supplied to the information storage node connected to the drain region of the other load MOSFET, which should not be supplied originally, thereby causing a standby current failure. Occurs.

(4) The drain region of the load MOSFET is connected to the drain region (corresponding to an information storage node) of the driving MOSFET of the memory cell of the SRAM. The drain region of this driving MOSFET and the load M
The connection with the drain region of the OSFET is performed via an electrode (polycrystalline silicon film in the same layer) extracted from the gate electrode of another load MOSFET in the memory cell. The drain region of the driving MOSFET and the electrode are connected to each other through an opening (connection hole) formed in the interlayer insulating film covering the main surface of the drain region of the driving MOSFET.

The connection structure of the electrode to the drain region of this driving MOSFET is formed by the following manufacturing process. First, a driving MOSFET is formed on the main surface set in the (100) crystal plane of the p-type well region formed in the n-type well isolation region of the p-type semiconductor substrate. Next, an interlayer insulating film is formed on the main surface of the drain region of this driving MOSFET. The interlayer insulating film is formed of a silicon oxide film deposited by the CVD method. Next, the MOS for driving the interlayer insulating film
An opening is formed on the main surface of the drain region of the FET. Then, a polycrystalline silicon layer is formed on the entire surface of the interlayer insulating film, the polycrystalline silicon layer being in contact with the main surface of the drain region through an opening at a part thereof. The polycrystalline silicon film is deposited by the CVD method, and an n-type impurity that reduces the resistance value is introduced into the polycrystalline silicon film during or after the deposition. Next, the polycrystalline silicon film is subjected to patterning, and the patterned electrode is subjected to heat treatment for the purpose of crystallization to form the gate electrode of the load MOSFET and the above-mentioned electrode.

However, since the electrode connected to the main surface of the drain region of the driving MOSFET is subjected to heat treatment for the purpose of crystallization after patterning of the polycrystalline silicon film, the electrode is voluminous by cooling after the heat treatment. Shrinkage occurs. The stress due to the volume contraction of the electrode has a difference in thermal expansion coefficient between the polycrystalline silicon film of the electrode and the silicon oxide film of the interlayer insulating film. Concentrate on the main surface of the drain region. Therefore, a crystal defect occurs from the main surface of the drain region across the pn junction between the drain region and the p-type well region, so that the amount of leak current at the information storage node of the memory cell increases and the standby current of the SRAM is increased. The amount increases. Also,
The information retention characteristic of the SRAM memory cell deteriorates. It has been confirmed by the present inventor that the above-mentioned crystal defects occur along the (111) crystal plane because the main surface of the p-type well region is set to the (100) crystal plane.

(5) The transfer MOSFET of the SRAM memory cell and the n-channel MOSFET of the peripheral circuit each have an LDD structure. The MOSFET adopting the LDD structure is formed by the following manufacturing process.

First, a gate electrode is formed on the main surface of the p-type well region with a gate insulating film interposed. Next, using the gate electrode or a mask for patterning the gate electrode, an n-type impurity is introduced into the main surface of the p-type well region at a low impurity concentration. Next, a sidewall spacer is formed on the sidewall of the gate electrode in the gate length direction.
The sidewall spacer can be formed only on the sidewall of the gate electrode by depositing a silicon oxide film on the entire surface by the CVD method and performing anisotropic etching on the entire surface of the silicon oxide film by an amount corresponding to the deposited film thickness. .. Next, using the sidewall spacer and the gate electrode as a mask, an n-type impurity is introduced into the main surface of the p-type well region at a high impurity concentration. In any case, the introduction of the n-type impurity is performed by ion implantation with high controllability of the impurity concentration. Next, the introduced n-type impurity is stretched and diffused to form an n-type semiconductor region having a low impurity concentration and an n-type semiconductor region having a high impurity concentration in the MOSFET adopting the LDD structure.

However, in the MOSFET adopting the LDD structure, volume contraction occurs in the gate electrode due to the temperature cycle during the SRAM manufacturing process. The volume contraction of the gate electrode causes stress concentration on the main surfaces of the source region and the drain region at the open end of the side wall of the gate electrode (the side opposite to the side contacting the side wall of the gate electrode). .. In addition, the stress concentration portion of each main surface of the source region and the drain region is
Since the n-type impurity having a particularly high impurity concentration is introduced by ion implantation, damage due to the introduction of the n-type impurity occurs. Therefore, a crystal defect is generated across the pn junction between the main surface of each of the source region and the drain region and the p-type well region. Memory cell transfer memory
At T, when the source region or the drain region is used as the information storage node of the memory cell, the amount of leak current of the information storage node increases and the amount of standby current of the SRAM increases. In addition, the information retention characteristic of the memory cell of the SRAM deteriorates. It has been confirmed by the present inventor that crystal defects are generated along the (111) crystal plane, similarly to the problem (4).

The objects of the present invention are as follows.

(1) In a semiconductor integrated circuit device adopting a double well structure (or a triple well structure), it is possible to improve the operational reliability of the circuit arranged on the main surface of the well region in the well isolation region. In addition, the operating speed of the circuit arranged on the main surface of the well region outside the well isolation region is increased.

(2) In a semiconductor integrated circuit device having an SRAM in which memory cells are arranged in the well region in the well isolation region, the information holding characteristic of the SRAM is improved.

(3) To improve the degree of integration in a semiconductor integrated circuit device which employs a double well structure.

(4) In a semiconductor integrated circuit device adopting a double well structure, the breakdown voltage between the well region in the well isolation region and the substrate is improved.

(5) In the semiconductor integrated circuit device adopting the double well structure, the number of steps in the manufacturing process is reduced.

(6) MISFET adopting SOI structure
(MetalInsulatorSemiconductorFieldEffect
Transistor) in a semiconductor integrated circuit device,
To improve the withstand voltage of the gate insulating film of the MISFET
It

(7) The above object (6) is achieved and the controllability of the film thickness of the gate insulating film of the MISFET is improved.

(8) The object (6) is achieved and the number of steps in the manufacturing process of the semiconductor integrated circuit device is reduced.

(9) The object (6) is achieved, and the surface of the semiconductor integrated circuit device is flattened.

(10) MISFE adopting SOI structure
In a semiconductor integrated circuit device having an SRAM having a memory cell of T, a standby current defect is prevented.

(11) In a semiconductor integrated circuit device in which electrodes are connected to the source region or the drain region of the MISFET, the occurrence of crystal defects in the connection region is prevented.

(12) In the semiconductor integrated circuit device in which the electrodes are connected to the source region or the drain region of the MISFET, the number of manufacturing process steps is reduced.

(13) MISFET for driving memory cell
In the semiconductor integrated circuit device having the SRAM in which the load element is connected to the drain region of, the power consumption is reduced.

(14) MISFET for driving memory cell
In a semiconductor integrated circuit device having an SRAM in which a load element is connected to the drain region of the memory cell, the information retention characteristic of the memory cell is improved.

(15) In the semiconductor integrated circuit device, wherein a sidewall spacer is formed on the sidewall of the gate electrode of the MISFET, and the sidewall spacer is used as a mask to form the source region and the drain region, respectively.
The generation of crystal defects occurring in the source region and the drain region of the ISFET is prevented.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0042]

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) A first semiconductor region of a second conductivity type is formed in a first region of a main surface of a semiconductor substrate of a first conductivity type, and a second semiconductor region of the first conductivity type is formed in a second region of the main surface of the semiconductor substrate. A second semiconductor region that is formed and has a higher impurity concentration than that of the semiconductor substrate is formed, and a third semiconductor region of the first conductivity type is formed on the main surface of the first semiconductor region, and the second semiconductor region is formed. , A semiconductor integrated circuit device in which a first conductivity type channel MISFET is formed on each main surface of the third semiconductor region, the impurity concentration of the surface of the third semiconductor region is the impurity concentration of the surface of the second semiconductor region. Is set equal to or higher than.

(2) The semiconductor integrated circuit device according to the above-mentioned means (1) is equipped with an SRAM, and the first conductivity type channel is formed on the main surface of the third semiconductor region of the main surface of the first semiconductor region. The MISFET constitutes a flip-flop circuit of an SRAM memory cell, and the first conductivity type channel MISFET formed on the main surface of the second semiconductor region is the S-type.
A peripheral circuit that directly or indirectly drives the memory cell of the RAM is configured.

(3) The third semiconductor region described in the means (1) or (2) is formed in self-alignment with the first semiconductor region.

(4) A second conductive type first semiconductor region is formed in the first region of the main surface of the first conductive type semiconductor substrate, and a first conductive type is formed in the second region of the main surface of the semiconductor substrate. A semiconductor integrated circuit device in which a second semiconductor region formed and having a higher impurity concentration than that of the semiconductor substrate is formed, and a third semiconductor region of the first conductivity type is formed on the main surface of the first semiconductor region. A fourth semiconductor region formed of the second conductivity type and having a higher impurity concentration than that of the first semiconductor region in a region of the main surface of the first semiconductor region along the outer periphery of the third semiconductor region. Make up.

(5) A first semiconductor region of the second conductivity type is formed in the first region of the main surface of the semiconductor substrate of the first conductivity type, and a first conductivity type is formed in the second region of the main surface of the semiconductor substrate. In a semiconductor integrated circuit device, a second semiconductor region formed and having a higher impurity concentration than that of the semiconductor substrate is formed, and a third semiconductor region of the first conductivity type is formed on the main surface of the first semiconductor region. In the forming method, a step of forming a first mask having an opening in the first region on the main surface of the semiconductor substrate, the first mask is used, and a second conductive type first mask is formed on the main surface of the semiconductor substrate. A step of introducing an impurity and diffusing the first impurity to form a first semiconductor region of the second conductivity type; and using the first mask, a main surface of the first semiconductor region of the first conductivity type is formed. Introducing a second impurity, removing the first mask, Forming a second mask in which the second region is opened or a second mask in which the second region and the first region are opened on the main surface of the conductor substrate; and using the second mask, the semiconductor A third impurity of the first conductivity type is introduced into the main surface of the substrate, and the third impurity, the second impurity
Each step of diffusing each of the impurities to form each of the second semiconductor region and the third semiconductor region is provided.

(6) A second conductive type first semiconductor region is formed in the first region of the main surface of the first conductive type semiconductor substrate, and the first conductive type is formed in the second region of the main surface of the semiconductor substrate. In a semiconductor integrated circuit device, a second semiconductor region formed and having a higher impurity concentration than that of the semiconductor substrate is formed, and a third semiconductor region of the first conductivity type is formed on the main surface of the first semiconductor region. In the forming method, a step of forming a first mask having an opening in the first region on the main surface of the semiconductor substrate, the first mask is used, and a second conductive type first mask is formed on the main surface of the semiconductor substrate. Introducing an impurity and introducing a second impurity that is of the first conductivity type and has a slow diffusion rate with respect to the first impurity; removing the first mask; and removing the first mask on the main surface of the semiconductor substrate. A second mask in which the second region is opened, or before Forming a second mask having openings in the second region and the first region; using the second mask, introducing a third impurity of the first conductivity type into the main surface of the semiconductor substrate; And diffusing each of the first impurity and the second impurity to form each of the second semiconductor region, the first semiconductor region, and the third semiconductor region.

(7) A semiconductor integrated circuit device having a MISFET in which a gate insulating film is provided on the surface of a channel forming region or a gate electrode and a gate electrode or a channel forming region which crosses the channel forming region or the gate electrode is formed. Forming a channel forming region or a gate electrode by depositing a semiconductor layer or a gate electrode layer on the entire surface of the substrate, patterning the semiconductor layer or the gate electrode layer, and forming the channel forming region or the gate electrode. A part of the film thickness of the electrode is oxidized or nitrided from the surface to form an oxide film or a nitride film having a film thickness larger than that of the native silicon oxide film, and the channel formation region or the surface of the gate electrode. And a step of forming a gate insulating film on the surface of the channel formation region or the gate electrode. , The upper and side surfaces of the channel forming region or the gate electrode, and interposing the gate insulating film comprises a respective step of forming the channel formation region or the gate electrode or the channel forming region across the gate electrode.

(8) In the step of forming the gate insulating film in the step described in the means (7), the channel forming region in the step or the oxide film or the nitride film on the surface of the gate electrode is removed, and then the channel forming region is formed. Alternatively, this is a step of newly forming a gate insulating film on the surface of the gate electrode.

(9) In the step of forming the gate insulating film in the step described in the above means (7), the step of forming the gate insulating film by the oxide film or the nitride film on the surface of the channel forming region or the gate electrode in the step Or a step of forming a gate insulating film with a composite film in which an insulating film is newly deposited on the surface of the oxide film or the nitride film.

(10) A semiconductor integrated circuit device having a MISFET in which a gate insulating film is provided on the surface of a channel forming region or a gate electrode and a gate electrode or a channel forming region which crosses the channel forming region or the gate electrode is formed. Forming a channel forming region or a gate electrode by depositing a semiconductor layer or a gate electrode layer on the entire surface of the substrate, patterning the semiconductor layer or the gate electrode layer, and forming the channel forming region or the gate electrode. A step of forming a side wall spacer on the side surface of the electrode, a part of the film thickness of the channel formation region or the gate electrode is oxidized or nitrided from the surface, and an oxide film having a film thickness larger than that of the native silicon oxide film is formed. A film or a nitride film is formed, and the shape of the corner of the channel formation region or the surface of the gate electrode is changed. The step of forming a gate insulating film on the surface of the channel forming region or the gate electrode, the channel forming region with the gate insulating film interposed on the upper and side surfaces of the surface of the channel forming region or the gate electrode. Alternatively, each step of forming a gate electrode or a channel formation region across the gate electrode is provided.

(11) Means (7) to (10)
The semiconductor integrated circuit device described in any one of
Is mounted, and the MISFET constitutes a load MISFET of the flip-flop circuit of the SRAM memory cell.

(12) On the main surface of the second semiconductor region of the second conductivity type formed on the main surface of the first semiconductor region of the first conductivity type,
In a method of manufacturing a semiconductor integrated circuit device in which a silicon film is connected through an opening formed in an insulating film on the main surface of the second semiconductor region, a second conductive film is formed on the main surface of the first conductive type first semiconductor region. Forming a second semiconductor region of the mold, forming an insulating film on the main surface of the second semiconductor region,
An opening is formed on the second semiconductor region of the insulating film, and a region corresponding to the inside of the opening has the same conductivity type as the second semiconductor region on the main surface of the first semiconductor region and the second semiconductor region. A step of forming a third semiconductor region having a deeper junction depth, and contacting the respective main surfaces of the second semiconductor region and the third semiconductor region through an opening formed in the insulating film on the entire surface of the insulating film. Deposit a silicon film by the CVD method,
Each step of patterning this silicon film to form an electrode or wiring is provided.

(13) On the main surface of the second semiconductor region of the second conductivity type formed on the main surface of the first semiconductor region of the first conductivity type,
In a method of manufacturing a semiconductor integrated circuit device in which a silicon film is connected through an opening formed in an insulating film on the main surface of the second semiconductor region, a second conductive film is formed on the main surface of the first conductive type first semiconductor region. Forming a second semiconductor region of the mold, forming an insulating film on the main surface of the second semiconductor region,
Forming an opening on the second semiconductor region of the insulating film,
Depositing a silicon film in contact with the main surface of the second semiconductor region through an opening formed in the insulating film on the entire surface of the insulating film; performing high temperature annealing for crystallizing the silicon film; Each step of patterning the film to form an electrode or wiring is provided.

(14) Means (12) or means (1)
The semiconductor integrated circuit device described in 3) has an SRAM mounted therein, the second semiconductor region is a drain region of a driving MISFET of a flip-flop circuit of a memory cell of the SRAM, and the electrode is connected to a power supply voltage. ..

(15) In a method of manufacturing a semiconductor integrated circuit device having a MISFET, a step of forming a gate electrode on the main surface of a semiconductor region of the first conductivity type with a gate insulating film interposed, and a gate length of the gate electrode. Forming a sidewall spacer having an insulating property on the side wall in the direction,
Forming a mask covering at least the surface of the sidewall spacer, and ion-implanting a second conductivity type impurity in a region other than the gate electrode, the sidewall spacer and the mask on the main surface of the first conductivity type semiconductor region. Each of the steps includes the step of introducing by implantation, forming the second conductivity type source region and the drain region with the second conductivity type impurity, and forming the MISFET.

[0058]

According to the above-mentioned means (1), the following operational effects can be obtained. (1) The impurity concentration of the surface of the third semiconductor region formed on the main surface of the first semiconductor region is set high (the impurity concentration of the surface is reduced by the impurity concentration of the first semiconductor region, the third semiconductor region is reduced). Of the first conductivity type channel MISFET on the main surface of the third semiconductor region is increased, so that the cutoff current of the first conductivity type channel MISFET is increased. It is possible to reduce the leak current of the semiconductor integrated circuit device. (2) The impurity concentration of the surface of the second semiconductor region is independently set lower than the impurity concentration of the surface of the third semiconductor region formed on the main surface of the first semiconductor region. Since the threshold voltage of the first conductivity type channel MISFET on the main surface can be lowered, the switching operation speed of the first conductivity type channel MISFET can be increased and the circuit operation speed of the semiconductor integrated circuit device can be increased.

According to the above-mentioned means (2), the following function and effect can be obtained in addition to the function and effect of the means (1). (1) Since the leak of the information stored in the information storage node of the flip-flop circuit (information storage section) of the memory cell is reduced and the inversion can be prevented, the information holding characteristic of the SRAM can be improved. (2) Since the circuit operation speed of the peripheral circuit can be increased, and both the information write operation speed and the information read operation speed of the memory cell can be increased (the access time can be increased), the SRAM circuit operation speed can be increased. Can be realized.

According to the above-mentioned means (3), in addition to the function and effect of the means (1) or (2), the arrangement position of the third semiconductor region with respect to the arrangement position of the first semiconductor region is manufactured. Since the size can be reduced by the amount corresponding to the mask alignment margin in the process, useless areas on the main surface of the semiconductor substrate can be eliminated, and the degree of integration of the semiconductor integrated circuit device can be improved.

According to the above-mentioned means (4), the impurity concentration around the outer periphery of the third semiconductor region on the main surface of the first semiconductor region (the impurity concentration in this portion is reduced by diffusion of the first semiconductor region). Is increased in the fourth semiconductor region and the extension of the depletion region extending from the pn junction between the first semiconductor region and the third semiconductor region into the first semiconductor region can be reduced.
The junction breakdown voltage between the third semiconductor region on the main surface of the semiconductor region and the semiconductor substrate can be improved. If the junction breakdown voltage is improved, the distance between the third semiconductor region on the main surface of the first semiconductor region and the semiconductor substrate, that is, the occupied area of the outer periphery of the third semiconductor region on the main surface of the first semiconductor region. Since it is possible to reduce the size, it is possible to eliminate a useless area on the main surface of the semiconductor substrate and improve the degree of integration of the semiconductor integrated circuit device.

According to the above-mentioned means (5), the following operational effects can be obtained. (1) A first mask for forming a first semiconductor region is used in a first region of a main surface of the semiconductor substrate, and a third semiconductor region is formed (using a first mask for introducing a first impurity). Since the second impurity is introduced), the number of steps in the manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of forming the mask for forming the third semiconductor region. (2) Diffusing the third impurity introduced into the second region of the main surface of the semiconductor substrate to form the second semiconductor region, diffusing the second impurity introduced into the first region, Third
Since the semiconductor region is formed, the number of steps in the manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of diffusing the second impurity and forming the third semiconductor region. (3) A third semiconductor region formed on the main surface of the first semiconductor region of the first region of the main surface of the semiconductor substrate and a second semiconductor region of the second region
Since the semiconductor regions are formed in separate steps, the impurity concentrations of the third semiconductor region and the second semiconductor region can be independently controlled. (4) A first mask for forming a first semiconductor region is used in the first region of the main surface of the semiconductor substrate, and the third semiconductor region is formed (using the same first mask, the first semiconductor region , And each of the third semiconductor regions are formed)
The placement position of the third semiconductor region is formed in self alignment with respect to the placement position of the semiconductor region, and the placement position of the third semiconductor region with respect to the placement position of the first semiconductor region is a mask alignment margin dimension in a manufacturing process. It can be reduced by a corresponding amount.

According to the above-mentioned means (6), the following function and effect can be obtained in addition to the function and effect of the means (5). (1) diffusing the third impurity introduced into the second region of the main surface of the semiconductor substrate and forming the second semiconductor region, diffusing the first impurity introduced into the first region, First
Since the semiconductor region is formed and the second impurity introduced into the first region is diffused to form the third semiconductor region,
The number of steps in the manufacturing process of the semiconductor integrated circuit device can be reduced by an amount corresponding to the step of diffusing each of the first impurity and the second impurity to form each of the first semiconductor region and the third semiconductor region. (2) Since the diffusion rate of the second impurity is slower than the diffusion rate of the first impurity, the difference in the diffusion rate is used to make the second surface on the main surface of the first semiconductor region formed by the diffusion of the first impurity. A third semiconductor region formed by diffusion of impurities can be formed.

According to the above-mentioned means (7), the following operational effects can be obtained. (1) The shape of the corner portion of the surface of the channel formation region or the gate electrode of the MISFET generated when the semiconductor layer or the gate electrode layer corresponding to the lower layer is patterned is relaxed by the oxidation or nitridation of the surface. (2) As a result of the action and effect (1), electric field concentration can be reduced in the channel formation region in the lower layer of the MISFET or in the corner portion of the surface of the gate electrode, so that in the corner region of the gate insulating film of the MISFET. It is possible to prevent the breakdown voltage from deteriorating. (3) Further, as a result of the action and effect (1), the MISF
Since it is possible to prevent the deterioration of the film quality in the channel formation region of the lower layer of ET or in the corner portion of the surface of the gate electrode, it is possible to prevent the deterioration of the withstand voltage in the corner portion region of the gate insulating film of the MISFET.

According to the above-mentioned means (8), since the gate insulating film is newly formed in an independent process for the oxide film or the nitride film formed on the surface of the channel forming region or the gate electrode, the gate insulating film is formed. The controllability of the thickness of the insulating film can be improved.

According to the above-mentioned means (9), in the step of forming the gate insulating film, the oxide film or the nitride film on the surface of the channel forming region or the gate electrode formed in the previous step is not removed. The number of steps in the manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the removing step.

According to the above-mentioned means (10), in addition to the effect of the above-mentioned means (7), M generated when the semiconductor layer or the gate electrode layer corresponding to the lower layer is patterned.
The step shape on the side surface of the channel formation region or the gate electrode of the ISFET is relaxed by the sidewall spacer.

According to the above-mentioned means (11), the SR
MI for load of flip-flop circuit of AM memory cell
In the SFET, it is possible to prevent a short circuit between the gate electrode and the channel formation region (or the source region or the drain region), so that it is possible to prevent a standby current defect.

According to the above-mentioned means (12), the following operational effects can be obtained. (1) Volume of a silicon film based on cooling after high temperature annealing during the deposition of the silicon film in the above process or high temperature annealing performed after the deposition of the silicon film (both are annealing at a temperature higher than the melting point of aluminum) A crystal defect that occurs due to the contraction and that crosses the pn junction between the first semiconductor region and the second semiconductor region from the opening end of the insulating film can be captured in the third semiconductor region. (2) Since a mask for forming an opening in the insulating film and a mask for implanting impurities for forming the third semiconductor region in the above step can both be used, the mask forming step can be reduced by the amount corresponding to the mask for implanting impurities. The number of steps in the manufacturing process of the semiconductor integrated circuit device can be reduced.

According to the above-mentioned means (13), the following operational effects can be obtained. (1) After the silicon film is deposited on the entire surface of the insulating film in the above process, and before the silicon film of the process is subjected to patterning, this silicon film is annealed at a high temperature for the purpose of crystallization. Since stress due to volume contraction during cooling can be dispersed in the entire silicon film and concentration of the stress generated at the opening end formed in the insulating film on the main surface of the second semiconductor region can be reduced. The volume shrinkage of the silicon film can prevent a crystal defect from crossing the pn junction between the first semiconductor region and the second semiconductor region from the opening end of the insulating film. (2) The step of performing the high temperature annealing for crystallizing the silicon film in the step, which has been performed after the patterning of the silicon film in the step, is performed after the silicon film in the step is deposited. Since the silicon film is simply replaced before the patterning step, it is possible to prevent an increase in the number of steps in the manufacturing process of the semiconductor integrated circuit device.

According to the above-mentioned means (14), the following operational effects can be obtained. (1) Since the leak current of the power supply supplied to the information storage node of the memory cell of the SRAM can be reduced, the SRAM
Power consumption of the standby current can be reduced. (2) Since the leak current of the power supply supplied to the information storage node of the memory cell of the SRAM can be reduced, the information retention characteristic of the memory cell can be improved. (3) In the SRAM described in the means (12), a third semiconductor region is added to the drain region of the driving MISFET of the memory cell, and an electrode on the surface of the drain region corresponding to the third semiconductor region. Since the impurity concentration of the region connected to the can be increased, the impurity concentration of the impurity that reduces the resistance value introduced into the electrode (silicon film) can be reduced (the impurity concentration required for ohmic connection is the third
It is ensured in the semiconductor region), and the seeping of impurities from the electrode to the drain region can be reduced.

According to the above-mentioned means (15), the maximum stress generated at the open end of the side wall spacer due to the volume change of the gate electrode (due to the difference in the coefficient of thermal expansion with the side wall spacer) is reduced. Regions in which damages due to implantation of the second conductivity type impurities forming the source region and the drain region are generated with respect to the concentrated regions can be shifted by an amount corresponding to the film thickness of the mask (maximum stress concentration). Region and damage-causing region), crystal defects occurring in the main surface of the first semiconductor region, the source region or the drain region in the open end region of the sidewall spacer, or the first region.
It is possible to prevent crystal defects that occur across the pn junction between the semiconductor region and the source or drain region.

The present invention will be described below in terms of the constitution of the present invention.
A description will be given with an embodiment applied to a RAM.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0075]

(Embodiment 1) FIG. 1 (chip layout diagram) shows an overall schematic configuration of a high-speed SRAM which is Embodiment 1 of the present invention.

The SRAM (semiconductor pellet) shown in FIG. 1 has a large capacity of 4 [Mbit]. This SRAM is
Although not shown, a DIP structure, an SOP structure, or the like is encapsulated in a resin-encapsulated semiconductor device that employs a dual in-line method in which a plurality of leads are arranged on each of two opposing sides of the encapsulation body. The SRAM has a rectangular planar shape. The SRAM of this embodiment has a rectangular long side (in FIG. 1,
The upper and lower sides are 17.41 mm and the short sides (Fig. 1)
Each of the middle, right side, and left side) is 7.55 mm.

The central area of the circuit system mounting surface of the SRAM, specifically, the central area of two long sides of a rectangular shape facing each other, from the left short side to the right short side (hereinafter, X In addition, a plurality of external terminals (bonding pads) BP are arranged, in which the direction from the upper long side to the lower long side is called the Y direction. This external terminal BP
Is electrically connected to the inner lead of the above-mentioned lead. For example, an address signal, a chip select signal, an output enable signal, a write enable signal, and an input / output data signal are applied to each of the plurality of external terminals BP. Further, the power supply voltage Vcc and the reference voltage Vss are applied to the external terminal BP (SRAM
Power is supplied from outside). The power supply voltage Vcc is, for example, the operating voltage of the circuit 5 [V], and the reference voltage Vss is, for example, the ground voltage 0 [V] of the circuit.

A power supply voltage conversion circuit (step-down power supply circuit or regulator) VRC is mounted on the SRAM. The power supply voltage conversion circuit VRC steps down the power supply voltage Vcc (5 [V]) supplied from the outside of the SRAM inside the SRAM, and drops it to a part of the peripheral circuit of the SRAM mainly for the purpose of low power consumption. The step-down power supply voltage Vdd is supplied. As the power supply voltage Vdd, 4 [V] is used in the SRAM of this embodiment. Two power supply voltage conversion circuits VRC are mounted on the circuit system mounting surface of the SRAM, and the central region of the short side on the left side,
At a position close to each of the central regions on the right short side,
Each is arranged.

A part of an indirect peripheral circuit of peripheral circuits such as an address buffer circuit and a predecoder circuit is provided in each of the upper and lower regions of the external terminals BP arranged on the circuit system mounting surface of the SRAM. RCs are arranged respectively.
As shown in FIG. 2B (block circuit diagram showing the power supply system), the indirect peripheral circuit RC is supplied with the step-down power supply voltage Vdd stepped down by the power supply voltage conversion circuit VRC. Peripheral circuits including indirect peripheral circuits other than the indirect peripheral circuit RC and direct peripheral circuits, specifically, decoder circuits (X decoder circuit XDEC, Y decoder circuit YDEC), control circuit CC, sense amplifier circuit SA, output buffer circuit,
Each of the memory cell arrays is basically supplied with a power supply voltage Vcc from the outside. That is, in FIG. 1, the SRAM has the power supply voltage conversion circuit VRC in a circuit arranged in a region surrounded by the virtually drawn dashed line surrounding the external terminal BP, the power supply voltage conversion circuit VRC, and the indirect peripheral circuit RC. The stepped down power supply voltage Vdd is supplied.

In FIG. 1, two memory blocks MB1 and MB2 are arranged between the rectangular long upper side and the indirect peripheral circuit RC on the circuit system mounting surface of the SRAM. Similarly, 2 is provided between the lower long side and the indirect peripheral circuit RC.
Memory blocks MB3 and MB4 are arranged. That is, a total of four memory blocks MB are arranged in the SRAM. Each of the memory blocks MB1 and MB3 is sequentially arranged in the Y direction along the short side on the left side of the rectangular shape, and each of the memory blocks MB2 and MB4 is sequentially arranged in the Y direction along the short side of the right side of the rectangular shape. ..

On the circuit system mounting surface of the SRAM, a Y switch circuit Y-SW, a Y decoder circuit YDEC, and a sense amplifier circuit SA are arranged between the memory blocks MB1 and MB2 and the indirect peripheral circuit RC. Similarly, Y switch circuits Y-SW and Y are provided between the memory blocks MB3 and MB4 and the indirect peripheral circuit RC.
A decoder circuit YDEC and a sense amplifier circuit SA are arranged.

The four memory blocks MB1 to MB4
1 is divided into eight memory mats MM arranged in the X direction, respectively, as shown in FIG. That is, SRA
Since M has four memory blocks MB divided into eight memory mats MM, M is divided into a total of 32 memory mats MM. The four memory blocks MB
In each of 1 to MB4, one X decoder circuit XDEC is arranged between four memory mats MM on the left side and four memory mats MM on the right side arranged in the X direction.

In addition, the memory blocks MB1 and MB2
Between the memory blocks MB3 and MB4, a redundant data line (Y-based redundant circuit) SDB is arranged. Since one redundant data line SDB is provided with four redundant input / output data lines, and four redundant data lines are connected to each redundant input / output data line, a total of 16 redundant data lines are provided. Will be placed. In addition, the memory blocks MB1 to MB1
A redundant word line (X system redundant circuit) SWB is arranged on the side of each Y switch circuit Y-SW and Y decoder circuit YDEC of MB4. In the redundant word line SWB, four redundant sub word lines are arranged for each memory block MB.

The four memory blocks MB1 to MB4
Among them, each of the memory mats MM divided into eight of the one memory block MB has four memories arranged in the X direction as shown in FIG. 2A (enlarged block diagram of a main part). It is composed of a cell array MAY. Each of the four memory cell arrays MAY is arranged in the X direction in the memory mat MM. That is, in the SRAM, each of the four memory blocks MB1 to MB4 is divided into eight memory mats MM, and each of the eight memory mats MM is composed of four memory cell arrays MAY. 128 memory cell arrays MAY are arranged.

Of the 128 memory cell arrays MAY, one memory cell array MAY is further divided into four sub memory cell arrays SMEY, as shown in FIG. 3 (enlarged block diagram of the main part). The sub memory cell arrays SMEY divided into four are arranged in the X direction. The sub memory cell array SMEY is composed of 16 memory cells MC arranged in the X direction (word line extending direction). That is, one memory cell array MAY
Has four sub-memory cell arrays SMEY in which 16 memory cells MC are arranged in the X-direction, a total of 64
(64 [bit]) memory cells MC are arranged. Further, in one memory cell array MAY, 514 (514 [bit]) memory cells MC are arranged in the Y direction (complementary data line extending direction). Of the 514 memory cells MC arranged in the Y direction, 512 (512 [bit]) are configured as regular (actually storing information) memory cells MC, and the remaining two (2 [bit]) Are configured as redundant memory cells MC (redundant word lines SWB).

As shown in FIG. 2 (A) and FIG. 3, 1
A word driver circuit WDR is arranged between the two memory cell arrays MAY on the left side and the two memory cell arrays MAY on the right side of each memory mat MM. FIG. 1
The eight word driver circuits WDR of each of the eight memory mats MM of the one memory block MB of the SRAM shown in FIG. 4 include four memory mats MM on the left side and four memory mats on the right side in the X direction. It is selected by the X decoder circuit XDEC arranged between the MM and the MM. That is,
In one memory block MB, one X decoder circuit XDEC selects one out of a total of eight word driver circuits WDR of eight memory mats MM.

As shown in FIG. 3, the word driver circuit WDR is selected by the X decoder circuit XDEC via the main word line MWL. The word driver circuit WDR is selected by the address signal line AL arranged for each word driver circuit WDR. The main word line MWL extends in the X direction on the memory cell array MAY, and a plurality of main word lines MWL are arranged in the Y direction for every four (4 [bit]) memory cells MC. The address signal lines AL extend in the Y direction and are arranged in the X direction. The address signal line AL is arranged on the right side of the word driver circuit WDR in the memory mat MM.
8 to select the memory cells MC of the memory cell array MAY, and 8 to select the memory cells MC of the two memory cell arrays MAY arranged on the left side.
A total of 16 books will be arranged.

As shown in FIGS. 2A and 3, in the memory mat MM, the word driver circuit WDR
Selects the first word line WL1 and the second word line WL2 extending over one of the four memory cell arrays MAY. First word line WL1
The second word line WL2 is arranged for each memory cell array MAY (for each four sub memory cell arrays SMEY). The first word line WL1 and the second word line WL2 are separated from each other and extend substantially parallel to each other in the X direction.
The first word line WL1 and the second word line WL2 are arranged for each one memory cell MC arranged in the Y direction.
That is, the two first word lines WL1 and the second word lines WL to which the same selection signal is applied to one memory cell MC.
2 are connected.

Of the two memory cell arrays MAY arranged on the right side of the word driver circuit WDR shown in FIGS. 2A and 3 respectively, the word driver circuit WDR
The first word line WL1 and the second word line WL2 extending in the memory cell array MAY on the side closer to are selected by the word driver circuit WDR via the second sub-word line SWL2. The first word line WL1 and the second word line WL2 extending in the memory cell array MAY far away from the word driver circuit WDR are selected by the word driver circuit WDR via the first sub-word line SWL1. The first sub-word line SWL1 and the second sub-word line SWL2 are separated from each other and extend in parallel in the X direction. The first sub-word line SWL1 and the second sub-word line SWL2 are arranged for each one memory cell MC arranged in the Y direction, like the first word line WL1 and the second word line WL2. The first sub-word line SWL1 has one memory cell array M on the side closer to the word driver circuit WDR.
Another memory cell array MA that extends over AY and is far away
First word line WL1 and second word line W arranged in Y
Connect between L2 and the word driver circuit WDR.

In each of the two memory cell arrays MAY arranged on the left side of the word driver circuit WDR, the first word line WL1 and the second word line WL2 are arranged similarly to the right side. The first word line WL1 and the second word line W
L2 is connected to the word driver circuit WDR via the first sub-word line SWL1 or the second sub-word line SWL2.

As shown in FIG. 2 (A), in the memory mat MM, the load circuits LOAD divided respectively are arranged above the four memory cell arrays MAY. Below each of the four memory cell arrays MAY, Y decoder circuits YDEC and Y are divided respectively.
A switch circuit Y-SW is arranged. Further, a sense amplifier circuit SA divided for each of the four memory cell arrays MAY is arranged below each memory cell array MAY. Four sense amplifier circuits SA are arranged for one memory cell array MAY, and 4 [bit] information (four memory cells M
The information stored in C) can be output at one time. A control circuit CC is provided below the word driver circuit WDR.
Are placed. In addition, the memory mat M shown in FIG.
In M, between the two memory cell arrays MAY arranged on the left side and the right side of the word driver circuit WDR, as shown in FIGS. A connecting cell including a connecting connection between the cell arrays MAY is arranged.

As shown in FIGS. 2A and 3, the complementary data lines DL are arranged in the memory cell array MAY in the memory mat MM. Complementary data line DL
Is the main word line MWL, the sub word line SWL,
Crosses the respective extending directions of the word lines WL (substantially orthogonal)
It extends in the Y direction. The complementary data line DL is composed of two data lines, a first data line DL1 and a second data line DL2, which are spaced apart from each other and extend in parallel in the Y direction. As shown in FIG. 3, the complementary data line DL is arranged for each memory cell MC arranged in the X direction. Complementary data line DL
One end side of the upper side of the load circuit LOAD shown in FIG.
Connected to. The other end side below the complementary data line DL is Y
It is connected to the sense amplifier circuit SA via the switch circuit Y-SW.

Peripheral circuits including direct peripheral circuits and indirect peripheral circuits mounted on the circuit system mounting surface of the SRAM,
Each of the memory cells MC arranged in the sub memory cell array SMEY is basically composed of a complementary MISFET. A specific cross-sectional structure of the SRAM will be described later (see FIG. 6,
10 and 11), the SRAM mainly comprises a p-type semiconductor substrate (Psub) 1 made of single crystal silicon.
In this embodiment, the main surface of the SRAM, which is the circuit system mounting surface of the p--type semiconductor substrate 1, is set to the (100) crystal plane (including crystallographically equivalent crystal planes). Also,
In the p − type semiconductor substrate 1, the plane orientation of the (100) crystal plane of the principal plane is 2.5 degrees in a predetermined plane orientation, for example, a [010] plane orientation (including a crystallographically equivalent plane orientation). It is formed of a so-called off-angle wafer inclined at 15 degrees or less. In the SRAM of this embodiment, the p-type semiconductor substrate 1 is formed from a 4 ° off-angle wafer.

As shown in FIG. 3 and FIG. 4 by enclosing the reference numeral 3i in a broken line, in the region where the memory cell array MAY is arranged, n − is formed on the main surface portion of the p − type semiconductor substrate 1.
A type well isolation region (Niso) 3i is arranged. The cross sectional structure of the n-type well isolation region 3i will be described later with reference to FIGS. 6 and 10, but the α-ray shows the p-type semiconductor substrate 1
The main purpose is to prevent the so-called undershoot (improve the α-ray soft error resistance), which prevents the minority carriers generated when entering the inside from entering the area of the memory cell array MAY.

A p--type well region (Pwell) 2M in which the memory cell array MAY is arranged is arranged on the main surface of the n--type well isolation region 3i. An area other than the memory cell array MAY, specifically, an area in which peripheral circuits including indirect peripheral circuits and direct peripheral circuits are arranged, that is, n-
A p--type well region (Pwell) 2 and an n--type well region (Nwell) 3 are arranged in different regions of the main surface of the p--type semiconductor substrate 1 around the outer periphery of the type well isolation region 3i. An n-channel MISFET forming a peripheral circuit is mainly arranged on the main surface of the p-type well region 2.
A p-channel MISFET forming a peripheral circuit is mainly arranged on the main surface of the n-type well region 3. That is, in the SRAM of this embodiment, the n-type well isolation region 3i is formed on the main surface of the p- type semiconductor substrate 1, and the p- type well region 2M is formed on the main surface of the n- type well isolation region 3i. The double well structure (or the triple well structure including the n-type well region 3) is adopted. In addition, the SRAM of this embodiment has p
A p-type well region 2 and an n-type well region 3 are arranged on the main surface of the --type semiconductor substrate 1 to form a so-called twin well structure.

As shown in FIGS. 3 and 4, the SR
In the memory mat MM of AM, two memory cell arrays M arranged on the left side of the word driver circuit WDR.
AY is arranged on the main surface of one p @-type well region 2M arranged on the main surface of one n @-type well isolation region 3i.
In the outer periphery of the memory cell array MAY (in this case, a region in which the memory cells MC are substantially arranged) is provided, and p
A guard ring region P-GR formed in a plane ring shape is arranged along the contour of the p-type well region 2M in the peripheral region of the -type well region 2M. The guard ring region P-GR supplies a fixed reference voltage Vss to the p-type well region 2M.

Between the two memory cell arrays MAY arranged on the left side of the word driver circuit WDR, a well contact region PWC1 is arranged on the main surface of the p--type well region 2M. The well contact regions PWC1 are arranged in the Y direction at a rate of one for each of the plurality of memory cells MC (for example, one for each of the two memory cells MC), and are arranged in plurality.

Similarly, in the memory mat MM,
The two memory cell arrays MAY arranged on the right side of the word driver circuit WDR are arranged on the main surface of one p--type well region 2M arranged on the main surface of one n--type well isolation region 3i. .. A guard ring region P-GR is arranged in the peripheral region of the p-type well region 2M, and a fixed reference voltage Vss is supplied. Word driver circuit WDR
Between each of the two memory cell arrays MAY arranged on the right side of, the well contact region PWC1 is arranged on the main surface of the p-type well region 2M.

Further, as shown in FIGS. 3 and 4, in the memory cell array MAY, a well contact region PWC2 is arranged between each of the four sub memory cell arrays SMEY. Similar to the well contact region PWC1 described above, the well contact region PWC2 has a ratio of one for each of the plurality of memory cells MC in the Y direction (for example, one for every two memory cells MC). Arranged and arranged in plural.

A well contact region PWC1 arranged between the memory cell array MAY and a well contact region PWC arranged between the sub memory cell arrays SMAY.
2 is a reference voltage V fixed to the p-type well region 2M.
It is arranged for the purpose of supplying ss and stabilizing the potential of the p-type well region 2M.

As shown in FIG. 4, a plurality of p--type well regions 2 and a plurality of n--type well regions 3 are alternately arranged in the X direction in a region of the memory mat MM where the word driver circuits WDR are arranged. It A guard ring region P-GR is arranged in the peripheral region of the p- type well region 2 in which the word driver circuit WDR is arranged, and a guard ring region N-GR is arranged in the peripheral region of the n- type well region 3. It

One memory cell MC arranged in the sub memory cell array SMEY of the memory cell array MAY shown in FIG. 3 has a word line WL and a complementary data line as shown in FIG. 5 (circuit diagram of the memory cell). It is arranged at each intersection with DL. That is, the memory cell MC has the first word line W
It is arranged at the intersection of L1 and the second word line WL2 and the first data line DL1 and the second data line DL2. The memory cell MC includes a flip-flop circuit and two transfer MISFs.
ETQt1 and Qt2. The flip-flop circuit is configured as an information storage unit, and this memory cell M
C stores 1 [bit] of information "1" or "0".

Two transfer MISs of the memory cell MC
Each of the FETs Qt1 and Qt2 connects one semiconductor region to each of the pair of input / output terminals of the flip-flop circuit. The other semiconductor region of the transfer MISFET Qt1 is connected to the first data line DL1 and the gate electrode is connected to the first word line WL1. The other semiconductor region of the transfer MISFET Qt2 is connected to the second data line DL2, and the gate electrode is connected to the second word line WL2. Each of the two transfer MISFEETs Qt1 and Qt2 is an n-channel type.

The flip-flop circuit includes two drive MISFETs Qd1 and Qd2 and two load MISFETs.
ETQp1 and Qp2. MISF for drive
Each of ETQd1 and Qd2 is an n-channel type. Each of the load MISFETs Qp1 and Qp2 is a p-channel type. That is, the memory cell MC of the SRAM of this embodiment is a completely complementary MISFET (so-called full CM).
OS) structure.

The driving MISFET Qd1 and the load M
Each of the ISFETs Qp1 connects their drain regions and their gate electrodes to each other, and has a complementary MISFE
Configure T. Similarly, the drive MISFET Qd2 and the load MISFET Qp2 are connected to each other's drain regions and to each other's gate electrodes.
Configure SFET. The drain regions (input / output terminals) of the drive MISFET Qd1 and the load MISFET Qp1 are connected to one semiconductor region of the transfer MISFET Qt1 and also to the gate electrodes of the drive MISFET Qd2 and the load MISFET Qp2. Drive MISFETQd2, load MISFETQ
The drain regions (input / output terminals) of p2 are M for transfer.
It is connected to one semiconductor region of the ISFET Qt2, and also has a driving MISFET Qd1 and a load MISFET.
It is connected to each gate electrode of Qp1. MIS for drive
The source region of each of the FETs Qd1 and Qd2 is the reference voltage V
It is connected to ss (for example, 0 [V]). MISFE for load
The source regions of TQp1 and Qp2 are the power supply voltage Vcc.
(For example, 5 [V]).

A capacitive element C is formed between a pair of input / output terminals of the flip-flop circuit of the memory cell MC, that is, between two information storage nodes. The capacitor C has one electrode connected to one information storage node and the other electrode connected to the other information storage node. The capacitive element C is basically configured for the purpose of increasing the charge storage amount of the information storage node and enhancing the α-ray soft error resistance. Further, since each electrode of the capacitive element C is connected between the two information storage nodes, the capacity of the capacitive element C is about half that of the case where two capacitive elements are independently formed in each of the two information storage nodes. It can be composed of plane products. That is, since the capacitive element C can reduce the area occupied by the memory cell MC, the integration degree of the SRAM can be improved.

The SRAM having the above-mentioned structure is as follows.
As shown in FIG. 1, FIG. 2A, and FIG. 3, one of a plurality of X decoder circuits XDEC arranged in the Y direction.
The main word line MWL is selected and one of the word driver circuits WDR arranged in the memory mats MM of the memory block MB is selected. By selecting each of the main word line MWL and the word driver circuit WDR, four sets of sub word lines SWL extending to the right side of the word driver circuit WDR of one memory mat MM and four sets of sub word lines extending to the left side SWL is selected. Then, based on the address signal (Y-system address signal) to the selected word driver circuit WDR, one of the four subword lines SWL on either the right side or the left side of the word driver circuit WDR is selected. SWL is selected, two first word lines WL connected to this sub word line SWL and extending one sub memory cell array SMEY
The first and second word lines WL2 are selected. That is, SR
The AM divides the first word line WL1 and the second word line WL2 into a plurality of pieces in the extending direction, and a set of the first word line WL1 and the second word line WL among the plurality of pieces.
2 is a word driver circuit WDR and an X decoder circuit X
The divided word line method selected by DEC is adopted. By adopting the divided word line method, the flow rate of charge / discharge of the selected word line WL can be reduced, so that the power consumption of the SRAM can be reduced.

As shown in FIGS. 2A and 3, the SRAM has a first memory cell array MAY extending from one of the two memory cell arrays MAY arranged at one end of the word driver circuit WDR. The word line WL1 and the second word line WL2 are connected to the word driver circuit WDR via the second sub-word line SWL2, and the other memory cell array M
First word line WL1 and second word line W extending AY
L2 is connected to the word driver circuit WDR via the first sub-word line SWL1. That is, the SRAM has word lines WL divided into memory cell arrays MAY.
Also, a double word line system is adopted in which sub word lines SWL connecting between the plurality of divided word lines WL are arranged. The adoption of the double word line system corresponds to the sub word line SWL, and the word driver circuit WD
Since the resistance value between R and the word line WL can be reduced, the charge / discharge speed of the selected word line WL can be increased and the circuit operation speed of the SRAM can be increased.

The X decoder circuit XDEC, the Y decoder circuit YDEC, the Y switch circuit Y-SW, the sense amplifier circuit SA, the load circuit LOAD, etc. arranged in the peripheral region of the memory cell array MAY of the SRAM constitute a peripheral circuit of the SRAM. .. This peripheral circuit directly or indirectly controls the information writing operation, information holding operation, information reading operation, etc. of the memory cell MC.

Next, the specific structure of the memory cell MC and the memory cell array MAY of the SRAM will be described. The planar structure of the memory cell MC in the completed state is shown in FIG. 7 (plan view), and the planar structure shown for each manufacturing step in the manufacturing process is shown in FIG. 8 (A) and FIG. 8 (B) (plan view), respectively. The sectional structure of the completed state of the memory cell MC is shown in FIG. 6 (a sectional view taken along the line II of FIG. 7).

As shown in FIGS. 6 and 7, the SRAM is mainly composed of the p--type semiconductor substrate 1 made of single crystal silicon as described above. An n--type well isolation region 3i is formed on the main surface of the memory cell array MAY region of the p--type semiconductor substrate 1, and a p--type well region 2M is formed on the main surface of the n--type well isolation region 3i. To be done. In regions other than the region of the memory cell array MAY, as described above, the p − type well region 2 and the n − type well region 3 are formed on the main surface of the p − type semiconductor substrate 1.

FIG. 13 (impurity concentration distribution chart of the substrate and the well region) shows the p--type semiconductor substrate 1, the n--type well isolation region 3i, the p--type well region 2M, the p--type well region 2,
The respective impurity concentrations of the n-type well region 3 are shown. The horizontal axis shown in FIG. 13 represents the depth [μm] from the main surface of the p − type semiconductor substrate 1, and the vertical axis represents the impurity concentration [atoms / cm ³ ].

As shown in FIG. 13, p--type semiconductor substrate 1
Is formed with an impurity concentration of about 1 × 10 ¹⁵ [atoms / cm ³ ] and is set to a resistance value of 6 to 12 [Ωcm].

The n--type well isolation region 3i is higher than the impurity concentration of the p--type semiconductor substrate 1 and lower than the impurity concentration of the n--type well region 3, for example, 10 ¹⁵ -1.
The impurity concentration is set to about 0 ¹⁶ [atoms / cm ³ ]. The depth of the pn junction between the n--type well isolation region 3i and the p--type semiconductor substrate 1, that is, the n--type well isolation region 3
The junction depth (xj) of i is set to about 4 to 5 [μm].

P of the main surface of the n--type well isolation region 3i
The -type well region 2M is higher than the impurity concentration of the p-type semiconductor substrate 1, for example, 10 ¹⁶ to 10 ¹⁷ [atoms / cm ³ ].
The impurity concentration on the surface is set to some extent. The junction depth of the p--type well region 2M is the n--type well isolation region because the diffusion of the p-type impurity in the p--type well region 2M is suppressed by the presence of the n-type impurity in the n--type well isolation region 3i. It is shallower than the junction depth of 3i or the diffusion depth of the p-type well region 2, and is set to about 2 [μm], for example. Also, p-
Since the type well region 2M is formed on the main surface of the n--type well isolation region 3i, the impurity concentration on the surface of the p--type well region 2M decreases due to the presence of the n-type impurity in the n--type well isolation region 3i. , P--type well region 2 as shown in FIG.
The impurity concentration on the surface of M is set to be equal to (or higher than) the impurity concentration on the surface of the p--type well region 2 arranged around the outer periphery of the n--type well isolation region 3i.

The n-type well region 3 around the outer periphery of the n-type well isolation region 3i has a surface higher than the impurity concentration of the n-type well isolation region 3i, for example, about 10 ¹⁷ [atoms / cm ³ ]. The impurity concentration of is set. The junction depth of the n-type well region 3 is set to the same depth as the junction depth of the n-type well isolation region 3i.

The p-type well region 2 around the n-type well isolation region 3i is higher than the impurity concentration of the p-type semiconductor substrate 1 and the surface of the p-type well region 2M. The surface impurity concentration is set to be equal to the impurity concentration. The diffusion depth of the p-type well region 2 is regulated by the diffusion rate of the p-type semiconductor substrate 1 having the same conductivity type (diffused into a region where n-type impurities do not exist).
The depth is set deeper than the diffusion depth of the -type well region 2M, for example, about 4 to 5 [μm].

6, 7, and 8 are formed on the main surface of the inactive region of the p--type well region 2M (on the main surface of the n--type well isolation region 3i) in which the memory cell array MAY is arranged.
As shown in (A), an element isolation insulating film (field silicon oxide film) 4 is formed. A p-type channel stopper region 5 is formed under the main surface portion of the inactive region of the p-type well region 2M, that is, below the element isolation insulating film 4. Similarly,
An element isolation insulating film 4 and a p-type channel stopper region 5 are formed on the main surface of the inactive region of the p-type well region 2 around the n-type well isolation region 3i (see FIG. 11). An element isolation insulating film 4 is formed on the main surface of the inactive region of the n-type well region 3. Compared to the p-type well regions 2 and 2M, the inversion region is less likely to occur in the main surface portion of the inactive region of the n-type well region 3 and element isolation can be reliably performed, thus reducing the number of steps in the manufacturing process. For this purpose, basically no n-type channel stopper region is provided.

One memory cell MC of the SRAM is p
-Configured on the main surface of the active region of the well region 2M. The active region is formed in a defined region surrounded by the element isolation insulating film 4 (particularly the end portion of the element isolation insulating film 4) and the p-type channel stopper region 5. Of the memory cells MC,
Each of the two driving MISFETs Qd1 and Qd2 has p in the region defined by the element isolation insulating film 4 as shown in FIGS. 6, 7, 8A and 8B.
-Configured on the main surface of the well region 2M. MIS for drive
Each of the FETs Qd1 and Qd2 mainly includes the p-type well region 2M, the gate insulating film 6, the gate electrode 7, the source region and the drain region.

The gate length (Lg) directions of the driving MISFETs Qd1 and Qd2 are set to be substantially parallel to each other, and the gate length directions thereof are the X direction (or the word line WL).
(Extending direction) of. The element isolation insulating film 4 (and the p-type channel stopper region 5) is mainly formed in the driving MIS.
The FETs Qd1 and Qd2 are arranged at positions that define the respective gate widths (Lw).

The p--type well region 2M is a driving MIS.
Each of the FETs Qd1 and Qd2 constitutes a channel forming region.

The gate electrode 7 is p- in the active region.
The gate insulating film 6 is formed on the channel forming region of the mold well region 2M. One end side of the gate electrode 7 protrudes in the Y direction on the element isolation insulating film 4 by at least the amount corresponding to the mask alignment margin dimension in the manufacturing process. The other end of the gate electrode 7 of the driving MISFET Qd1 extends in the Y direction through the element isolation insulating film 4 and onto the drain region of the driving MISFET Qd2. Similarly, drive MI
One end side of the gate electrode 7 of the SFET Qd2 projects on the element isolation insulating film 4, and the other end side extends in the Y direction through the element isolation insulating film 4 and onto the drain region of the driving MISFET Qd1.

The gate electrode 7 is formed in the first-layer gate material forming step, and is formed of, for example, a polycrystalline silicon film having a single layer structure. An n-type impurity such as P (or As) that reduces the resistance value is introduced into this polycrystalline silicon film. Since the thickness of the gate electrode 7 having a single-layer structure can be reduced, the surface of the interlayer insulating film serving as the base of the upper conductive layer can be flattened.

Each of the source region and the drain region is composed of an n type semiconductor region 10 having a low impurity concentration and an n + type semiconductor region 11 having a high impurity concentration provided on the main surface thereof. The two types of n-type semiconductor regions 10 and n + -type semiconductor regions 11 having different impurity concentrations are formed on the side of the gate electrode 7 in the gate length direction.
(To be precise, as will be described later, the gate electrode 7, the side wall spacers 9 and the mask 9T covering the side wall spacers 9 are formed in self alignment. That is, each of the source region and the drain region of the driving MISFETs Qd1 and Qd2 has a so-called DDD structure. Each of the source region and the drain region of this DDD structure is formed in a region surrounded by a dashed line indicated by DDD in FIG. 8A on the main surface of the active region of the p-type well region 2M. It

Each of the source region and the drain region is n
The type semiconductor region 10 is formed of P which is an n-type impurity, for example. The n + type semiconductor region 11 is formed of As, which is an n type impurity having a slower diffusion rate than P. In the manufacturing process, when two types of n-type impurities are introduced in the same manufacturing process using the same mask, the n-type semiconductor region 10,
The difference in diffusion distance between the n + type semiconductor regions 11 is governed by the difference in diffusion rate between the two types of n type impurities. In each of the driving MISFETs Qd1 and Qd2 adopting the DDD structure, the substantial dimension in the gate length direction of the n-type semiconductor region 10 between the n + -type semiconductor region 11 and the channel forming region is the same as that of the n-type semiconductor region 10. This corresponds to the dimension obtained by subtracting the diffusion distance of the n + type semiconductor region 11 from the diffusion distance. The n-type semiconductor region 10 has a substantial dimension in the gate length direction smaller than the dimension in the gate length direction of an n-type semiconductor region (17) having a low impurity concentration in the LDD structure, which will be described later, and further has a low LDD structure impurity. Concentration n-type semiconductor region (17)
The impurity concentration is higher than that of. In other words, drive MISFE
In each of TQd1 and Qd2, in the current path between the source region and the drain region, the parasitic resistance added to the n-type semiconductor region 10 is smaller than that of the n-type semiconductor region (17) of the LDD structure, so that the LDD structure described later is used. The drive capability can be made higher than that of each of the transfer MISFETs Qt1 and Qt2 adopting the.

Sidewall spacers 9 are formed on the side walls of the gate electrode 7 in the gate length direction. The sidewall spacer 9 is formed in self-alignment with the gate electrode 7, and is formed of, for example, an insulating film such as a silicon oxide film.

The conductive layer (1 above the gate electrode 7)
An insulating film is formed in the region where 3) is arranged, although no reference numeral is attached. This insulating film is formed mainly for the purpose of electrically separating the lower gate electrode 7 and the upper conductive layer (13) and preventing the surface of the gate electrode 7 from being oxidized. For example, a silicon oxide film. Is formed by.

The memory cell MC is shown in FIGS.
(In the case of generically including (A) and (B), only the drawing number is shown. The same applies to the following.) A region in which the planar shape surrounded by a chain double-dashed line is defined by a rectangular shape Placed inside. MISF for driving one side of the memory cell MC
The plane shape of ETQd1 is the center point CP of the memory cell MC.
Driving MISFE for (intersection of rectangular diagonal lines)
It is configured by point symmetry of the plane shape of TQd2. The center point CP is a point that is virtually drawn for convenience of description, and is not a point that is actually formed as a pattern in the memory cell MC of the SRAM.

As shown in FIGS. 7 and 8, in the memory cell array MAY or the sub memory cell array SMAY, the driving MISFETs Qd1 and Qd of the memory cell MC.
Each of the two planar shapes of the second memory cell MC is different from the other memory cell MC with respect to the X1-X3 axis or the X2-X4 axis with another memory cell MC adjacent in the X direction that coincides with the gate length direction of the driving MISFET Qd. Driving MISFET Qd
1 and Qd2 are formed in line symmetry with respect to their planar shapes. Similarly, the driving MISFETs Qd1 and Qd of the memory cell MC are
The plane shape of each d2 is the driving MISFET Qd.
MISFETQd for driving the other memory cell MC with respect to the X1-X2 axis or the X3-X4 axis between the memory cell MC and another memory cell MC adjacent in the Y direction that coincides with the gate width direction of the other memory cell MC.
1 and Qd2 are formed in line symmetry with respect to their planar shapes. That is, the driving MISFET Qd of the memory cell MC is formed in a line-symmetrical shape for each memory cell MC in the arrangement of the memory cells MC in the X direction and the Y direction.

Of the driving MISFETs Qd of the memory cells MC arranged in the X direction, the mutually facing source regions of the driving MISFETs Qd of the adjacent memory cells MC are integrally formed (see FIG. 9B). ). That is, the driving MISFE of one of the adjacent memory cells MCs
M for driving the other memory cell MC in the source region of TQd
The source region of the ISFET Qd is configured to drive MISF
The area occupied by the source region of ETQd is reduced. Also, the source region of the driving MISFET Qd of one memory cell MC and the driving region M of the other memory cell MC facing the source region.
Since the element isolation insulating film 4 (and the p-type channel stopper region 5) is not interposed between the source region of the ISFET Qd and the memory cell M corresponding to the element isolation insulating film 4.
The area occupied by C can be reduced.

Two transfer MISs of the memory cell MC
As shown in FIGS. 6, 7 and 8, each of the FETs Qt1 and Qt2 is formed on the main surface of the p − type well region 2M in the region defined by the element isolation insulating film 4. Each of the transfer MISFETs Qt1 and Qt2 is mainly composed mainly of the p--type well region 2M, the gate insulating film 12, the gate electrode 13, the source region and the drain region.

The respective gate length (Lg) directions of the transfer MISFETs Qt1 and Qt2 are set substantially parallel to each other, and the respective gate length directions are set in the Y direction (or the extending direction of the complementary data line DL). Match. That is, the transfer MI
The gate length direction of each of the SFETs Qt1 and Qt2 and the gate length direction of the driving MISFETs Qd1 and Qd2 intersect at a substantially right angle. The element isolation insulating film 4 (and the p-type channel stopper region 5) is mainly formed by the transfer MISFET Qt.
The gate widths (Lw) of 1 and Qt2 are defined.

The p--type well region 2M is a transfer MIS.
The respective channel forming regions of the FETs Qt1 and Qt2 are formed.

The gate electrode 13 is p in the active region.
The gate insulating film 12 is formed on the channel forming region of the -type well region 2M. The gate electrode 13 is formed in the second layer gate material forming step, and for example, the polycrystalline silicon film 13A, the polycrystalline silicon film 13B, and the refractory metal silicide film 13 are formed.
Each of the Cs is sequentially laminated to form a three-layer laminated structure (so-called polycide structure). An n-type impurity such as P (or As) that reduces the resistance value is introduced into the lower polycrystalline silicon film 13A. An n-type impurity such as P (or As) that reduces the resistance value is introduced into the polycrystalline silicon film 13B of the intermediate layer.
The upper refractory metal silicide film 13C is formed of, for example, WSix (x is 2). In this gate electrode 13, the specific resistance value of the upper refractory metal silicide film 13C is smaller than that of each of the lower polycrystalline silicon film 13A and the intermediate polycrystalline silicon film 13B, so that the signal transmission speed can be increased. Can be achieved. Also,
The gate electrode 13 has a laminated structure of a polycrystalline silicon film 13A, a polycrystalline silicon film 13B, and a refractory metal silicide film 13C, and can increase the total cross-sectional area and the resistance value. Higher speed can be achieved. The refractory metal silicide film 13C, which is the upper layer of the gate electrode 13, is formed of MoSix, TiSix, or TaSi in addition to the WSix.
x may be used.

As shown in FIG. 8A, the gate width of the gate electrode 13 is smaller than the gate width of the gate electrode 7 of the driving MISFET Qd. That is, the transfer MISFET Qt is the drive MIS.
Since the driving capability is smaller than that of the FET Qd and the β ratio of the memory cell MC can be increased, the memory cell MC can stably hold the information stored in the information storage node.

Each of the source region and the drain region is
As shown in FIG. 6, the n + type semiconductor region 18 having a high impurity concentration and the n type semiconductor region 17 having a low impurity concentration provided between the n + type semiconductor region 18 and the channel forming region are mainly configured. Of the two types having different impurity concentrations, the n-type semiconductor region 17 is formed on the side portion of the gate electrode 13 in the gate length direction in self-alignment with the gate electrode 13.
The n-type semiconductor region 17 is formed of an n-type impurity, such as P, whose impurity concentration gradient is gentle at the pn junction with the channel formation region. The n + type semiconductor region 18 is formed on the side portion of the gate electrode 13 in the gate length direction with respect to the sidewall spacer 16 (actually, the driving MISFE described above is used.
Like TQd, it is self-aligned (to the mask that covers the sidewall spacers 16). The n + type semiconductor region 18 is formed of an n type impurity such as As that can make the depth of the junction with the p − type well region 2M (junction depth) shallow. That is, each of the transfer MISFETs Qt1 and Qt2 has an LDD structure. Since each of the transfer MISFETs Qt1 and Qt2 adopting this LDD structure can relax the electric field strength in the vicinity of the drain region, it is possible to reduce the amount of hot carriers generated and to reduce the change in the threshold voltage over time.

The sidewall spacers 16 are formed on the sidewalls of the gate electrode 13 in a self-aligned manner.
The sidewall spacers 16 are formed of an insulating film such as a silicon oxide film.

An insulating film 15 is formed on the gate electrode 13. The insulating film 15 is mainly the lower layer gate electrode 1
3. The upper conductive layer (23) is electrically separated from each other and is formed of, for example, a silicon oxide film. The insulating film 15 is formed to have a larger film thickness than the insulating film provided on the gate electrode 7.

As shown in FIG. 8A, the transfer MI is
One source region or drain region of the SFETQt1 is integrally formed with the drain region of the driving MISFETQd1. Transfer MISFET Qt1, drive MIS
Since each of the FETs Qd1 intersects the gate length direction (or the gate width direction), the active region of the driving MISFET Qd1 is in the X direction (direction coinciding with the gate length direction) around the integrally formed portion. Toward M for transfer
The active regions of the ISFET Qt1 are formed in the Y direction (direction matching the gate length direction). That is, each of the active regions of the transfer MISFET Qt1 and the drive MISFET Qd1 is formed into a substantially L-shaped plane. Similarly, one of the source region and the drain region of the transfer MISFET Qt2 has a driving MISFET Qd.
The two drain regions are integrally formed. That is, each of the active regions of the transfer MISFET Qt2 and the drive MISFET Qd2 is configured to have a substantially L-shaped planar shape.
Element isolation insulating film 4 (and p-type channel stopper region 5)
Are arranged at positions that define the transfer MISFET Qt and the driving MISFET Qd, which are integrally formed, along the outer periphery thereof, that is, the periphery of the L-shaped active region described above.

The plane shapes of the transfer MISFETs Qt1 and Qt2 are point-symmetrical with respect to the center point CP in the memory cell MC, similar to the relationship between the drive MISFETs Qd1 and Qd2. That is, as shown in FIG. 8A, the memory cell MC includes a transfer MISFET Qt1 and a drive M integrated with the transfer MISFET Qt1.
The ISFET Qd1, the transfer MISFET Qt2, and the driving MISFET Qd2 integrated with the ISFET Qd1 are point-symmetrical with respect to the center point CP (point-symmetrical shape in memory cell). The memory cell MC is a transfer MISFET Qt.
1 and driving MISFET Qd1, transfer MISFET
The planar shapes of Qt2 and the driving MISFET Qd2 are not the unbalanced shape but the same shape. The memory cell MC has transfer MISFETs Qt1 and Qt.
During each of t2, the driving MISFETs Qd1 and Qd2
Are arranged, and the driving MISFETs Qd1 and Qd2 are arranged facing each other. That is, the transfer MISFET Qt1 and the drive MISFET Qd of the memory cell MC.
1. Transfer MISFET Qt2 and drive MISFET
Each of Qd2 is separated only by the element isolation insulating film 4 and the p-type channel stopper region 5 arranged between each of the driving MISFETs Qd1 and Qd2, and the isolation dimension is limited only by the width dimension of the element isolation insulating film 4. Is regulated.

As shown in FIGS. 7 and 8, in the memory cell array MAY or the sub memory cell array SMEY, the transfer MISFETs Qt1 and Qt of the memory cell MC.
The respective planar shapes of 2 are the other memory cells MC with respect to the X1-X2 axis or the X3-X4 axis with another memory cell MC adjacent in the Y direction that coincides with the gate length direction of the transfer MISFET Qt. Transfer MISFET Qt
1 and Qt2 are formed in line symmetry with respect to their planar shapes. Similarly, transfer MISFETs Qt1 and Qt of the memory cell MC
Each plane shape of t2 is the transfer MISFET Qt.
MISFETQt of the other memory cell MC with respect to the X1-X3 axis or the X2-X4 axis between the memory cell MC and the other memory cell MC adjacent in the X direction that matches the gate width direction of the other memory cell MC.
1 and Qt2 are formed in line symmetry with respect to their planar shapes. That is, the transfer MISFET Qt of the memory cell MC is configured in a line-symmetrical shape for each memory cell MC in the array of the memory cells MC in the X direction and the Y direction.

Of the transfer MISFETs Qt of the memory cells MC arranged in the Y direction, the other drain or source regions of the transfer MISFETs Qt of the adjacent memory cells MC facing each other are integrally formed (see FIG. 9 (B)). That is, the transfer MIS of the other memory cell MC in the other drain region or source region of the transfer MISFET Qt of the adjacent one memory cell MC.
By configuring the other drain region or source region of the FET Qt, the occupied area of the other drain region or source region of the transfer MISFET Qt can be reduced. In addition, the element isolation insulating film 4 is provided between the other drain region or source region of the transfer MISFET Qt of one memory cell MC and the other drain region or source region of the other transfer MISFET Qt of the other memory cell MC facing it. Therefore, the area occupied by the memory cell MC can be reduced by the amount corresponding to the element isolation insulating film 4.

MISFET for transfer of the memory cell MC
Each of the gate electrodes 13 of Qt1 and Qt2 is connected to the word line (WL) 13 in the X direction that coincides with the gate width direction thereof, as shown in FIGS. 7 and 8. The word line 13 is formed integrally with the gate electrode 13 and is formed of the same conductive layer. Of the memory cells MC, transfer MI
The gate electrode 13 of the SFET Qt1 has a first word line (W
L1) 13 is connected, and the first word line 13 extends on the element isolation insulating film 4 in a substantially straight line in the X direction. Transfer M
The second word line (WL2) 13 is connected to the gate electrode 13 of the ISFET Qt2, and the second word line 13 extends substantially linearly in the X direction. That is, in one memory cell MC, two first word lines 13 and two second word lines 13 that are separated from each other and extend in parallel in the same X direction are arranged. In the memory cell array MAY, the first
The planar shapes of the word line 13 and the second word line 13 are line-symmetrical in the X direction with respect to the X1-X3 axis and the X2-X4 axis described above. The planar shapes of the first word line 13 and the second word line 13 are X1-X2 axis and X3-X.
It is configured to be line-symmetric in the Y direction with respect to each of the four axes.

The first word line (WL1) 13 is shown in FIG.
Further, as shown in FIG. 8A, it intersects with a portion protruding above the element isolation insulating film 4 in a direction coinciding with the gate width direction of the gate electrode 7 of the driving MISFET Qd1 of the memory cell MC. Similarly, the second word line (WL2) intersects with a portion protruding above the element isolation insulating film 4 in a direction coinciding with the gate width direction of the gate electrode 7 of the driving MISFET Qd2.

Also, the first word line (WL1) 13 and the second word line (WL2) 1 arranged in the memory cell MC.
A reference voltage line (source line: Vss) 13 is arranged between each of the three. One reference voltage line 13 is arranged in the memory cell MC, and the driving MISFET of the memory cell MC.
It is configured as a common source line for Qd1 and Qd2.
The reference voltage line 13 is formed of the same conductive layer as the word line 13, is separated from the word line 13, and extends on the element isolation insulating film 4 in a substantially straight line in the X direction. In the memory cell array MAY or the sub memory cell array SMEY, the planar shape of the reference voltage line 13 is X1-X3 axis, X2
It is configured to be line-symmetric in the X direction with respect to each of the −X4 axes. The planar shape of the reference voltage line 13 is X1-X2.
The axis and the X3-X4 axis are line-symmetrical in the Y direction.

The reference voltage line 13 is shown in FIG. 6 and FIG.
As shown in (A), the drive MISF of the memory cell MC.
On the element isolation insulating film 4 between each of the ETQd1 and Qd2, it intersects with a portion of the driving MISFETs Qd1 and Qd2 protruding in a direction corresponding to the gate width direction of the respective gate electrode 7.

The reference voltage line 13 is, as shown in FIGS. 6, 7 and 8A, the driving MISFETs Qd1 and Qd.
It is connected to each source region (n + type semiconductor region 11) of d2. The reference voltage line 13 is formed on the insulating film 12 formed in the same step as the step of forming the gate insulating film 12 of the transfer MISFET Qt on the source region of the driving MISFET Qd, as shown in FIG. 8A. Connection is made through the connected connection hole 14. The reference voltage line 13 has a laminated structure of three layers as described above, and the connection hole 14 is formed in the polycrystalline silicon film 13A after forming the polycrystalline silicon film 13A in the lower layer of the reference voltage line 13. . That is, the reference voltage line 13 connects the polycrystalline silicon film 13B of the intermediate layer directly to the source region through the connection hole 14 formed in the polycrystalline silicon film 13A of the lower layer and the insulating film 12 of the lower layer. The upper refractory metal silicide film 13C is connected to the source region through the layer polycrystalline silicon film 13B.

MISFET for driving this reference voltage line 13
The connection structure of Qd to the source region will be described later in the description of the manufacturing process, and the order of the forming steps will be described later. Since the connection hole 14 is formed,
When performing the photolithography technique and the etching technique, the surface of the gate insulating film 12 of the transfer MISFET Qt can be protected by the lower polycrystalline silicon film 13A. That is, since the film quality of the gate insulating film 12 of the transfer MISFET Qt can be prevented from being deteriorated, the withstand voltage of the gate insulating film 12 can be improved.

Further, the driving MISFE of the reference voltage line 13
The connection structure of TQd to the source region is such that the direct connection between the source region and the refractory metal silicide film 13C in the upper layer is abolished, and the polycrystalline silicon film 13B in the intermediate layer is interposed between the source region and the source region. The contact resistance value with the reference voltage line 13 can be reduced. Polycrystalline silicon film 13B as an intermediate layer of the reference voltage line 13
For the purpose of reducing the contact resistance value, a large amount of impurities for reducing the resistance value are introduced as compared with the lower polycrystalline silicon film 13A. On the contrary, the polycrystalline silicon film 1 under the reference voltage line 13
3A is an intermediate polycrystalline silicon film 13 for the purpose of improving the withstand voltage of the gate insulating film 12 of the transfer MISFET Qt.
Compared to B, less impurities that reduce the resistance value are introduced.

As shown in FIGS. 6, 7 and 8B, the capacitive element C arranged in the memory cell MC mainly includes the first electrode 7, the dielectric film 21, and the second electrode 23, respectively. Are sequentially laminated. That is, the capacitive element C has a stacked structure. 2 mainly in the memory cell MC
A plurality of capacitance elements C are arranged, and these two capacitance elements C are connected and arranged in parallel between the information storage nodes of the memory cells MC.

The first electrode 7 of the capacitive element C is a driving MI.
It is composed of a part of the gate electrode of the SFET Qd (polycrystalline silicon film formed in the first layer gate material forming step). That is, one driving MISFET Qd of the memory cell MC
The one gate electrode 7 constitutes the first electrode 7 of one of the two capacitive elements C. The other driving MISFET Qd2
Of the gate electrode 7 constitutes the first electrode 7 of the other capacitive element C.

The dielectric film 21 is formed on the first electrode (gate electrode) 7. The dielectric film 21 is formed in a region other than the first electrode 7, but on the first electrode 7, a region defined by each of the first word line (WL1) 13 and the reference voltage line 13, and A region defined by each of the two word lines (WL2) 13 and the reference voltage line 13 is used as a substantial dielectric film 21 of the capacitive element C. This dielectric film 21
Is formed of, for example, a silicon oxide film.

The second electrode 23 is formed on the first electrode 7 with the dielectric film 21 interposed therebetween. Similar to the dielectric film 21, the second electrode 23 has a region defined by each of the word line (WL) 13 and the reference voltage line 13, which is used as a substantial second electrode 23 of the capacitive element C. The second electrode 23 is formed in the third layer gate material forming step, and is formed of, for example, a single-layer polycrystalline silicon film. An n-type impurity such as P (or As) that reduces the resistance value is introduced into this polycrystalline silicon film.

That is, the capacitive element C is the driving MIS.
The gate electrode 7 of the FET Qd1 is used as the first electrode 7, and the capacitive element C is arranged in the region of the driving MISFET Qd1.
The gate electrode 7 of the driving MISFET Qd2 is replaced with the first electrode 7
And the capacitive element C arranged in the region of the driving MISFET Qd2. The second electrode 2 of this capacitive element C
3, which will be described later, is also configured as the gate electrode 23 of the load MISFET Qp. The second electrode 23 of the capacitive element C is connected to the drain region of the load MISFET Qp (actually the n-type channel forming region 26N) and the transfer MISF.
One semiconductor region of ETQt, driving MISFET Qd
Is also configured as a conductive layer (intermediate conductive layer or coupling conductive layer) 23 that connects the drain region of the gate electrode 7 of the driving MISFET Qd.

The second electrode 23 of the one capacitance element C arranged in the region of the driving MISFET Qd1 has the driving M.
Drain region (11) of ISFET Qd1, transfer MI
One semiconductor region (18) of SFETQt1, drive M
It is connected to each of the gate electrodes 7 of the ISFET Qd2.
These connections connect the second electrode 23 of the capacitive element C to the driving M
The conductive layer 23 is formed in the same layer as and integrally with the second electrode 23, which is drawn out in the X direction that coincides with the gate length direction of the ISFET Qd1. The conductive layer 23 includes the insulating film (the same layer as the dielectric film 21) 21, the connection hole (opening) 22 formed by removing the insulating film 12 and the like, the drain region (11), one semiconductor region (18), It is connected to each of the gate electrodes 7. Similarly, the driving MISFET Q
The second electrode 2 of the other capacitive element C arranged in the region of d2
3 is a drain region (1 of the driving MISFET Qd2
1), one semiconductor region (18) of the transfer MISFET Qt2, and the gate electrode 7 of the drive MISFET Qd1. These connections are the second of the capacitive element C.
This is performed by the conductive layer 23 in which the electrode 23 is drawn out in a direction that coincides with the gate length direction of the driving MISFET Qd2. The conductive layer 23 is connected to the drain region (1
1), one of the semiconductor regions (18) and the gate electrode 7 are connected.

The connection structure between one of the semiconductor regions (18) of the transfer MISFET Qt, the drain region (11) of the driving MISFET Qd, the gate electrode 7 of the driving MISFET Qd and the conductive layer 23 is shown in FIG. The details are shown in the enlarged sectional view). As shown in FIG. 12, the connection hole 2
In the region whose periphery is defined by 2, an n @ + type semiconductor region 21N having a high impurity concentration is formed in the main surface of the p @-type well region 2M. As will be described later, the n + type semiconductor region 21N is formed by introducing an n type impurity using an etching mask for forming the connection hole 22 in the insulating film 21 as an impurity introduction mask.
Although there is some lateral diffusion, it has a planar shape that is almost the same as the planar shape of the connection hole 22. The gate electrode 7
The gate electrode 7 serves as an impurity introduction mask depending on the condition of impurity introduction, so that the n + -type semiconductor region 21N is not formed under the gate electrode 7.

Each of the n + type semiconductor regions 11 and 18 is formed with a junction depth of, for example, about 0.2 to 0.3 [μm] in the present embodiment.
1N is a junction depth deeper than the junction depth of each of the n + type semiconductor regions 11 and 18, for example, 0.35 to 0.45 [μ
m] is set. That is, the n + type semiconductor region 21
N is from the end of the connection hole 22 of the n + type semiconductor region 11 or 18 (p − type semiconductor substrate 1) to the n + type semiconductor region 1
1 or 18 and the p-type semiconductor substrate 1 are formed to a depth enough to capture the crystal defects generated across the pn junction. Crystal defects mainly occur due to the volume contraction of the conductive layer 23, the difference in thermal expansion coefficient between the conductive layer (polycrystalline silicon film) 23 and the insulating film (silicon oxide film), etc. In the cell MC, n + type semiconductor regions 11 and 18
For driving MISF at the connection between each of the above and the conductive layer 23.
Since the volumetric shrinkage of the gate electrode (polycrystalline silicon film) 7 of ETQd is also added and crystal defects frequently occur, the arrangement of the n + type semiconductor region 21N is effective.

Further, as shown in FIG. 1, in the memory cell MC, a similar connection structure has a transfer MISFETQ.
Intermediate conductive layer 2 when connecting complementary data line (DL) 33 to n + type semiconductor region 18 which is the other semiconductor region of t
Since it exists at the connection portion between the n-type semiconductor regions 3 and 3, the n + type semiconductor region 21N is also formed at this connection portion. In other words, in the SRAM manufacturing process described later, the transfer MIS is used.
N + which is one of the semiconductor regions of the FETQt and the other of the FETQt
The connection hole 22 is formed on the surface of the semiconductor region 18 in the same manufacturing process.
Are formed, the n + type semiconductor regions 2 are formed in the semiconductor regions of the transfer MISFET Qt, respectively.
1N is formed.

In the memory cell array MAY or the sub memory cell array SMEY, the capacitance elements C of the memory cells MC arranged in the X direction are relative to the X1-X3 axis or the X2-X4 axis shown in FIGS. 7 and 8B. The second electrode 2
The planar shape of 3 (and the conductive layer 23) is axisymmetric. The capacitive elements C of the memory cells MC arranged in the Y direction are the same as the above-mentioned drive MISFET Qd and transfer MI.
Unlike the line-symmetrical arrangement of the SFETs Qt, the planar shape of the second electrode 23 is non-line-symmetrical. That is, with respect to the arrangement of the second electrodes 23 of the respective capacitive elements C of the plurality of memory cells MC arranged in the X direction, the plurality of memory cells arranged in the X direction of the next stage adjacent in the Y direction. The capacitive element C of the MC has the same structure as the second electrode 23 of the preceding stage.
The plane shape of the is linearly symmetric in the X direction, and the second
The planar shape of the electrode 23 is formed by shifting in the X direction by one memory cell MC (one memory cell pitch) with respect to the array of the memory cells MC in the preceding stage. In the memory cell array MAY, the capacitive element C of the aforementioned memory cell MC
The arrangement of the second electrodes 23 (and the conductive layers 23) will be described later. The plane shape of the power supply voltage line (Vcc: 26P) and the load MISFET Qp formed mainly on the upper layer of the second electrode 23 is in the Y direction. On the other hand, it is composed of non-line symmetry, so it is composed of non-line symmetry.

Two load MISs of the memory cell MC
Each of the FETs Qp1 and Qp2 is shown in FIG. 6, FIG. 7 and FIG.
As shown in (B), it is formed on the region of the driving MISFET Qd. The load MISFET Qp1 is a drive MI.
It is formed on the area of the SFET Qd2 and has a load MISFE.
The TQp2 is formed on the driving MISFET Qd1.
This load MISFET Qp has a so-called SOI structure (or T
FT structure). MISFET Qp1 for load,
Each of Qp2 is arranged so that the gate length direction thereof is substantially orthogonal to the direction in which the gate length direction of each of the driving MISFETs Qd1 and Qd2 coincides. This load MISFET Qp1,
Each of Qp2 is mainly composed of an n-type channel forming region 26N, gate insulating films 24 and 24G, a gate electrode 23, a source region 26P and a drain region 26P.

The gate electrode 23 is composed of the second electrode (polycrystalline silicon film formed in the third layer gate material forming step) 23 of the capacitive element C. That is, the drive MISF
The second of the one capacitive element C arranged in the region of ETQd1
The electrode 23 is the gate electrode 23 of the load MISFET Qp2.
Make up. The second electrode 23 of the other capacitive element C arranged in the region of the driving MISFET Qd2 is the load MISF.
The gate electrode 23 of ETQp1 is formed.

As shown in FIG. 12, the load MISF is used.
ETQp gate electrode 23 (conductive layer 23, intermediate conductive layer 2
(Including all 3), a part of the film thickness of the gate electrode 23 is oxidized (or nitrided) from the surface after patterning,
Corner of the surface (corner between the upper surface of the surface of the gate electrode 23 and the side surface of the patterned surface, reference numeral 2 in FIG. 12)
The cross-sectional shape of the portion 23C (shown with 3C) is relaxed from a sharp projecting shape to a rounded cross-sectional shape. Since the oxidation of the surface of the gate electrode 23 does not sufficiently improve the cross-sectional shape to the extent that a native silicon oxide film having a film thickness of 1 to 3 [nm] is formed, the surface of the gate electrode 23 is naturally oxidized. It is performed to such an extent that a silicon oxide film having a thickness larger than that of the silicon film can be formed. In addition, the gate electrode 23
Is necessary to remain as a conductor region, the oxidation from the surface of the gate electrode 23 is limited to a part of the film thickness of the gate electrode 23. That is, the oxidation of the surface of the gate electrode 23 is
It is performed to the extent that a silicon oxide film having a film thickness equal to or larger than that of the natural silicon oxide film can be formed, and is limited to a part of the film thickness of the gate electrode 23. In the SRAM of this embodiment, oxidation is performed so that a silicon oxide film having a film thickness of about 5 to 15 [nm] can be formed on the surface of the gate electrode 23.

As shown in FIG. 12, the load MISFE is used.
The gate electrode 23 of TQp is on the gate electrode 7 of the driving MISFET Qd, on the word line 13 having a higher position than the gate electrode 7, on the reference voltage line (Vss) 13, and in the p-type well region 2M. They are arranged over regions having different heights from the main surface. When the end portion of the gate electrode 23 is located in the stepped region of the base shape, the gate electrode 23
Patterning is performed by anisotropic etching for the purpose of microfabrication, the corner portion 23 of the surface of the gate electrode 23
The cross-sectional shape of C is formed to have a sharp protruding shape with an acute angle. Therefore, the above-mentioned gate electrode 2
Of the gate electrode 23 based on the oxidation of part of the film thickness of the surface of No. 3
The improvement of the cross-sectional shape of the corner portion 23C of the surface of the SRAM is particularly the SRAM having the load MISFET Qp having the SOI structure.
Is effective in.

The improvement of the cross-sectional shape of the corner portion 23C on the surface of the gate electrode 23 can reduce the electric field concentration in the area of the corner portion 23C, and the gate insulating film 24 formed along the corner portion 23C. The film quality can be improved, and as a result, the withstand voltage of the gate insulating film 24 can be improved.

The gate electrode 23 (similarly to the conductive layer 2
3, a side wall spacer 24S is formed on the side surface of the surface of each of the intermediate conductive layers 23). The sidewall spacer 24S is formed only on the side surface of the gate electrode 23 by depositing a silicon oxide film by, for example, a CVD method, and anisotropically etching the silicon oxide film by an amount corresponding to the deposited film thickness. .. This sidewall spacer 24S
Can improve the cross-sectional shape of the corner portion 23C on the surface of the gate electrode 23 described above.
The withstand voltage of 4 can be improved.

The gate insulating film 24 is the SR of this embodiment.
In the load MISFET Qp of AM, the gate electrode 2
3 has a three-layer structure in which a natural silicon oxide film (not shown), a silicon oxide film 24G, and a silicon oxide film 24F are sequentially laminated from the surface of No. 3. The natural silicon oxide film below the gate insulating film 24 is the same in the SRAM manufacturing process from the step of depositing the polycrystalline silicon film that is the gate electrode 23 to the step of forming the silicon oxide film 24F above the gate insulating film 24. It can be eliminated if it is carried out in a vacuum system, but it is almost certainly formed if there is an opening to the atmosphere in the middle. The natural silicon oxide film is formed with a very thin film thickness as described above. The intermediate silicon oxide film 24G is the gate electrode 23 described above.
For the purpose of improving the cross-sectional shape of the corner portion 23C on the surface of, the above-mentioned film thickness is formed. The upper silicon oxide film 24F is
It is formed of a silicon oxide film deposited by the CVD method, for example, 50
It is formed with a film thickness of about 70 [nm].

As the gate insulating film 24, a silicon nitride film may be used instead of the intermediate silicon oxide film 24G. That is, in this case, the improvement of the cross-sectional shape of the corner portion 23C on the surface of the gate electrode 23 is performed by nitriding. Further, the gate insulating film 24 may be mainly composed of the silicon oxide film 24F by removing the intermediate silicon oxide film 24G and then depositing the silicon oxide film 24F by the CVD method in the removed region. . In this case, the natural silicon oxide film is very thin, and the gate insulating film 2 has the same thickness as the silicon oxide film 24F.
4 is almost determined, and the silicon oxide film 24
Since F can be formed with a uniform film thickness without being affected by the crystal grains of the underlying gate electrode (polycrystalline silicon film) 23, the controllability of the film thickness of the gate insulating film 24 is extremely high.

The n-type channel forming region 26N is formed on the gate electrode 23 with the gate insulating film 24 interposed therebetween. n
The type channel formation region 26N is arranged so that its gate length direction substantially coincides with the direction in which it coincides with the gate width direction of the driving MISFET Qd. The n-type channel formation region 26N is
It is formed in the gate material forming step of the fourth layer and is made of, for example, a polycrystalline silicon film. MISF for load is used for the polycrystalline silicon film.
An n-type impurity (for example, P) that sets the threshold voltage of ETQp to the enhancement type is introduced. MIS for load
The FET Qp can sufficiently supply the power supply voltage Vcc to the information storage node during operation (ON operation), and can stably hold information. In addition, the load MISFET Qp is
During the FF operation), since the supply of the power supply voltage Vcc to the information storage node can be cut off almost certainly, the standby current amount can be reduced and the power consumption can be reduced. This point, MISF for load
ETQp is different from that of the high resistance element for load (a minute current always flows through the high resistance element for load).

The source region 26P is a p-type conductive layer (26P) integrally formed on one end side (source region side) of the n-type channel forming region 26N and formed of the same conductive layer.
Composed of. That is, the source region (p-type conductive layer) 26
P is formed of a polycrystalline silicon film formed in the fourth layer gate material forming step, and a p-type impurity (for example, BF ₂ ) is introduced into the polycrystalline silicon film. The source region 26P is shown in FIG.
It is configured in a region surrounded by an alternate long and short dash line with reference numeral 26P attached to (B) (a part is configured as a power supply voltage line 26P). The drain region 26P is integrally formed on the other end side (drain side) of the n-type channel forming region 26N, and like the source region 26P, is formed of a p-type conductive layer (26P) formed of the same conductive layer. It Drain region 2
6P is formed in a region surrounded by a chain line with reference numeral 26P. That is, in the manufacturing process described later, the p-type impurity forming the source region and the drain region 26P is introduced into the region 26P surrounded by the alternate long and short dash line, and the other region is formed as the n-type channel forming region 26N. It

The drain region 26P of the load MISFET Qp1 is connected to one semiconductor region of the transfer MISFET Qt1, the drain region of the drive MISFET Qd1 and the gate electrode 7 of the drive MISFET Qd2. Similarly, the drain region 26P of the load MISFET Qp2 is connected to one semiconductor region of the transfer MISFET Qt2, the drain region of the drive MISFET Qd2, and the gate electrode 7 of the drive MISFET Qd1. These connections are made through the conductive layer 23.

The drain region 26P of the load MISFET Qp is separated from the gate electrode 23 via the n-type channel forming region 26N. In other words, the load MIS
In the FET Qp, the gate electrode 23 and the drain region 26P are separated without overlapping. That is, the load MISF
The drain region 26P side of ETQp has an offset structure. Load MISFETQ with this offset structure
p is an n-type channel forming region 26N−drain region 26P
The breakdown withstand voltage can be improved. That is, this offset structure has the drain region 26P and the gate electrode 2
3 is separated from the n-type channel forming region 26N in which the charge is induced by the drain region 26P.
The breakdown voltage of the pn junction between the n-type channel forming region 26N and the n-type channel forming region 26N can be improved. In the case of this embodiment, the load M
The ISFET Qp is composed of an offset dimension (separation dimension) of about 0.6 [μm] or more.

As described above, the conductive layer 23 is the capacitive element C.
Of the second electrode 23 (polycrystalline silicon film formed in the third layer gate material forming step). Conductive layer 2
3 is formed of the same conductive layer as the gate electrode 23 of the load MISFET Qp. The conductive layer 23 passes through a connection hole 25 formed in the interlayer insulating film 24 and is used as an upper load MISFE.
It is connected to the p-type drain region 26P of TQp. Also,
As described above, the conductive layer 23 is connected to the one semiconductor region (18) of the transfer MISFET Qt, the drain region (11) of the driving MISFET Qd, and the gate electrode 7 through the connection hole 22. Conductive layer 23 configured in this way
Corresponds to the film thickness of the conductive layer 23 and the dimension between the position of the connection hole 25 on the upper side of the conductive layer 23 and the position of the connection hole 22 on the lower side of the conductive layer 23, and is the drain region 26 of the load MISFET Qp.
The other end of P, the one semiconductor region (18) of the transfer MISFET Qt, and the drain region (11) of the driving MISFET Qd can be separated from each other. Since the conductive layer 23 is formed of a polycrystalline silicon film into which an n-type impurity is introduced, each of the one semiconductor region (18) and the drain region (11) of the p-type impurities forming the p-type drain region 26P is formed. The diffusion distance to the conductive layer 23 can be increased. That is, the conductive layer 2
3 is a transfer MISFETQt, a drive MISFETQ
In each channel formation region of d, the load MISFETQ
The diffusion of p-type impurities in the p drain region 26P is reduced, and the transfer MISFET Qt and the drive MISFE are reduced.
It is possible to prevent the variation of each threshold voltage of TQd. The conductive layer 23 is the gate electrode 2 of the load MISFET Qp.
3. Since the second electrode 23 of the capacitive element C is formed of the same conductive layer (the same manufacturing process), the number of conductive layers can be structurally reduced, and the number of manufacturing steps in the manufacturing process can be reduced.

As shown in FIGS. 6, 7 and 8B,
A power supply voltage line (Vcc) 26P is connected to the source region (p-type conductive layer 26P) of the load MISFET Qp.
The power supply voltage line 26P is the p-type conductive layer 2 which is the source region.
6P and the same conductive layer. That is, the power supply voltage line 26P is formed of the polycrystalline silicon film formed in the fourth layer gate material forming step, and p-type impurities (for example, BF ₂ ) for reducing the resistance value are introduced into this polycrystalline silicon film. To be done.

Two power supply voltage lines (Vcc) 26P are arranged in the memory cell MC. These two power supply voltage lines 26
In the memory cell array MAY or the sub memory cell array SMEY, Ps are separated from each other and extend substantially parallel to the same X direction. One power supply voltage line 26P arranged in the memory cell MC is formed integrally with the source region of the load MISFET Qp2, and the first word line (WL1) 1
3 extends along a direction coinciding with the extending direction.
The other power supply voltage line 26P is connected to the load MISFET Qp1.
Of the second word line (WL
2) Extend on 13 along a direction coinciding with the extending direction.

As shown in FIGS. 7 and 8B, in the memory cell MC, one power supply voltage line 26P extends in the X direction and is complementary to the other semiconductor region (18) of the transfer MISFET Qt1. The connection portion (intermediate conductive layer 29 described later) of the sex data line DL with the first data line (DL1: 33) is detoured in the Y direction. That is, one power supply voltage line 26P is connected to the load MISFETQ of the memory cell MC.
It does not pass between p1 and the connecting portion and is adjacent to this connecting portion in the Y direction (arranged on the upper side in FIG. 8B).
It passes between the other memory cell MC and the load MISFET Qp1 to bypass the memory cell MC. Further, one power supply voltage line 26P is also used as one power supply voltage line 26P of another memory cell MC adjacent in the Y direction (arranged on the upper side in FIG. 8B). Similarly, the other power supply voltage line 26P extends in the X direction and is a connection portion between the other semiconductor region (18) of the transfer MISFET Qt2 and the second data line (DL2: 33) of the complementary data line DL. (Intermediate conductive layer 29 described later) is detoured in the Y direction. The other power supply voltage line 26P
Is a load of another memory cell MC that bypasses between the load MISFET Qp2 of the memory cell MC and the connecting portion and is adjacent to this connecting portion in the Y direction (arranged on the lower side in FIG. 8B). It does not pass between the MISFET Qp2 for use.
Similarly, the other power supply voltage line 26P is also used as the other power supply voltage line 26P of another memory cell MC adjacent to the Y direction (arranged on the lower side in FIG. 8B). That is, one memory cell MC has two power supply voltage lines 26P.
However, since each of the two power supply voltage lines 26P also serves as the power supply voltage line 26P of another memory cell MC that is vertically adjacent in the Y direction, one memory cell M
In C, substantially one power supply voltage line 26P is arranged.

The two power supply voltage lines 26P arranged in the memory cells MC correspond to the X1-X3 axis or the X2-X4 axis shown in FIG. 8B in the memory cell array MAY or the sub memory cell array SMEY. , The plane shape is line-symmetric in the X direction. Further, the two power supply voltage lines 26P arranged in the memory cell MC are
Different from the line-symmetrical arrangement of the ISFET Qd and the transfer MISFET Qt, and like the arrangement of the second electrode 23 of the capacitive element C, the planar shape is configured to be non-axisymmetric in the Y direction. That is, with respect to the planar shape of the power supply voltage line 26P extending the plurality of memory cells MC arranged in the X direction, the memory cells MC arranged in the X direction of the next stage adjacent in the Y direction are extended. The power supply voltage line 26P is the memory cell MC of the preceding stage.
Of the power supply voltage line 26P extending in the same manner as the power supply voltage line 26P extending in the X direction, and one memory cell MC (1 memory cell Pitch) is shifted in the column direction. In the memory cell array MAY or the sub memory cell array SMAY, the transfer MISF of the power supply voltage line 26P
The detour of the connection portion (intermediate conductive layer 29) between the other semiconductor region of ETQt and the complementary data line DL is all performed on the upper side in the same Y direction.

The second electrode 23 (and the conductive layer 23) of the capacitive element C arranged on the driving MISFET Qd1 among the capacitive elements C arranged in the memory cell MC described above is as shown in FIG.
As shown in (B), one power supply voltage line 26P is diverted to the other memory cell MC on the upper side in the connection portion (intermediate conductive layer 29), and the connection portion and the load MISFE.
Since the distance from TQp1 is reduced, the planar shape of the memory cell MC is reduced by the amount corresponding to this reduced dimension. In addition, MISFE for driving the memory cell MC
The second electrode 23 (and the conductive layer 23) of the capacitive element C disposed on the TQd2 connects the other power supply voltage line 26P to the memory cell MC at the connection portion (intermediate conductive layer 29).
To the inside, and the connection part and the load MISFET Qp
Since the other power supply voltage line 26P is passed between 2 and
The planar shape of the memory cell MC increases by the amount corresponding to the passage of the other power supply voltage line 26P. That is, the power supply voltage line 26P always extends over the memory cell MC for the purpose of improving the degree of integration (uses the area occupied by the memory cell MC).
Therefore, when the plane shape of the second electrode 23 (and the conductive layer 23) of the capacitive element C arranged on the driving MISFET Qd2, which is the side where the power supply voltage line 26P bypasses the memory cell MC, is used as a reference, The second electrode 23 (and the conductive layer 2) of the capacitive element C arranged on the driving MISFET Qd1.
The plane shape of 3) is reduced because the power supply voltage line 26P does not bypass the memory cell MC. Therefore, the second electrode 23 (and the conductive layer 23) of the capacitive element C of the memory cell MC
Are linearly symmetric in the X direction (X1-X2 axis or X3-X4 axis), all of the (drive M) in the planar shape of the second electrode 23 placed on the drive MISFET Qd2.
Although the planar shape of the second electrode 23 (on the ISFET Qd1) is regulated and the occupied area of the memory cell MC increases, as described above, the power supply voltage line 26P is arranged non-axisymmetrically in the Y direction. The planar shape of the second electrode 23 on the driving MISFET Qd1 is reduced, and an amount corresponding to this reduction is
The area occupied by the memory cell MC can be reduced.

In the memory cell MC, a total of 4 layers including the first conductive layer 7, the second conductive layer 13, the third conductive layer 23, and the fourth conductive layer 26. The so-called gate material of the layer is constituted. As shown in FIGS. 6 and 8C (plan views showing patterns of specific conductive layers), in the memory cell MC, the second conductive layer 13 is the transfer MIS.
It is configured as a gate electrode 13, a word line 13 and a reference voltage line 13 of the FET Qt. Each of the word line (including a gate electrode 13 in a part thereof) 13 and the reference voltage line 13 is
Since they are the same conductive layer, they are separated from each other by the minimum processing dimension of the photolithography technique or more in the manufacturing process of the SRAM, and extend substantially parallel to the X direction. In the memory cell MC, the third conductive layer 23 is the gate electrode 23 of the load MISFET Qp and the conductive layer 2
3, the intermediate conductive layer 23, and the second electrode 23 of the capacitive element C. In the memory cell MC, the fourth conductive layer 26 is configured as the n-type channel forming region 26N, the p-type source region 26P, the p-type drain region 26P and the power supply voltage line 26P of the load MISFET Qp. Since the load MISFETs Qp1 and Qp2 have the same gate length direction in the Y direction and are the same conductive layer, they are separated from each other by a minimum processing dimension of the photolithography technique or a dimension larger than that in the SRAM manufacturing process. It extends substantially parallel to the Y direction.

A plurality of conductive layers 1 configured as described above
In the memory cell MC in which 3, 23, and 26 are stacked, as shown in FIG. 8C, the lower second conductive layer 13 and the intermediate third conductive layer 23 are respectively formed. Are formed in separate conductive layers, so that they can be separated with a fine dimension Lm smaller than the minimum processing dimension of the photolithography technique. In other words, the memory cell MC
Has a plurality of conductive layers 13, 23, 26 mainly for the purpose of reducing the occupied area and improving the integration degree of SRAM.
Each of them is positively brought close to each other with a fine dimension Lm. However, between the conductive layer 13 of the second layer and the conductive layer 23 of the third layer, which are separated by the fine dimension Lm, the film thickness is thinner than about one half of the fine dimension Lm. When the interlayer insulating film (21) is formed to have a uniform film thickness (eg, deposited by the CVD method), the fine dimension Lm
In the region (1), a groove having a small opening size and a deep groove (a groove having a crevasse shape in cross section) is generated. Since the fourth conductive layer 26 is formed of a polycrystalline silicon film deposited by the CVD method, the polycrystalline silicon film is buried in the groove, and the fourth conductive layer 26 is patterned. It cannot be completely removed in the etching process. In other words, load MISFET
Each of Qp1 and Qp2 is left unetched in a groove formed in a region of a minute dimension Lm between the second conductive layer 13 of the lower layer and the third conductive layer 23 of the intermediate layer. As a result, a short circuit occurs through the remaining polycrystalline silicon film.

The memory cell MC of the SRAM of this embodiment is
With the main purpose being to cut off the grooves generated between the load MISFETs Qp1 and Qp2, as shown by the symbol OS in FIG. 8C, the second conductive layer 13 and the third conductive layer 13 are formed. When there is a portion separated by a fine dimension Lm between the respective conductive layers 23, the at least a part of the third conductive layer 23 is superposed on the second conductive layer 13 ( In FIG. 8C, the overlapped region is shown by hatching.) In FIG. 8C, reference numeral NS indicates the second conductive layer 1
3 shows a region where the conductive layer 23 of the third layer is separated from each other with a fine dimension Lm and an etching residue may occur. The conductive layer 13 of the second layer and the conductive layer 23 of the third layer are shown. The respective superpositions of the conductive layers 23 are performed in a shape that crosses the region NS (a shape in which the etching residue is partially generated, but the etching residue is cut off in the middle).

MISFET for transfer of the memory cell MC
The other semiconductor region (18) of Qt is connected to the complementary data line (DL) 33, as shown in FIGS.
One transfer MISFET Qt1 of the memory cell MC is connected to the first data line (DL1) of the complementary data line 33. The other transfer MISFET Qt2 is connected to the second data line (DL2) of the complementary data line 33. The other semiconductor region of the transfer MISFET Qt and the complementary data line 33 are connected to each other through the intermediate conductive layers 23 and 29 sequentially stacked from the lower layer side toward the upper layer side.

The intermediate conductive layer 23 is formed on the interlayer insulating film 21, as shown in FIGS. 6, 7 and 8B. A part of the intermediate conductive layer 23 is transferred through the connection hole 22 formed in the interlayer insulating film 21 in the region defined by the sidewall spacer 16 to transfer MISFE.
It is connected to the other semiconductor region (18) of TQt. The connection hole 22 has an opening size larger than the region defined by the sidewall spacer 16 (larger on the gate electrode 12 side). As described above, the sidewall spacers 16 serve as the gate electrodes 12 of the transfer MISFET Qt.
Formed on the sidewalls of the same in a self-aligned manner. That is,
A part of the intermediate conductive layer 23 is at a position regulated by the sidewall spacer 16 and self-aligned with the position for transfer M.
It is connected to the other semiconductor region of the ISFET Qt. The other part of the intermediate conductive layer 23 is at least the intermediate conductive layer 23.
And an amount corresponding to the mask alignment margin dimension in the manufacturing process of the upper intermediate conductive layer 29 and the upper intermediate conductive layer 29 are drawn onto the interlayer insulating film 21. The intermediate conductive layer 23 absorbs the mask misalignment in the manufacturing process even if the semiconductor misalignment of the transfer MISFET Qt and the intermediate conductive layer 23 occur, and the other semiconductor region of the transfer MISFET Qt is absorbed. In contrast, the intermediate conductive layer 23 can be apparently connected by self-alignment.

The intermediate conductive layer 23 is the load MISF.
ETQp gate electrode 23, capacitive element C second electrode 2
3 and the conductive layers 23 are formed of the same conductive layer. That is, it is formed of a polycrystalline silicon film formed in the third layer gate material forming step, and an n-type impurity that reduces the resistance value is introduced into this polycrystalline silicon film.

The intermediate conductive layer 29 is formed on the interlayer insulating film 27, as shown in FIGS. One end of the intermediate conductive layer 29 has a connection hole 28 formed in the interlayer insulating film 27.
Through to the intermediate conductive layer 23. The intermediate conductive layer 23 is connected to the other semiconductor region of the transfer MISFET Qt as described above. The other end of the intermediate conductive layer 29 is drawn out in the X direction and connected to the complementary data line 33 through a connection hole 31 formed in the interlayer insulating film 30.

The intermediate conductive layer 29 whose one end side is connected to the other semiconductor region of the transfer MISFET Qt1 is the first of the complementary data lines 33 extending in the Y direction on the other semiconductor region of the transfer MISFET Qt2. Data line (D
L1) It is led out in the X direction to the bottom of 33, and is connected to the first data line 33 in this pulled out region. Similarly, the intermediate conductive layer 29 whose one end side is connected to the other semiconductor region of the transfer MISFET Qt2 is formed of the transfer MISFE.
The complementary data lines 33 extending in the Y direction on the other semiconductor region of TQt1 are led out in the X direction down to the second data line (DL2) 33, and in the pulled out region, the second data line 33 Connected. That is, the intermediate conductive layer 29 includes the transfer MISFET Qt1 of the memory cell MC,
A cross wiring structure that connects each of Qt2 and each of the first data line 33 and the second data line 33 extending to the inversion position in the X direction is configured.

The intermediate conductive layer 29 is formed of a refractory metal film, for example, a W film formed in the metal material forming step of the first layer of the manufacturing process, the forming method of which will be described later.
The W film has a smaller specific resistance value than the polycrystalline silicon film and the refractory metal silicide film.

As shown in FIG. 6, the interlayer insulating film 27, which is the base of the intermediate conductive layer 29, is made of silicon oxide films 27A and BP.
It is composed of a composite film in which the SG films 27B are sequentially laminated. The BPSG film 27B, which is the upper layer of the interlayer insulating film 27, is subjected to glass flow, and the surface is subjected to flattening processing.

As shown in FIG. 6, the interlayer insulating film 30 is composed of a deposition type silicon oxide film 30A and a coating type silicon oxide film 3.
0B and the deposition type silicon oxide film 30C are sequentially laminated, and each layer has a three-layer laminated structure. Lower silicon oxide film 30
A, Each of the upper layer of the silicon oxide film 30C, as described later, tetra lizard silane (TEOS: T etra E thoxy S ilan
e) It is deposited by a plasma CVD method using a gas as a source gas. The lower silicon oxide film 30A is deposited with a uniform film thickness along the stepped shape of the base, and particularly in the recessed part of the stepped shape of the base, the overhang shape above the recessed portion is unlikely to occur. That is, the lower silicon oxide film 30A can reduce the generation of cavities due to the overhang shape.
The intermediate silicon oxide film 30B is formed on the spin-on-glass ( S pi
coated with n O n G lass) method, after the baking process is performed, it is entirely etched (etch back). The intermediate silicon oxide film 30B is intensively formed (remains) on the step-shaped portion of the surface of the lower silicon oxide film 30A, and the surface of the interlayer insulating film 30 can be flattened. The intermediate silicon oxide film 30B is basically formed on the stepped portion on the surface of the lower silicon oxide film 30A except the region of the connection hole 31 which connects the intermediate conductive layer 29 and the complementary data line 33. To be done.
That is, it is possible to prevent the complementary data line (aluminum alloy) 33 from being corroded due to the moisture contained in the intermediate silicon oxide film 30B. The upper silicon oxide film 30C covers the surface of the intermediate silicon oxide film 30B.
The deterioration of the film quality of 0B can be prevented.

The complementary data line (DL) 33 is shown in FIG.
As shown in, it is formed on the interlayer insulating film 30. The complementary data line 33 is connected to the extended portion of the intermediate conductive layer 29 through the connection hole 31. The complementary data line 33 is formed in the metal material forming step of the second layer of the manufacturing process. The complementary data line 33 includes a lower metal film 33A, an intermediate aluminum alloy film 33B, and an upper metal film 33C.
Each of these is sequentially laminated to form a three-layer laminated structure. The lower metal film 33A is basically a transfer MISFE.
A barrier metal film for preventing mutual diffusion of the other semiconductor region (18) of TQt, silicon (Si) of the intermediate conductive layer 23, and aluminum (AL) of the aluminum alloy film 33B of the intermediate layer, and so-called alloy spike. To form as. The lower metal film 33A is formed of, for example, a TiW film.
The aluminum alloy film 33B of the intermediate layer has a smaller specific resistance value than the polycrystalline silicon film, the refractory metal film, and the refractory metal silicide film. The aluminum alloy film 33B is made of Cu, S
It is made of aluminum to which at least one of i is added. Cu basically has the effect of improving electromigration resistance. Si basically has the function of preventing alloy spikes. The upper metal film 33C is basically the intermediate aluminum alloy film 33.
It is configured for the purpose of preventing the aluminum hilllock phenomenon of B. Further, the upper metal film 33C is used for the purpose of reducing the reflectance of the surface of the intermediate aluminum alloy film 33B and preventing the diffraction phenomenon (halation) in the exposure process at the time of patterning by the photolithography technique. It is formed.

The complementary data line 33 may be formed by using the aluminum alloy film 33B as an aluminum film or by removing the lower metal film 33A and forming a single-layer aluminum alloy film.

The complementary data line 33 extends in the Y direction on the memory cell MC as shown in FIG. One of the complementary data lines 33, the first data line (DL1) 33
Extends in the Y direction on the driving MISFET Qd1, the transfer MISFET Qt2, and the load MISFET Qp2 of the memory cell MC. The other second data line (DL2) 33
Extends in the Y direction on the driving MISFET Qd2, the transfer MISFET Qt1 and the load MISFET Qp1 of the memory cell MC. That is, the first complementary data line 33
The data line 33 and the second data line 33 are separated from each other and extend substantially parallel to each other in the Y direction.

As shown in FIG. 7, the memory cell array M
In the AY or sub memory cell array MAY, the complementary data lines 33 of the memory cells MC arranged in the X direction are arranged in line symmetry with respect to the X1-X3 axis or the X2-X4 axis. The planar shape of the complementary data line 33 of the memory cells MC arranged in the Y direction is X1-X2 axis or X3-.
They are arranged in line symmetry with respect to the X4 axis.

On the memory cell MC, as shown in FIGS.
As shown in, the main word line (MWL) 29 and the sub word line (SWL1) 29 are arranged. Each of the main word line 29 and the sub word line 29 has the same conductive layer (first
It is made of a high melting point metal film formed in the metal material forming step of the second layer, and is made of the same conductive layer as the intermediate conductive layer 29. That is, each of the main word line 29 and the sub word line 29 is formed in a layer between the word line (WL) 13 and the complementary data line 33. Each of the main word line 29 and the sub word line 29 has a transfer MISFET for the memory cell MC.
Intermediate conductive layer 29 connected to Qt1 and transfer MISFE
It is arranged between the intermediate conductive layer 29 connected to TQt2. The main word line 29 and the sub word line 29 are separated from each other, and the memory cell array MAY extends substantially in parallel in the X direction.

As shown in FIGS. 2A and 3 described above,
There are four main word lines 29 (4 [bi
t]), one is arranged for each memory cell MC. One main word line 29 corresponds to the memory block M shown in FIG.
Since the four memory mats MM of B extend over a total of 16 memory cell arrays MAY, the wiring width is made thicker than that of the sub word line 29 for the purpose of reducing the resistance value.

As shown in FIGS. 2A and 3 described above, the sub word line (SWL1) 29 is arranged in the Y direction in the memory cell array MAY arranged on the side close to the word driver circuit WDR of the memory mat MM. One is arranged for each arranged memory cell MC. The sub-word line 29 has a length that extends over one memory cell array MAY and is shorter than the main word line 29. Therefore, the wiring width is smaller than that of the main word line 29. Composed. As shown in FIGS. 6 and 7, in each of the main word line 29 and the sub word line 29, the reference voltage line (Vss) 13 connected to the memory cell MC is formed of the same conductive layer as the word line (WL) 13. , This reference voltage line 1
Since the conductive layer extending 3 has been used as an empty region, it is arranged using this empty region (a region where two wirings can be arranged). That is, the memory cell MC has a word line (W
L) 13 and the reference voltage line 13, a main word line 29 used in the divided word line system in the X direction and a sub word line 29 used in the double word line system.
2 word lines can be extended.

Complementary data line 33 of the memory cell MC
On the entire surface of the substrate including the above (excluding the area of the external terminal BP),
As shown in FIG. 6, a final passivation film (final protective film) 34 is formed. The final passivation film 34 has a three-layer laminated structure in which a silicon oxide film, a silicon nitride film, and a resin film are sequentially laminated, though its structure is not shown in detail.

The silicon oxide film below the final passivation film 34 has a laminated structure of three layers and has the same structure as the interlayer insulating film 30. That is, the lower silicon oxide film is a silicon oxide film deposited by a CVD method using tetraethoxysilane gas as a source gas, a silicon oxide film etched after coating, and a CVD method using a tetraethoxysilane gas as a source gas. Formed of each of the silicon oxide films. That is, the lower silicon oxide film flattens the surface and prevents the formation of cavities in the upper silicon nitride film. The intermediate silicon nitride film is formed by the plasma CVD method. The intermediate silicon nitride film has the function of increasing the moisture resistance. The upper resin film is formed of, for example, a polyimide resin. This resin film shields alpha rays emitted from a small amount of radioactive elements contained in the resin encapsulation portion of the resin encapsulation type semiconductor device, and can improve the alpha ray soft error resistance of SRAM. Further, the resin film prevents the filler contained in the resin sealing portion from causing cracks in the interlayer film such as the final passivation film 34.

Next, the well structure and the structure of the memory cell MC in the peripheral region (end portion) of the memory cell array MAY of the memory mat MM of SRAM will be described.

SR shown in FIGS. 2 (A), 3 and 4
The peripheral structure of the memory cell array MAY or the sub memory cell array SMEY of the memory mat MM of AM is shown in FIG. 9 (enlarged plan view of the peripheral region) and FIG. 10 (main part sectional view). In FIG. 9, FIG. 9A shows the planar shape of the active region whose peripheral shape is defined by the element isolation insulating film 4. FIG. 9 (B)
Shows the planar shapes of the driving MISFET Qd and the transfer MISFET Qt which are superposed on the active region. Figure 9
(C) is a load MISFET superposed on the active region, the driving MISFET Qd and the transfer MISFET Qt.
The plane shape of Qp is shown. FIG. 9D shows a sub word line (SW) superposed on the active region, the driving MISFET Qd, the transfer MISFET Qt, and the load MISFET Qp.
L) 29, main word line (MWL) 29, and complementary data line (DL) 33 are shown in plan view.

As shown in FIG. 9A, in the central area of the memory cell array MAY or the sub memory cell array SMEY, some active areas of the four memory cells MC adjacent in the X and Y directions are integrally formed. The plane shape is a ring shape. Specifically, FIG.
With the memory cell MC2 indicated by the reference numeral MC2 in (A) as the center, this memory cell MC2, the memory cell MC adjacent to the right side thereof, and the two memory cells MC adjacent to the lower side of these two memory cells MC. , Of the four memory cells MC in total, one transfer MISFET Qt and one drive MISFET Q of each of the four memory cells MC
d, the active regions of the total of four transfer MISFETs Qt and the four drive MISFETs Qd are integrally configured to form a ring-shaped active region (a partially filled region in FIG. 9A).

In other words, the above-mentioned four transfer MISFEs
TQt and each of the four driving MISFETs Qd (total 8
Each MISFET) has a source region or a drain region facing each other integrally, and is also electrically connected in series in a ring shape. That is, in the four memory cells MC adjacent to each other in the X direction and the Y direction, one transfer MISFET Qt and the driving M of the memory cell MC.
One L-shaped active region composed of the ISFET Qd is continuous with each other, and there is no termination in the direction in which the active regions extend (direction coinciding with the gate length direction of a plurality of MISFETs connected in series), The pattern of the active area is composed of a closed ring shape. The inner frame side and the outer frame side of the ring-shaped active region facing each other (transfer MISFE
Regions defining the gate widths of TQt and the driving MISFET Qd) are defined by the element isolation insulating film 4 and the p-type channel stopper region 5. The transfer MISFET Qt of each of the four memory cells MC has the gate length direction aligned with the Y direction, and the drive MISFET Qd has the gate length direction aligned with the X direction. Therefore, the ring shape is circular or elliptical. Rather, it is configured by a planar shape that is close to a rectangular shape (rectangular shape).

The active region formed in the ring shape is X
In the direction (direction matching the gate width direction of the transfer MISFET Qt or the gate length direction of the driving MISFET Qd), a plurality of shapes are arranged at the same pitch. This X
The element isolation insulating film 4 (and the p-type channel stopper region 5) is disposed between each of the plurality of ring-shaped active regions adjacent to each other in the direction, and is electrically isolated. The ring-shaped active region at the next stage adjacent to the ring-shaped active region in the Y direction (the direction matching the gate length direction of the transfer MISFET Qt or the gate width direction of the driving MISFET Qd) is
Similar to the array in the previous stage, a plurality of arrays having the same shape and the same pitch in the X direction are arranged and X
They are arranged so as to be offset by a half pitch (half pitch) in the direction. That is, the ring-shaped active region has the shape shown in FIG.
As shown in (A), the memory cell array MAY (or the sub-memory cell array SMEY) is arranged in a zigzag manner while ensuring periodicity.

As shown in FIG. 9 (A) and FIG.
Memory cell array MAY (also sub memory cell array SM
AY), that is, at the end of the memory cell array MAY and in the area close to the guard ring area P-GR arranged on the outer periphery of the memory cell array MAY,
A layout is provided to relax the periodic irregularity of the array of ring-shaped active regions. Specifically, as shown in FIGS. 9A and 10, the memory cell array MAY is provided between the memory cell array MAY and the guard ring region P-GR.
Dummy active regions 4D1-4 having the same or similar shape as a part of the ring-shaped active regions arranged in the central region of
Each of D3 is arranged.

The guard ring region P-GR surrounding the two memory cell arrays MAY of the memory mat MM shown in FIG. 4 is, as shown in FIG. 9A and FIG.
In the peripheral region of the main surface of the p − type well region 2M, the periphery is defined by the element isolation insulating film 4 (a part is the active region 4D).
(Specified by the)) area. Guard ring area P
The −GR is mainly composed of the p + type semiconductor region 40 formed on the main surface of the p − type well region 2M, and supplies a fixed reference voltage Vss to the p − type well region 2M.

The guard ring region P-GR is shown in FIG.
As shown in (D) and FIG. 10, the reference voltage line (Vss) 2
The reference voltage line (Vss) 33 is electrically connected via the line 9. The reference voltage line 29 is the main word line (MW
L) 29, sub-word line (SWL) 29, etc. are formed of the same conductive layer and extend along the periphery of the memory cell array MAY. The reference voltage line 29 is connected to the guard ring region P-GR through a connection hole 28 formed in the interlayer insulating film 27. The reference voltage line 33 is formed of the same conductive layer as the complementary data line (DL) 33. Since the complementary data line 33 extends in the Y direction in the memory cell array MAY, the reference voltage line 33 extends in the Y direction to avoid contact with the complementary data line 33. The reference voltage line 33 is connected to the reference voltage line 29 in the lower layer through a connection hole 31 formed in the interlayer insulating film 30.

As shown in FIGS. 9 and 10, the memory cell array MAY basically has the n-type well isolation region 3.
is arranged on the main surface of the p − -type well region 2M on the main surface of i,
An n-type well region 3 is formed on the outer periphery of the p-type well region 2M in which the memory cell array MAY is arranged and on the main surface of the n-type well isolation region 3i. The n-type well region 3 arranged on the main surface of the n-type well isolation region 3i has a higher impurity concentration than that of the surface of the n-type well isolation region 3i as shown in FIG. Therefore, the impurity concentration of the main surface of the n-type well isolation region 3i can be set high (correction can be made to increase the impurity concentration). In other words, the n-type well isolation region 3i
The impurity concentration of the n-type well region 3 is added to the main surface of the outer peripheral portion of the p-type well region 2M, which is set to a high impurity concentration. As a result, the p-type well regions 2M and n-of the main surface of the n-type well isolation region 3i in the double well structure are formed.
It is possible to improve the dielectric isolation breakdown voltage between the p-type semiconductor substrate 1 and the outer periphery of the type well isolation region 3i.

As shown in FIG. 9 (A) and FIG.
A guard ring region N is formed in the peripheral region of the n-type well region 3.
-GR is placed. The guard ring region N-GR is n
In the peripheral region of the main surface of the -type well region 3, the region is defined by the element isolation insulating film 4. The guard ring region N-GR is mainly composed of the n + type semiconductor regions 11 and 18 formed in the main surface portion of the n- type well region 3 and supplies a fixed power supply voltage Vcc to the n- type well region 3. .

The guard ring region N-GR is shown in FIG.
(D) and as shown in FIG. 10, the power supply voltage line (Vcc) 2
The power supply voltage line (Vcc) 33 is electrically connected via the line 9. The power supply voltage line 29 is formed of the same conductive layer as the reference voltage line 29, and the power supply voltage line 33 is formed of the same conductive layer as the reference voltage line 33.

Further, as shown in FIG. 9B, in the memory cell array MAY, dummy gate electrodes 7D are arranged in order to reduce the disturbance of the periodicity at the end. The dummy gate electrode 7D is arranged at the end portion of the memory cell array MAY and has the same or similar plane shape as the plane shape of the gate electrode 7 of the driving MISFET Qd of the memory cell MC arranged in the central region of the memory cell array MAY. Configured. Similarly, in order to reduce the disturbance of the periodicity at the end of the memory cell array MAY, the dummy word line 13
Each of D1 and the dummy reference voltage line 13D2 is arranged.
The dummy word line 13D1 and the dummy reference voltage line 13D
2 are arranged at the ends of the memory cell array MAY, and are configured to have the same or similar planar shape as the planar shape of the word line 13 and the reference voltage line 13 arranged in the central region of the memory cell array MAY. It

Next, FIG. 11 shows the specific structure of the complementary MISFET which constitutes the peripheral circuit of the SRAM described above.
A brief description will be given using (enlarged cross-sectional view of a main part).

As shown in FIG. 11, the complementary MISFET of the peripheral circuit including the direct peripheral circuit and the indirect peripheral circuit of the SRAM has the p-type well region 2 and the n-type well region 2 on the main surface of the p-type semiconductor substrate 1 as shown in FIG. It is arranged in the mold well region 3. That is,
The complementary MISFET of the peripheral circuit has an n-type well region 2M in which the memory cell array MAY is arranged.
The p-type well region 2 and the n-type well region 3 are arranged around the outer periphery of the -type well isolation region 3i.

Of the complementary MISFETs, the n-channel MISFET Qn is the element isolation insulating film 4 in the inactive region.
And in the region surrounded by the p-type channel stopper region 5 on the main surface of the p-type well region 2.
That is, the n-channel MISFET Qn is mainly composed of the p-type well region 2 (channel forming region), the gate insulating film 12, the gate electrode 13, the source region and the drain region. The n-channel MISFET Qn is the memory cell M.
The gate electrode 13 of the n-channel MISFET Qn is formed of the same conductive layer as the gate electrode 13 of the transfer MISFET Qt. Similarly, the n-channel MISFETQ
n has an LDD structure, and each of the source region and the drain region is composed of an n-type semiconductor region 17 having a low impurity concentration and an n + -type semiconductor region 18 having a high impurity concentration.

In the n-channel MISFET Qn, a wiring 29 or a wiring 33 is electrically connected to the n + type semiconductor region 18 of at least one of the source region and the drain region through the wiring 29.

Of the complementary MISFETs, p
The channel MISFET Qp is arranged on the main surface of the n--type well region 3 in the region surrounded by the element isolation insulating film 4 in the inactive region. That is, p-channel MIS
The FET Qp mainly includes an n-type well region 3 (channel forming region), a gate insulating film 12, a gate electrode 13, a source region and a drain region. p channel MI
Although the SFET Qp has a different channel conductivity type, it has substantially the same structure as the n-channel MISFET Qn.
That is, the p-channel MISFET Qp has an LDD structure, and the source region and the drain region each have a low impurity concentration p-type semiconductor region 39 and a high impurity concentration n +.
It is composed of the type semiconductor region 40.

In the p-channel MISFET Qp, the wiring 29 or the wiring 33 is electrically connected to the p + type semiconductor region 40 of at least one of the source region and the drain region through the wiring 29.

The transfer MISFET Qt and the drive MI of the memory cell MC of the SRAM memory cell array MAY.
P-type well region 2M in which each of SFETQd is arranged
Is the n-channel MISF of the complementary MISFET of the peripheral circuit
The impurity concentration on the surface is set independently of the impurity concentration on the surface of p @-type well region 2 in which ETQn is arranged.
That is, the impurity concentration on the surface of the p-type well region 2M is
The impurity concentration on the surface of the p-type well region 2 can be set to be equal to or higher than that, and as a result, the memory cell M can be set.
C transfer MISFETQt, drive MISFETQd
The threshold voltage of each can be raised. This memory cell M
C transfer MISFETQt, drive MISFETQd
If each of the threshold voltages can be set high, malfunction due to noise can be prevented, so that the information held in the information storage node of the memory cell MC can be stably held.

The impurity concentration on the surface of the p-type well region 2 in which the n-channel MISFETQn is arranged is determined by the transfer MISFETQt and the driving MIS of the memory cell MC.
The impurity concentration of the surface is set independently of the impurity concentration of the p-type well region 2M in which each of the FETs Qd is arranged. That is, the impurity concentration on the surface of the p-type well region 2 can be set to be equal to or lower than the impurity concentration on the surface of the p-type well region 2M, and as a result, the threshold voltage of the n-channel MISFET Qn can be set. Can be lowered. If the threshold voltage of the n-channel MISFETQn can be set low, the operating speed of the n-channel MISFETQn can be increased.

Next, regarding a specific method of manufacturing the above-described SRAM, FIG. 14 (a cross-sectional view of an essential part showing each step in the central region of the memory cell array) and FIG. 15 (each step at the end of the memory cell array). A brief description will be given with reference to the cross-sectional view of the main part shown).

<< Step of Forming Well Separation Region >> First, the p--type semiconductor substrate 1 made of single crystal silicon is prepared (FIG. 14).
(A) and FIG. 15 (A)). As described above, the p − type semiconductor substrate 1 has the main surface set to the (100) crystal plane, and a so-called off-angle wafer is used.

Next, a silicon oxide film 50 is formed on the main surface of the p--type semiconductor substrate 1. The silicon oxide film 50 is formed by, for example, a thermal oxidation method and has a film thickness of about 20 to 25 [nm].

Next, as shown in FIGS. 14A and 15A, the silicon oxide film 50 is formed on the main surface of the formation region of the n--type well isolation region 3i of the p--type semiconductor substrate 1. A silicon nitride film 51 is formed through. This silicon nitride film 51 is used as an oxidation resistant mask. The silicon nitride film 51 is deposited by, for example, a CVD method and is formed to have a film thickness of about 40 to 60 [nm]. The silicon nitride film is patterned by an etching technique using a mask formed by a photolithography technique after the deposition.

Next, the silicon nitride film 51 is used as an oxidation resistant mask, and the region other than the silicon nitride film 51, that is, n.
In a region other than the region where the -type well isolation region 3i is formed, the silicon oxide film 50 on the main surface of the p-type semiconductor substrate 1 is grown to a thick silicon oxide film 50M. This silicon oxide film 5
0M is formed with a film thickness of, for example, about 120 to 150 [nm] for the purpose of using it as an impurity introduction mask for introducing impurities by utilizing the film thickness difference from the above-mentioned silicon oxide film 50. The silicon oxide film 50M used as the impurity introduction mask is the silicon nitride film 5 used as the oxidation resistant mask.
1 is self-aligned. After that, the silicon nitride film 51 is removed.

Next, using the silicon oxide film 50M as an impurity introduction mask, n − of the main surface of the p − type semiconductor substrate 1 is formed.
An n-type impurity is introduced into the formation region of the type well isolation region 3i, and the n-type impurity is expanded and diffused to form the n-type well isolation region 3i (FIGS. 14B and 15).
(See (B)). The n-type impurities are, for example, 10 ¹² to 10 10.
Use P with an impurity concentration of about ¹³ [atoms / cm ² ] and
It is introduced by ion implantation with an energy of about 70 [KeV]. The introduced n-type impurities are 1100 to 1300.
At a temperature of about [° C.], stretch diffusion of about 150 to 200 [min] is performed.

Next, as shown in FIGS. 14B and 15B, the silicon oxide film 50 used as the impurity introduction mask of the n-type impurity for forming the n--type well isolation region 3i.
Using M (using the same mask), a p-type impurity 2Mp is introduced into the main surface portion of the n-type well isolation region 3i. Since the p-type impurity 2Mp is introduced using the silicon oxide film 50M forming the n-type well isolation region 3i, it is formed in self-alignment with the n-type well isolation region 3i. Moreover, since the p-type impurity 2Mp is introduced by using the silicon oxide film 50M forming the n-type well isolation region 3i, the p-type impurity 2Mp also serves as an impurity introduction mask.
The step of forming an impurity introduction mask formed only for introducing p can be eliminated. The p-type impurity 2Mp forms the p-type well region 2M in which the memory cell array MAY is arranged. It is carried out by utilizing the expansion and diffusion of each.

The p-type impurity 2Mp is, for example, 10 ¹² to
BF ₂ having an impurity concentration of about 10 ¹³ [atoms / cm ² ] is used, and ion implantation is performed with an energy of about 50 to 70 [KeV].

Next, each of the silicon oxide films 50 and 50M is removed.

<< Well Forming Step >> Next, a silicon oxide film 52 is formed on the entire main surface of the p--type semiconductor substrate 1 including the main surface of the n--type well isolation region 3i. Silicon oxide film 5
2 is formed by, for example, a thermal oxidation method, and is formed with a film thickness of about 40 to 50 [nm].

Next, a region of the main surface of the n--type well isolation region 3i in which the p-type impurity 2Mp is introduced (this region is formed by the p-type impurity 2Mp during the thermal oxidation step for forming the silicon oxide film 52). Is slightly diffused to form the p-type well region 2M), and on the formation region of the p-type well region 2 on the main surface of the p-type semiconductor substrate 1 except the n-type well isolation region 3i. A silicon nitride film 53 is formed on each of them. This silicon nitride film 53 is used as an impurity introduction mask and an oxidation resistant mask. The silicon nitride film 53 is deposited by, for example, a CVD method and is formed to have a film thickness of about 40 to 60 [nm]. The silicon nitride film 53 is patterned by the etching technique using a mask formed by the photolithography technique after the deposition.

Next, as shown in FIGS. 14C and 15C, the silicon nitride film 53 is used as an impurity introduction mask to form the n--type well region 3 of the p--type semiconductor substrate 1. An n-type impurity 3n is introduced into the main surface of the region. As shown in FIG. 15C, the n-type impurity 3n is the outer periphery of the region into which the p-type impurity 2Mp is introduced (the formation region of the p-type well region 2M), and is the n-type well isolation region. 3i
It is also introduced on the main surface of. The n-type impurity 3n is, for example, 1 ×
P is used with an impurity concentration of about 10 ^{13 to} 3 × 10 ¹⁴ [atoms / cm ² ] and is introduced by ion implantation with an energy of about 120 to 130 [KeV]. The n-type impurity 3n is introduced into the main surface portion of the p-type semiconductor substrate 1 through the silicon oxide film 52.

Next, using the silicon nitride film 53 as an oxidation resistant mask, the region of the p--type semiconductor substrate 1 into which the n-type impurity 3n is introduced and the n--type well isolation region 3i of the n-type impurity 3n are introduced. In each of the formed regions, the silicon oxide film 5 is formed.
2 is grown to form a thick silicon oxide film 52M.
The growth of the silicon oxide film 52M is performed by a thermal oxidation method using the silicon nitride film 53 as an oxidation resistant mask. The silicon oxide film 52M is formed to have a film thickness of about 130 to 140 [nm]. After that, the silicon nitride film 53 is removed.

Next, as shown in FIGS. 14D and 15D, the grown silicon oxide film 52M is used as an impurity introduction mask, and the p − -type semiconductor substrate 1 is covered with p
The main surface portion of the formation region of the -type well region 2 and the main surface portion of the p-type well region 2M of the n-type well isolation region 3i are respectively p-typed.
A type impurity 2p is introduced. p-type impurity 2p is 1 × 10
BF with an impurity concentration of about ^{13 to} 3 × 10 ¹³ [atoms / cm ² ].
₂ is used and is introduced by ion implantation with an energy of about 50 to 70 [KeV]. The p-type impurity 2p is introduced into the main surface portion of each of the p--type semiconductor substrate 1 and the p--type well region 2M through the silicon oxide film 52.

Next, as shown in FIGS. 14E and 15E, n introduced into the main surface portion of the p--type semiconductor substrate 1 is introduced.
Each of the p-type impurity 3n, the p-type impurity 2p, and the p-type impurity 2Mp introduced into the main surface portion of the n-type well isolation region 3i is stretched and diffused. , P − type well region 2 is formed by diffusion of p type impurity 2p, and p − type well region 2M is formed by diffusion of p type impurity 2Mp. That is, when this process is completed, p
In the main surface of the --type semiconductor substrate 1, an n--type well isolation region 3i is formed.
And the double well structure formed by the p- type well region 2M is completed, and the n- type well region 3 and the p- type well region 2 are formed in different regions of the main surface of the p- type semiconductor substrate 1. The completed twin well structure is completed. The stretching diffusion is about 10 at a temperature of 1100 to 1300 [° C.], for example.
It is carried out for 0 to 200 minutes. After this, the silicon oxide film 5
2 is removed.

<< Device Isolation Region Forming Step >> Next, p
A silicon oxide film is formed on the entire surface of the p − type semiconductor substrate 1 including the main surfaces of the − type well region 2, the n − type well region 3 and the p − type well region 2M. This silicon oxide film is formed by a thermal oxidation method, and has a film thickness of, for example, about 15 to 20 [nm].

Then, a silicon nitride film is formed on the main surface of the active region forming regions of the p--type well region 2, n--type well region 3 and p--type well region 2M. The silicon nitride film is used as an impurity introduction mask and an oxidation resistant mask. The silicon nitride film is deposited by, for example, a CVD method,
It is formed with a film thickness of about 150 [nm]. The silicon nitride film is
Using photolithography technology and etching technology,
Patterned.

Next, when the silicon nitride film is patterned, the silicon oxide film or a part thereof is removed in the inactive region exposed from the silicon nitride film, so that the inactive region is newly oxidized. The silicon film is formed again. This newly formed silicon oxide film is formed by, for example, a thermal oxidation method,
It is formed with a film thickness of about 8 to 12 [nm]. The newly formed silicon oxide film is formed for the purpose of removing etching damage when the silicon nitride film is patterned and preventing contamination when introducing impurities.

Next, using the silicon nitride film as an impurity introduction mask, p-type impurities are added to the formation regions of the inactive regions (element isolation regions) of the p--type well region 2 and the p--type well region 2M. Introduce. The p-type impurity is, for example, 10 ¹³ to
BF ₂ having an impurity concentration of about 10 ¹⁴ [atoms / cm ² ] is used, and ion implantation is performed with energy of about 30 to 50 [KeV]. This p-type impurity is introduced into the main surface portions of the p-type well region 2 and the p-type well region 2M through the silicon oxide film. The main surface of the n-type well region 3 is covered with a mask (not shown) formed by a photolithography technique, and p-type impurities are not introduced. This mask is removed after the introduction of the p-type impurity.

Next, using the silicon nitride film as an oxidation resistant mask, on the main surface of each inactive region of the p--type well region 2, n--type well region 3 and p--type well region 2M. A silicon oxide film is grown to form the element isolation insulating film 4 (see FIGS. 14F and 15F). The element isolation insulating film 4 is formed of, for example, a silicon oxide film formed by a thermal oxidation method (selective thermal oxidation method of the substrate), and has a thickness of 400 to 500 [n.
The film thickness is about m].

When the heat treatment process for forming the element isolation insulating film 4 is performed, p-type impurities introduced into the respective inactive regions of the p-type well region 2 and the p-type well region 2M are respectively introduced. 14F and FIG.
As shown in FIG. 5 (F), p-type channel stopper region 5 is formed.

After forming the element isolation insulating film 4 and the p-type channel stopper region 5, the silicon nitride film used as the oxidation resistant mask is removed.

In the manufacturing process thereafter, the manufacturing process of the memory cell MC of the memory cell array MAY is used (there is a part of the same manufacturing process).
Therefore, the memory cell array MAY will be described mainly with reference to the drawings, and the peripheral circuits will be described without reference to the drawings, only the parts that are basically different from the manufacturing process of the memory cell array MAY.

<< Formation Step of First Gate Insulating Film >> Next, a silicon oxide film on the main surface of each active region of the p--type well region 2, n--type well region 3 and p--type well region 2M. To remove. By the step of removing the silicon oxide film, p-
The main surfaces of the active regions of the type well region 2, the n-type well region 3 and the p-type well region 2M are exposed.

Next, a new silicon oxide film is formed on the main surfaces of the active regions of the p--type well region 2, the n--type well region 3 and the p--type well region 2M. The silicon oxide film is formed mainly for the purpose of preventing contamination at the time of introducing impurities and removing the so-called white ribbon of the silicon nitride film at the end of the element isolation insulating film 4 which cannot be completely removed at the time of removing the silicon nitride film. . The silicon oxide film is formed by, for example, a thermal oxidation method and has a thickness of 18 to
It is formed with a film thickness of about 20 [nm].

Then, threshold voltage adjusting impurities are introduced into the main surface portions of the active regions of the p--type well region 2, the n--type well region 3, and the p--type well region 2M. A p-type impurity such as BF ₂ is used as the threshold voltage adjusting impurity. This BF ₂ is introduced by ion implantation and is, for example, 10 ¹² to 1 at an energy of about 40 to 50 [KeV].
The impurity concentration is about 0 ¹³ [atoms / cm ² ]. This BF ₂ is introduced into the main surface portions of the p − type well region 2, the n − type well region 3 and the p − type well region 2M through the silicon oxide film.

Next, the silicon oxide film on the main surface of each active region of the p--type well region 2, the n--type well region 3 and the p--type well region 2M is removed, and the p--type well region 2 is removed. , N
The main surfaces of the active regions of the -type well region 3 and the p-type well region 2M are exposed. Thereafter, a gate insulating film 6 is formed on the main surfaces of the active regions of the exposed p--type well region 2, n--type well region 3 and p--type well region 2M. The gate insulating film 6 is formed by a thermal oxidation method,
It is formed with a film thickness of about 5 [nm]. The gate insulating film 6 is a MIS for driving the memory cells MC of the memory cell array MAY.
It is used as the gate insulating film 6 of the FET Qd.

<< First Layer Gate Material Forming Step >> Next, a polycrystalline silicon film (7) is deposited on the entire main surface of the p--type semiconductor substrate 1 including the gate insulating film 6. This polycrystalline silicon film is formed in the first layer gate material forming step.
The polycrystalline silicon film is formed by so-called doped polysilicon, which is deposited by the CVD method, and an impurity for reducing the resistance value is introduced during the deposition. This polycrystalline silicon film is made of disilane (Si ₂
It is deposited by a CVD method using H ₆ ) and phosphine (PH ₃ ) as source gases. In the case of the present embodiment, P, which is an n-type impurity, is introduced into the polycrystalline silicon film, and P is 10 ²⁰ -1.
The impurity concentration is about 0 ²¹ [atoms / cm ³ ]. The polycrystalline silicon film is formed to have a relatively thin film thickness of about 100 [nm] when used as the gate electrode 7 of the driving MISFET Qd and the first electrode 7 of the capacitive element C in the memory cell MC. To be done. The polycrystalline silicon film is an insulator for the dielectric film (21) formed thereabove or the underlying gate insulating film (6) as long as it does not impair the operating speed when used as the gate electrode 7 of the driving MISFET Qd. The withstand voltage can be secured and the upper layer can be made flat by thinning.

After the polycrystalline silicon film formed in the gate material forming step of the first layer is formed, this polycrystalline silicon film is heat-treated. This heat treatment is performed by using, for example, nitrogen (N ₂ )
8 to 12 [min] at a temperature of 700 to 950 [° C] in gas
After that, the P introduced into the polycrystalline silicon film is activated and the quality of the film is stabilized.

Next, an insulating film (no reference numeral) is formed on the entire main surface of the p--type semiconductor substrate 1 including the polycrystalline silicon film.
To form. This insulating film electrically separates the lower polycrystalline silicon film and the upper conductive layer (13) from each other. The insulating film uses inorganic silane (SiH ₄ or SiH ₂ Cl ₂ ) as a source gas,
It is formed of a silicon oxide film deposited by a CVD method using a nitrogen oxide (N ₂ O) gas as a carrier gas. Silicon oxide film is about 8
It is deposited at a temperature of 00 [° C.]. The insulating film is, for example, 130
It is formed with a film thickness of about 160 nm.

Next, the insulating film and the polycrystalline silicon film are sequentially patterned to form a gate electrode 7 of the polycrystalline silicon film (see FIG. 14G). The patterning is performed by anisotropic etching such as RIE using a mask formed by a photolithography technique. The gate electrode 7 is configured as the gate electrode 7 of the driving MISFET Qd or the like of the memory cell MC. In addition, although not shown, the above-described FIG.
Of the memory cell array MAY shown in FIG.
D, the gate electrode 7 of the MISFET forming the peripheral circuit, etc. are also formed.

<< Step of Forming First Source Region and Drain Region >> Next, sidewall spacers 9 are formed on the sidewalls of the gate electrode 7 and the insulating film formed thereon. The sidewall spacer 9 is formed by depositing a silicon oxide film on the entire main surface of the p − type semiconductor substrate 1 including the insulating film, and etching the entire surface of the silicon oxide film by an amount corresponding to the deposited film thickness. It is formed by The silicon oxide film is deposited by a CVD method using an inorganic silane gas as a source gas as described above, and has a thickness of, for example, 140 to 160 [nm].
It is formed with a film thickness of about a certain degree. For the etching, anisotropic etching such as RIE is used.

Next, during the etching for forming the sidewall spacer 9, the main surface of the active region of the p--type well region 2M in the region other than the region where the gate electrode 7 and the sidewall spacer 9 are formed is exposed. Therefore, a silicon oxide film (no reference numeral is formed) is formed in this exposed region. This silicon oxide film is mainly used for the purpose of preventing contamination when introducing impurities, and preventing damage to the main surface of the active region due to the introduction of impurities. This silicon oxide film is formed by, for example, a thermal oxidation method and has a film thickness of about 8 to 12 [nm].

Next, as shown in FIG. 14G, the p--type semiconductor substrate 1 including the gate electrode 7 (actually the upper silicon oxide film) and the surface of the sidewall spacer 9 is formed. An insulating film 9T is formed on the entire main surface of the. The insulating film 9T is p at the open end of the sidewall spacer 9 (the end opposite to the side in contact with the side wall of the gate electrode 7 and defining the n-type impurity introduction region in the subsequent step). The impurity (semiconductor region 10, 1
The main purpose is to shift the position where damage occurs on the main surface of the p--type well region 2M when introducing the n-type impurities forming each of 1, 17, and 18). The concentration of the maximum stress generated on the main surface of the p − type well region 2M at the open end of the sidewall spacer 9 is caused by the thermal expansion of the sidewall spacer (silicon oxide film) 9 and the gate electrode (polycrystalline silicon film) 7. This is due to the volume contraction of the gate electrode 7 based on the coefficient difference. When the position where the maximum stress is concentrated and the position where the damage is caused by the introduction of impurities coincide with each other, a crystal defect occurs from the open end of the sidewall spacer 9 to the main surface of the p--type well region 2M. The insulating film 9T is C using inorganic silane gas as a source gas.
It is deposited by the VD method and is formed to have a film thickness of, for example, about 15 to 25 [nm].

Next, although not shown, the memory cell array M
In the formation regions of the AY transfer MISFET Qt, the n-channel MISFET Qn of the peripheral circuit, and the p-channel MISFET Qp (excluding the formation region of the DDD structure),
An impurity introduction mask is formed. Memory cell array MAY
8A, the impurity introduction mask is formed outside the region surrounded by the alternate long and short dash line with the reference numeral DDD in FIG. The impurity introduction mask is formed by photolithography, for example.

Next, using the impurity introduction mask (mainly the mask with the reference numeral DDD), an n-type impurity is formed in the main surface portion of the p--type well region 2M in the formation region of the driving MISFET Qd of the memory cell array MAY. To introduce. This n-type impurity forms the n-type semiconductor region 10 having a low impurity concentration in each of the source region and the drain region of the driving MISFET Qd which mainly adopts the DDD structure, and P having a high diffusion rate is used. P uses ion implantation, for example, with an energy of about 30 to 40 [KeV], 10
It is introduced at an impurity concentration of about ¹⁴ to 10 ¹⁵ [atoms / cm ² ]. When introducing P, the impurity introduction mask (DD
Together with D), the gate electrode 7, the side wall spacer 9 formed on the side wall thereof, and the insulating film 9T formed along the surface of the side wall spacer 9 are also used as an impurity introduction mask. After the introduction of P, the impurity introduction mask is removed.

Next, P as the n-type impurity is stretched and diffused to form an n-type semiconductor region 10 having a low impurity concentration as shown in FIG. In this n-type semiconductor region 10, since the sidewall spacer 9 is used as an impurity introduction mask, the amount of diffusion to the channel formation region side is regulated by the sidewall spacer 9 in the formation region of the driving MISFET Qd. That is, the n-type semiconductor region 10 can reduce the amount of diffusion toward the channel formation region side by an amount corresponding to the film thickness of the sidewall spacer 9, as compared with the case where the gate electrode 7 is used as an impurity introduction mask. The reduction of the diffusion amount to the channel formation region side is
Since the effective gate length dimension (channel length dimension) of the driving MISFET Qd can be increased, the driving MISFET Qd
The short channel effect of d can be prevented.

As described above, the n-type semiconductor region 10
The n-type impurity forming the is formed into the insulating film 9T on the surface of the sidewall spacer 9, and is introduced into the main surface portion of the p--type well region 2M by using the impurity introduction mask mainly including this insulating film 9T. .. That is, at the position where the maximum stress generated in the main surface of the p-type well region 2M at the open end of the sidewall spacer 9 is concentrated, the main surface portion of the p-type well region 2M is introduced when the n-type impurity is introduced. Displace the position where damage occurs.

<< Step of Forming Second Gate Insulating Film >> Next, the transfer MISFET Qt of the memory cell array MAY, the n-channel MISFET Qn of the peripheral circuit, and the p-channel MIS.
In each forming region of the FET Qp, a threshold voltage adjusting impurity is introduced into the main surface portion of each active region of the p--type well region 2M, the p--type well region 2 and the n--type well region 3. A p-type impurity such as BF ₂ is used as the threshold voltage adjusting impurity. BF ₂ uses ion implantation, for example, with energy of about 40 to 60 [KeV]
It is introduced at an impurity concentration of about 0 ¹² to 10 ¹³ [atoms / cm ² ]. BF ₂ is introduced into the main surface portions of the p − type well region 2M, the p − type well region 2 and the n − type well region 3 through a silicon oxide film formed on the main surface of the active region.

Next, the transfer MISFET Qt of the memory cell array MAY and the n-channel MISFE of the peripheral circuit.
In the respective formation regions of TQn and p-channel MISFETQp, the silicon oxide film on the main surface of each active region of p--type well region 2M, p--type well region 2 and n--type well region 3 is removed, and The main surface is exposed.

Next, the exposed p--type well region 2 is formed.
A gate insulating film 12 is formed on the main surface of each active region of the M, p-type well region 2 and the n-type well region 3. The gate insulating film 12 is formed by a thermal oxidation method, for example, 13 to 14
It is formed with a film thickness of about [nm]. The gate insulating film 12 is
MISFETQt for transfer of memory cell MC, n-channel MISFETQn of peripheral circuit, p-channel MISFET
Used as each gate insulating film of Qp.

<< Step of Forming Second Layer Gate Material >> Next, a polycrystalline silicon film 13A (electrode layer having a three-layer structure) is formed on the entire main surface of the p--type semiconductor substrate 1 including the gate insulating film 12. Bottom layer). This polycrystalline silicon film 13A is the second
It is formed by the gate material forming step of the first layer. The polycrystalline silicon film 13A is deposited by the CVD method using Si ₂ H ₆ and PH ₃ as the source gas, like the polycrystalline silicon film of the gate electrode 7. In the case of this embodiment, the polycrystalline silicon film 13A is
For the purpose of improving the withstand voltage of the underlying gate insulating film 13A, P is introduced at an impurity concentration of, for example, about 1 × 10 ^{20 to} 3 × 10 ²⁰ [atoms / cm ³ ]. In addition, the polycrystalline silicon film 1
3A is, for example, 30 to 50 for the purpose of flattening the upper layer.
It is formed with a thin film thickness of about [nm].

Next, the source region (10) of the driving MISFET Qd of the memory cell MC of the memory cell array MAY.
In the connection region between the upper source region and the reference voltage line (Vss, 13), the polycrystalline silicon film 13A and the gate insulating film 12 therebelow are sequentially removed to form a connection hole 14.
The connection hole 14 is formed by performing anisotropic etching such as RIE using a mask formed by photolithography. This connection hole 14 is for driving MISFETQ.
The source region of d and the reference voltage line (13) are connected to each other. After forming a clean gate insulating film 12, directly
Since the polycrystalline silicon film 13A is formed on the gate insulating film 12 and the connection hole 14 is formed after this, the mask forming the connection hole 14 does not directly contact the surface of the gate insulating film 12. That is, in the step of forming the connection hole 14, the gate insulating film 12 is not contaminated due to the formation of the mask and the peeling of the mask, so that the withstand voltage of the gate insulating film 12 does not deteriorate.

Next, p including the polycrystalline silicon film 13A is formed.
The polycrystalline silicon film 13 is formed on the entire main surface of the-type semiconductor substrate 1.
B and the refractory metal silicide film 13C are sequentially formed. The polycrystalline silicon film 13B is formed by the gate material forming step of the second layer. The polycrystalline silicon film 13B is deposited by the CVD method using Si ₂ H ₆ and PH ₃ as the source gas, like the polycrystalline silicon film of the gate electrode 7. In the case of the present embodiment, the polycrystalline silicon film 13B is directly connected to the surface of the source region (10) as the reference voltage line (13), and therefore, for the purpose of improving the contact resistance value in this connection, for example, 4 × 1
P to an impurity concentration of about 0 ^{20 to} 6 × 10 ²⁰ [atoms / cm ³ ].
Will be introduced. That is, P is introduced into the intermediate polycrystalline silicon film 13B at a higher impurity concentration than the impurity concentration of P introduced into the lower polycrystalline silicon film 13A. The polycrystalline silicon film 13B is formed with a thin film thickness of, for example, about 30 to 50 [nm] for the purpose of flattening the upper layer. The refractory metal silicide film 13C is formed in the second layer gate material forming step. A part of the refractory metal silicide film 13C is connected to the source region of the driving MISFET Qd through the connection hole 14 and the intermediate polycrystalline silicon film 13B. The refractory metal silicide film 13C is formed of WSi ₂ deposited by the CVD method or the sputtering method. WSi ₂ is a highly stable gate material in mass production. Refractory metal silicide film 13C
Has a smaller specific resistance than the polycrystalline silicon films 13A and 13B, and is formed with a relatively thin film thickness of, for example, about 80 to 100 [nm] in order to suppress the growth of the step shape of the upper layer. It

Next, an insulating film 15 is formed on the entire main surface of the p--type semiconductor substrate 1 including the refractory metal silicide film 13C. This insulating film 15 is, for example, 200 to 400 [n
The film thickness is about m]. The insulating film 15 uses, for example, organic silane (Si (OC ₂ H ₅ ) ₄ ) as a source gas, and has a high temperature (eg, 700 to 850 [° C.]) and a low pressure (eg, 1.0 [torr]) CVD method. It is formed of a silicon oxide film deposited by.

Next, as shown in FIG. 14I, the insulating film 15, the refractory metal silicide film 13C, the polycrystalline silicon film 13 are formed.
B and the polycrystalline silicon film 13A are sequentially patterned to form a gate electrode 13 having a laminated structure composed of the polycrystalline silicon films 13A and 13B and the refractory metal silicide film 13C. The gate electrode 13 is a transfer MIS of the memory cell MC.
FETQt, n-channel MISFETQn of peripheral circuit,
It is used as each gate electrode of the p-channel MISFET Qp. In the same manufacturing process as the process of forming the gate electrode 13, the word line (WL) 13 and the reference voltage line (V
ss) 13 are formed respectively. The patterning is
Using a mask formed by photolithography technology,
Anisotropic etching such as RIE is performed. Further, the dummy word line 13D1 and the like shown in FIG. 9B described above are formed by the step of forming the gate electrode 13.

<< Step of Forming Second Source Region and Drain Region >> Next, the memory cell MC of the memory cell array MAY.
Transfer MISFETQt, drive MISFETQd,
In each formation region of the n channel MISFETQn of the peripheral circuit, an n type impurity is introduced into the main surface portion of the active region of the p--type well region 2M. This n-type impurity is introduced for the purpose of forming the n-type semiconductor region (17) having a low impurity concentration of the LDD structure, and the impurity concentration gradient is set to be P gentler than As in order to weaken the electric field strength near the drain region. use. P uses ion implantation, for example 40-60
1 × 10 ^{13 to} 3 × 10 with energy of about [KeV]
It is introduced with an impurity concentration of about ¹³ [atoms / cm ² ]. P
Is a driving MI using the gate electrode 13 (actually the insulating film 15 or a mask for patterning the same) as an impurity introduction mask in the formation regions of the transfer MISFET Qt and the n-channel MISFET Qn of the memory cell MC.
In the formation region of the SFET Qd, the gate electrode 7 (actually the insulating film 9T) is used as an impurity introduction mask,
The gate electrodes 13 and 7 are introduced in a self-aligned manner.

After that, a heat treatment is performed to extend and diffuse the P to form the n-type semiconductor region 17 having a low impurity concentration (see FIG. 14J). The heat treatment is performed, for example, in argon (Ar) at a high temperature of 900 to 1000 [° C.] for about 15 to 25 [minutes]. Based on this heat treatment, in the n-type semiconductor region 17, the diffusion amount to the channel formation region side of each of the transfer MISFET Qt and the n-channel MISFET Qn increases, and the gate electrode 13 is completed after the manufacturing process is completed.
Moderately overlaps.

Next, although not shown, in the formation region of p channel MISFETQp of the peripheral circuit, p type impurities are introduced into the main surface portion of the active region of n--type well region 3.
This p-type impurity is introduced for the purpose of forming a p-type semiconductor region (39) having a low impurity concentration in the LDD structure (FIG. 11).
reference). BF ₂ is used as the p-type impurity. This BF
₂ uses ion implantation, for example, 30 to 50 [Ke
V] energy of 3 × 10 ^{12 to} 7 × 10 ¹² [atoms
/ Cm ² ]. BF ₂ is introduced in self-alignment with the gate electrode 13 using the gate electrode 13 as an impurity introduction mask. By introducing this p-type impurity, L of the p-channel MISFET Qp
Low impurity concentration p-type semiconductor region 3 forming a DD structure
9 is formed. Since the diffusion rate of p-type impurities is higher than that of n-type impurities, the p-type semiconductor region can form a sufficient overlap with the gate electrode 13 without heat treatment.

Next, the above-mentioned gate electrode 13 and insulating film 15 are formed.
Sidewall spacers 16 are formed on the respective side walls. The sidewall spacer 16 is formed by depositing a silicon oxide film on the entire main surface of the p − type semiconductor substrate 1 including the insulating film 15, and etching the entire surface of the silicon oxide film by an amount corresponding to the deposited film thickness. It is formed by The silicon oxide film is deposited by a CVD method using an inorganic silane gas as a source gas as described above, and is, for example, 250 to 300 [nm].
It is formed with a film thickness of about. For the etching, anisotropic etching such as RIE is used.

Next, at the time of etching for forming the sidewall spacers 16, the p--type well regions 2M, p--type well regions 2, n-- in the regions other than the regions where the gate electrodes 13 and the sidewall spacers 16 are formed. Type well region 3
Since the main surface of each active region is exposed, a silicon oxide film (no reference numeral is formed) is formed on the entire main surface of p--type semiconductor substrate 1 including the exposed region. This silicon oxide film is formed along the surface of the sidewall spacer 16 as in the above-described insulating film 9T. The silicon oxide film is used for the purpose of preventing contamination when introducing impurities and preventing damage to the main surface of the active region due to the introduction of impurities. Further, this silicon oxide film is formed in the p-type well region 2 at the open end of the sidewall spacer 16 like the insulating film 9T.
The position of the region of damage generated when the impurities (the respective impurities forming the semiconductor regions 18 and 40 respectively) introduced in the subsequent step are introduced with respect to the position of the maximum stress concentration on the main surface of M. Also used for the purpose of shifting. The silicon oxide film is formed by, for example, a thermal oxidation method and has a film thickness of about 10 to 20 [nm].

Next, the transfer MISFET Qt and the drive MISFET of the memory cell MC of the memory cell array MAY.
In each of the formation regions of Qd and the n-channel MISFET Qn of the peripheral circuit, an n-type impurity is introduced into the main surface portion of each active region of the p-type well region 2M and the p-type well region 2. As the n-type impurity, As having a slower diffusion rate than P is used for the purpose of making the pn junction depth shallow. As is ion-implanted and is introduced with an energy of about 30 to 50 [KeV] and an impurity concentration of about 1 × 10 ^{15 to} 5 × 10 ¹⁵ [atoms / cm ² ]. This As is the gate electrode 7,
13, side wall spacers 9 and 16 and insulating film 9T
Etc. are used as an impurity introduction mask, and they are introduced in self-alignment with respect to them.

Thereafter, heat treatment is performed to stretch and diffuse the n-type impurities to form n + -type semiconductor regions 11 and 18 having high impurity concentrations, respectively, as shown in FIG. The heat treatment is, for example, 800 to 900 in nitrogen gas.
It is carried out at a high temperature of [° C] for about 15 to 20 minutes. N +
Each of the type semiconductor regions 11 and 18 is used as a source region and a drain region.

By the step of forming the n + type semiconductor region 11, the driving MISFET Qd adopting the DDD structure of the memory cell MC is completed, and by the step of forming the n + type semiconductor region 18, the transfer adopting the LDD structure is performed. For MIS
FETQt is completed. Further, the n-channel MISFET Qn adopting the LDD structure of the peripheral circuit is completed by the process of forming the n + type semiconductor region 18 (see FIG. 11). Further, as shown in FIGS. 9 and 10, by forming the n + type semiconductor regions 11 and 18, the n + type semiconductor regions 11 and 18 arranged in the peripheral region of the n− type well region 3 are formed. The guard ring region N-GR is completed.

<< Third Layer Gate Material Forming Step >> Next, p
Etching the whole main surface of the -type semiconductor substrate 1,
The insulating film formed on the gate electrode 7 of the driving MISFET Qd of the memory cell MC of the memory cell array MAY is mainly removed. The removal of this insulating film is performed by the gate electrode 1
3, the insulating film 15 and the sidewall spacers 16 formed on the word line 13 and the reference voltage line 13, respectively, are used as an etching mask (the regions defined by these masks are removed). That is, the insulating film existing under each of the gate electrode 13, the word line 13, and the reference voltage line 13 remains. This removal of the insulating film is mainly performed by the drive MI which becomes the first electrode 7 of the capacitive element C of the memory cell MC.
This is performed for the purpose of exposing the surface of the gate electrode 7 of the SFET Qd. The insulating film above the gate electrode 7, that is, the first electrode 7 is formed of the silicon oxide film as described above, and
Insulating film 15 and side wall spacers 16 above
Is formed of a silicon oxide film as described above, and an etching rate difference cannot be secured, but since the insulating film 15 and the sidewall spacers 16 are formed to be thick, this insulating film 1
5 and the sidewall spacers 16 can remove only the insulating film on the first electrode 7 in a state where they remain.

Next, the gate electrode 7, that is, the first electrode 7
An insulating film 21 is formed on the entire main surface of the p- type semiconductor substrate 1 including the exposed surface of the. The insulating film 21 is mainly used as the dielectric film 21 of the capacitive element C of the memory cell MC. The insulating film 21 is formed of, for example, a silicon oxide film deposited by a CVD method using inorganic silane as a source gas. The first electrode 7 of the capacitive element C is a CV whose source gas is Si ₂ H _6.
The insulating film 21 is deposited by the D method and can flatten the surface.
The withstand voltage can be improved, and as a result, the film thickness of the insulating film 21 can be reduced. Further, since the insulating film 21 is formed of a single-layer silicon oxide film, it can be formed with a thin film thickness, for example, 40 to 50.
It is formed with a thin film thickness of about [nm].

Next, transfer MISFE of the memory cell MC
On one semiconductor region (18) and the other semiconductor region (18) of TQt, the insulating film 21 and the underlying insulating film are removed to form a connection hole 22 (FIG. 14 (K)).
reference). The connection hole 22 formed on one semiconductor region of the transfer MISFET Qt includes the one semiconductor region, the drain region (11) of the driving MISFET Qd, the gate electrode 7, and the second electrode (23) of the capacitor C, respectively. Are formed for the purpose of connecting (the connection points of the four elements of the memory cell MC). The connection hole 22 formed on the other semiconductor region of the transfer MISFET Qt is
It is formed for the purpose of connecting each of the intermediate conductive layers (23). The connection hole 22 formed in the latter insulating film 22 is
The gate electrode 1 is more than the side wall spacer 16 provided on the side wall of the gate electrode 13 of the transfer MISFET Qt.
It is formed with a large opening size on the 3 side. That is, the surface of the sidewall spacer 16 is exposed in the connection hole 22 formed in the insulating film 21, and the opening size of the substantial connection hole 22 on the other semiconductor region (18) is defined by the sidewall spacer 16. To be done. Therefore, since the sidewall spacer 16 is formed in self-alignment with the gate electrode 13, the opening position of the contact hole 22 on the gate electrode 13 side is substantially defined in self-alignment with the gate electrode 13. To be done. For the connection hole 22, a mask formed by a photolithography technique (in FIG. 14K, reference numeral 22M is attached and a part of the mask is shown by a broken line) is used, and the insulating film 21 is formed by anisotropic etching such as RIE. It is formed by removing. Further, since the insulating film 21 has a thin film thickness as described above, the connection hole 22 may be formed by using isotropic etching.

Next, using the above-mentioned mask in which the connection hole 22 is formed (the mask indicated by the broken line 22M in FIG. 14K) and shown in the area defined by the mask (the above-mentioned mask). 14 (K), by introducing an n-type impurity into the main surface portion of the p − -type semiconductor substrate 1 at substantially the same pattern and substantially the same position as the connection hole 22.
An n + type semiconductor region 21N is formed. The n + type semiconductor region 21N is formed to a depth such that crystal defects generated from the main surface of the p − type semiconductor substrate 1 can be captured at the opening end of the connection hole 22. The n-type impurity forming the n + -type semiconductor region 21N has, for example, P whose diffusion rate is faster than that of As.
Is used for ion implantation with an impurity concentration of about 10 ¹⁴ to 10 ¹⁵ [atoms / cm ² ] and an energy of about 120 to 130 [KeV]. The above-mentioned transfer MISFET Qt
N + type semiconductor region 18 of drive n of drive MISFET Qd
The junction depth of each + type semiconductor region 11 is about 0.2 to 0.3.
It is formed in the order of [μm]. On the other hand, the n + type semiconductor region 21N formed under the above conditions has a deeper junction depth than the n + type semiconductor regions 11 and 18, respectively, for example, about 0.3 to 0. It is formed with a junction depth of about 0.4 [μm].

Since the n + type semiconductor region 21N is formed by using the mask (22M) for forming the contact hole 22 in the insulating film 21, another mask other than the mask for forming the contact hole 22 is used. Since it is not necessary to form it, the number of manufacturing process steps can be reduced.

In the connection hole 22, the n-type transfer MISFET Qt is formed on the main surface of the p--type semiconductor substrate 1.
In addition to the + type semiconductor region 18 and the n + type semiconductor region 11 of the driving MISFET Qd, an n + type semiconductor region 21
N is added to the n + type semiconductor regions 11, 18 and 21N.
Since the impurity concentration of the synthesized surface can be increased, the contact resistance value with the conductive layer 23 formed in a later step can be reduced. In other words, the conductive layer 23 is formed of a polycrystalline silicon film, and the n-type impurity is introduced into the polycrystalline silicon film to the saturation region or to a degree close to the saturation region. The impurity concentration of can be reduced. If the impurity concentration of the n-type impurities introduced into the conductive layer 23 can be reduced, the flow-out (diffusion) of the n-type impurities from the conductive layer 23 to the p-type semiconductor substrate 1 side can be reduced.
N-type semiconductor region (LD with low impurity concentration of SFET Qt
The D part 17 is converted into a region having a high impurity concentration (apparently, the n-type semiconductor region 17 has a high impurity concentration n).
(Eating by the + type semiconductor region 18) can be prevented.

In the n + type semiconductor region 21N, after the insulating film 21 is formed, the mask (22M) is formed, and before the connection hole 22 is formed, an n type impurity is passed through the insulating film 21. You may form by introducing.
In this case, as described above, the number of steps of the manufacturing process can be reduced, and the insulating film 21 can be introduced when the n-type impurity is introduced.
Is present, the contamination due to the introduction of the n-type impurity can be prevented, and the main surface of the p- type semiconductor substrate 1 (actually, the main surface of the n + type semiconductor regions 11 and 18) is damaged. Can be prevented.

Then, a polycrystalline silicon film (23) is deposited on the entire main surface of the p--type semiconductor substrate 1 including the insulating film 21 serving as the dielectric film (see FIG. 14L). This polycrystalline silicon film is formed in the gate material forming step of the third layer. A part of the polycrystalline silicon film is connected to the one semiconductor region (18) of the transfer MISFET Qt, the drain region (11) of the driving MISFET Qd, and the gate electrode 7 through the connection hole 22. This polycrystalline silicon film is a load MISF
It is used as the gate electrode (23) of the ETQp, the second electrode (23) of the capacitive element C, the conductive layer (23), and the intermediate conductive layer (23). In particular, the polycrystalline silicon film is used as the gate electrode (23) of the load MISFET Qp and the capacitive element C.
Since it is used as the second electrode (23) of (3), it is deposited by the CVD method using Si ₂ H ₆ and PH ₃ as the source gas in the same manner as described above (doped polysilicon). The deposition temperature of the polycrystalline silicon film by the CVD method is set to about 680 to 720 [° C.]. The polycrystalline silicon film is formed with a thin film thickness of, for example, about 60 to 80 [nm] in order to suppress the growth of the step shape of the upper layer, and has a P concentration of about 10 ²⁰ to 10 ²¹ [atoms / cm ³ ]. Will be introduced.

Next, the polycrystalline silicon film is patterned to form the gate electrode 23 of the load MISFET Qp, the second electrode 23 of the capacitive element C, the conductive layer 23, and the intermediate conductive layer 23.
Form each of. This polycrystalline silicon film is patterned by using a mask formed by, for example, a photolithography technique and performing anisotropic etching such as RIE.

By the step of forming the second electrode 23,
The capacitive element C in which the first electrode 7, the dielectric film 21, and the second electrode 23 are sequentially laminated is completed.

Next, the gate electrode 23 of the load MISFET Qp, the second electrode 23 of the capacitive element C, the conductive layer 23,
Each surface of the intermediate conductive layer 23 is subjected to thermal oxidation treatment to form a silicon oxide film 24G on each surface (see FIG. 14L). The thermal oxidation treatment is performed in an oxygen gas atmosphere (O ₂ dry) of 800 to 900 ° C. for about 15 to 25 minutes, and the silicon oxide film 24G has a thickness of about 5 to 15 nm as described above. Formed in thickness. Due to the formation of the silicon oxide film 24G, the corner portions of the respective surfaces of the gate electrode 23, the second electrode 23 of the capacitive element C, the conductive layer 23, and the intermediate conductive layer 23 (see FIG.
The cross-sectional shape of the corner portion 23C shown in 2) can be improved. In the SRAM of this embodiment, this silicon oxide film 24G is used for the load MISFET Qp formed in a later step.
It is also used as a gate insulating film (24).

<< Step of Forming Third Source Region and Drain Region >> Next, in the formation region of the p-channel MISFET Qp of the peripheral circuit, p-type impurities are introduced into the main surface portion of the active region of the n--type well region 3 (see FIG. 11). BF ₂ is used as the p-type impurity. BF ₂ uses ion implantation and is 2 × with energy of, for example, about 50 to 70 [KeV].
The impurity concentration is about 10 ^{15 to} 6 × 10 ¹⁵ [atoms / cm ² ]. BF ₂ is introduced in self-alignment with the gate electrode 13 and the sidewall spacer 16 using the gate electrode 13 and the sidewall spacer 16 as an impurity introduction mask. By introducing this p-type impurity, the p + -type semiconductor region 40 having a high impurity concentration is formed, and the p-channel MISFET Qp adopting the LDD structure of the peripheral circuit is completed.

The p + type semiconductor region 40 is the outer periphery of the memory cell array MAY and is located in the p − type well region 2.
Also formed on the main surface of the peripheral region of M, this p + type semiconductor region 40 forms a guard ring region P-GR (FIG. 1).
0).

Next, as shown in FIG. 14L, sidewall spacers are provided on the side walls of the gate electrode 23 of the load MISFET Qp, the second electrode 23 of the capacitive element C, the conductive layer 23, and the intermediate conductive layer 23, respectively. (Indicated by reference numeral 24S in FIG. 12) are formed. The side wall spacer 24S includes the gate electrode 23 and the second electrode 23.
The steep step shape of the side wall is relaxed to flatten the upper layer (especially, the channel forming region 26N of the load MISFET Qp).
Is formed for the purpose of flattening the fourth-layer gate material including the above. The side wall spacer 24S is the gate electrode 2
3, a silicon oxide film is deposited on the entire main surface of the p − type semiconductor substrate 1 including the upper layer of No. 3, and the amount corresponding to the deposited film thickness is R
It is formed by performing anisotropic etching such as IE. The silicon oxide film of the sidewall spacer 24S is deposited by, for example, a CVD method using inorganic silane as a source gas,
It is deposited with a film thickness of about 120 [nm].

Further, in the SRAM of this embodiment, the cross section of the corner portion 23C on the surface of each of the gate electrode 23 of the load MISFET Qp, the second electrode 23 of the capacitive element C, the conductive layer 23, and the intermediate conductive layer 23 described above. The step of forming the silicon oxide film 24G for improving the shape is performed by the sidewall spacer 24S.
It may be performed after the formation of.

<< Step of Forming Third Gate Insulating Film >> Next, on the main surface of the p--type semiconductor substrate 1 including the upper portions of the gate electrode 23, the second electrode 23, the conductive layer 23, and the intermediate conductive layer 23, respectively. An insulating film 24 is formed on the entire surface of the. The insulating film 24 includes a conductive layer such as the lower gate electrode 23 and an upper conductive layer (2
Each of 6) is electrically separated and the load MIS
It is used as the gate insulating film 24 of the FET Qp. The insulating film 24 is formed of a silicon oxide film deposited by a CVD method using an inorganic silane gas as a source gas, like the dielectric film 21 of the capacitive element C described above. The insulating film 24 has, for example, 50 to 70 [n] for the purpose of ensuring the withstand voltage and ensuring the conduction characteristic (ON characteristic) of the load MISFET Qp.
The film thickness is about m].

<< Fourth Layer Gate Material Forming Step >> Next, a connection hole 25 is formed in the insulating film 24 above the conductive layer 23 of the memory cell MC of the memory cell array MAY. The connection holes 25 are formed by the lower conductive layer 23 and the upper conductive layer (2
6. Actually, it is formed for the purpose of connecting each of the n-type channel forming regions 26N) of the load MISFET Qp.

Next, a polycrystalline silicon film is formed on the entire surface including the insulating film 24. This polycrystalline silicon film is formed by the gate material forming step of the fourth layer. The polycrystalline silicon film serves as an n-type channel forming region (26
N), source region (26P), power supply voltage line (Vcc: 26)
Form each of P). The polycrystalline silicon film is different from the above-mentioned polycrystalline silicon films (7, 13A, 13B and 23, respectively).
It is formed of so-called non-doped polysilicon deposited by a CVD method using Si ₂ H ₆ as a source gas. This polycrystalline silicon film is formed with a thin film thickness of, for example, about 30 to 50 nm. That is, the polycrystalline silicon film is formed with a film thickness larger than the film thickness of the crystal grains that does not affect the uniformity of the film thickness and smaller than the film thickness that can reduce the leakage current of the load MISFET Qp. It is formed.

<< Formation Step of Fourth Source Region and Drain Region >> Next, although not shown, the polycrystalline silicon film (26) is formed.
An insulating film is formed thereover. This insulating film is formed for the purpose of preventing contamination that occurs when impurities are introduced in a later step and mitigating surface damage. The insulating film is formed of, for example, a silicon oxide film formed by a thermal oxidation method, and has a thin film thickness of about 4 to 6 [nm]. Further, since this insulating film is formed by using a thermal oxidation method using an oxygen gas atmosphere, oxygen in the oxygen gas atmosphere is bonded to a dangling bond of silicon in the polycrystalline silicon film, This dangling bond can be reduced. By reducing the dangling bonds, the amount of current flowing between the source region and the drain region of the load MISFET Qp can be increased, and the current of the load MISFET Qp-
The voltage characteristics can be improved.

Next, a threshold voltage adjusting impurity is introduced into the entire surface of the polycrystalline silicon film. An n-type impurity such as P is used as the threshold voltage adjusting impurity. P is for load M
It is introduced for the purpose of enhancing the threshold voltage of ISFET Qp. The enhancement type threshold voltage is obtained with an impurity concentration of about 10 ¹⁷ to 10 ¹⁸ [atoms / cm ³ ]. Therefore, P uses ion implantation and has an energy of about 20 to 40 [KeV] and is about 10 ¹² to
It is introduced with an impurity concentration of about 10 ¹³ [atoms / cm ² ].
The impurity concentration of P introduced into the polycrystalline silicon film is 10 ¹⁸ [at
oms / cm ³ ], the polycrystalline silicon film acts as a high resistance element because the threshold voltage rises (becomes larger in absolute value). That is, the load MISFET Qp has the n-type channel formation region (2
Since the power supply voltage Vcc can be supplied to the information storage node region of the memory cell MC only in a current corresponding to the leakage current in 6N), the information retention characteristic deteriorates. Further, when the impurity concentration of P introduced into the polycrystalline silicon film is further increased and the threshold voltage is increased, the amount of leak current increases. This increase in leak current hinders power consumption. An n-type channel formation region 26N is formed by the step of introducing the threshold voltage adjusting impurities (see FIG. 14M).

Next, the source region (26 of the load MISFET Qp of the memory cell MC of the memory cell array MAY).
In the formation region of P) and the formation region of the power supply voltage line (Vcc: 26P), p-type impurities are introduced into the polycrystalline silicon film (26). As the p-type impurity, for example, BF ₂ is used, and is introduced into the region surrounded by the alternate long and short dash line with reference numeral 26P in FIGS. 7 and 8B. This BF ₂ is introduced by ion implantation, for example, with an energy of about 20 to 40 [KeV] and an impurity concentration of about 10 ¹⁴ to 10 ¹⁵ [atoms / cm ² ]. A mask formed by a photolithography technique is used for introducing the p-type impurity.

Next, the silicon oxide film formed on the surface of the polycrystalline silicon film (26) is removed. The stepped shape of the underlying layer is transmitted to the surface of the polycrystalline silicon film formed on the surface of the underlying insulating film (gate insulating film) 24 having the stepped shape. The silicon oxide film formed on the surface of the polycrystalline silicon film to which the step shape has been transferred can be removed by anisotropic etching in the flat area, but the film thickness in the step area becomes apparently thick. However, it cannot be removed by anisotropic etching. Therefore, the silicon oxide film formed on the surface of the polycrystalline silicon film is isotropically etched for the purpose of removing both the flat region and the step region. To be done. If it is not removed by isotropic etching, the silicon oxide film is not removed in the step region, and this silicon oxide film serves as an etching mask to form the polycrystalline silicon film in the patterning step of the lower polycrystalline silicon film. Etching residue occurs.

Next, as shown in FIG. 14M, the polycrystalline silicon film is patterned to form an n-type channel forming region 26N, a source region 26P and a power supply voltage line 26P. The patterning of the polycrystalline silicon film is performed by anisotropic etching such as RIE using a mask formed by photolithography, for example. When the n-type channel forming region 26N and the source region 26P are formed, the load MISFET Qp of the memory cell MC is completed. Also, with the completion of this load MISFET Qp,
The memory cell MC is completed.

<< First Layer Metal Wiring Forming Step >> Next, an interlayer insulating film 27 is formed on the entire surface including the memory cell MC. The interlayer insulating film 27 is formed of the silicon oxide film 27A and the BPSG film 2
7B, each of which has a laminated structure of two layers.

The lower silicon oxide film 27A is formed of the upper BPSG film.
It is formed for the purpose of preventing leakage of B and P contained in the film 27B to the lower layer side. The silicon oxide film 27A uses, for example, Si (OC ₂ H ₅ ) ₄ as a source gas, and has a high temperature (for example, 600 to 800 [° C.]) and a low pressure (for example, 1.0 [tor].
r]) is deposited by the CVD method. The silicon oxide film 27A is formed with a film thickness of, for example, about 140 to 160 [nm].

The upper BPSG film 27B is formed for the purpose of flattening the surface and suppressing the growth of the step shape of the upper layer. B
The PSG film 27B is mainly deposited by a CVD method using an inorganic silane (for example, SiH ₄ ) as a source gas. BPSG film 2
7B is deposited with a film thickness of, for example, about 280 to 320 [nm], and then glass flow is performed to flatten the surface. The glass flow is, for example, 800 to 900 [° C] in nitrogen gas.
At a high temperature of about 10 minutes.

Next, a connection hole 28 is formed in the interlayer insulating film 27. The connection hole 28 is formed on the intermediate conductive layer 23 formed on the other semiconductor region (18) of the transfer MISFET Qt of the memory cell MC in the memory cell array MAY. Further, the connection hole 28 is formed in the peripheral region of the memory cell array MAY, that is, in the upper part of the p + type semiconductor region 40 of the guard ring region P-GR, in the guard ring region N-G.
The n + type semiconductor regions 11 and 18 of R are also formed on the respective upper portions. The connection hole 28 is formed by anisotropic etching such as RIE using a mask formed by photolithography.

Next, a refractory metal film 29 is formed on the entire surface including the interlayer insulating film 27. The refractory metal film 29 is the first
It is formed in the metal wiring forming process of the first layer. The refractory metal film 29 is formed of, for example, a W film deposited by a sputtering method.
When deposited by the CVD method, the W film has good step coverage in the step-shaped portion, but is easily peeled off from the surface of the interlayer insulating film 27. The W film deposited by the sputtering method has an advantage that it has high adhesiveness on the surface of the interlayer insulating film 27, but has a drawback that step coverage is poor and, if the film thickness is large, internal stress increases. Therefore, the SRAM of this embodiment
Takes advantage of the high adhesiveness of the W film, flattens the surface of the interlayer insulating film 27 underlying the W film (steps of glass flow using the BPSG film 27B), and copes with the step coverage of the W film. Deal with internal stress by making it thinner. The W film is formed as a thin metal wiring with a film thickness of, for example, about 280 to 320 [nm].

Next, as shown in FIG. 14N, the refractory metal film 29 is patterned to form a main word line (MWL) 29 in the memory cell array MAY.
The sub-word line (SWL) 29 and the intermediate conductive layer 29 are formed respectively. A part of the intermediate conductive layer 29 is connected to the lower intermediate conductive layer 23 through the connection hole 28. The intermediate conductive layer 23 is connected to the other semiconductor region (18) of the transfer MISFET Qt of the memory cell MC. Further, in regions other than the memory cell array MAY, for example, in the upper part of the p + type semiconductor region 40 of the guard ring region P-GR, the reference voltage line (Vss) 29 is formed, and the n + type semiconductor of the guard ring region N-GR is formed. A power supply voltage line (Vcc) 29 is formed above the regions 11 and 18 (see FIGS. 10 and 9D). The refractory metal film 29 is patterned by anisotropic etching using a mask formed by photolithography, for example.

<< Step of Forming Second Layer Metal Wiring >> Next, an interlayer insulating film 30 is formed on the entire surface including the main word lines 29, the sub word lines 29, the intermediate conductive layer 29 and the like.
The interlayer insulating film 30 includes a silicon oxide film 30A and a silicon oxide film 30.
B and the silicon oxide film 30C are sequentially laminated to form a three-layer laminated structure.

The lower silicon oxide film 30A is deposited by the plasma CVD method using tetraethoxysilane gas (TEOS: Si (OC ₂ H ₅ ) ₄ ) as a source gas. Silicon oxide film 3
0A can form a uniform film thickness in each of the flat portion and the step portion. For example, a concave portion (corresponding to the minimum wiring interval) between the main word line 29 and the sub word line 29 is buried and the surface thereof is covered. In the case of flattening, almost no overhang shape is generated, so a so-called nest is not generated. The silicon oxide film 30A is formed with a film thickness that is ½ or more of the minimum wiring interval, for example, about 400 to 600 [nm], for the purpose of filling the minimum wiring interval and flattening its surface. .

The silicon oxide film 30B of the intermediate layer is applied by spin-on-glass method to a film thickness of, for example, about 200 to 300 [nm], baked, and then entirely etched. The silicon oxide film 30B is mainly used for the interlayer insulating film 30.
Is formed for the purpose of flattening the surface of the. The entire surface etching is performed by using the lower conductive layer (29) and the upper conductive layer (3).
It is carried out under the condition that it is not left in the respective connection portions (inside the connection holes 31) of 3) and is left in the step portions.

Like the lower silicon oxide film 30A, the upper silicon oxide film 30C is deposited by the plasma CVD method using tetraethoxysilane gas as a source gas. The silicon oxide film 30C is formed to have a film thickness of, for example, about 300 to 500 [nm]. The silicon oxide film 30C mainly secures a film thickness necessary for insulation separation between upper and lower wiring layers as the interlayer insulating film 30, and covers the intermediate silicon oxide film 30B,
It is formed for the purpose of preventing the deterioration of the film quality of the intermediate silicon oxide film 30B.

Next, a connection hole 31 is formed in the interlayer insulating film 30. The connection hole 31 is formed by anisotropic etching such as RIE using a mask formed by photolithography, for example.

Next, as shown in FIG. 14 (O), complementary data lines (DL) 33 are formed on the interlayer insulating film 30 in the memory cell array MAY. Also, in FIG.
As shown in (D) and FIG. 10, the memory cell array MA
In the peripheral area of Y, for example, the guard ring area P-G
A reference voltage line (Vs
s) 33, the power supply voltage line (Vcc) 33 is formed on the n + type semiconductor regions 11 and 18 of the guard ring region N-GR.

The complementary data line 33 (and the wiring 33)
Is formed in the second-layer metal wiring forming process. The complementary data line 33 passes through the connection hole 31 and is connected to the lower intermediate conductive layer 29.
Connected to. The complementary data line 33 is connected to the lower metal film 3
3A, an aluminum alloy film 33B as an intermediate layer, and a metal film 33C as an upper layer are sequentially laminated to form a two-layer laminated structure. The lower metal film 33A is formed of, for example, a TiW film deposited by a sputtering method and has a film thickness of about 30 to 50 [nm]. Since the lower metal film 33A mainly functions as a barrier metal film, a film other than the TiW film,
For example, it may be formed of a TiN film or the like. The intermediate aluminum alloy film 33B is formed by sputtering, and C
It is formed of aluminum to which at least one of u and Si is added, and has a film thickness of about 700 to 900 [nm]. The upper metal film 33C is formed of, for example, a TiW film deposited by a sputtering method, and is, for example, 150 to 2
It is formed with a film thickness of about 50 [nm]. The upper metal film 33C is mainly for the purpose of preventing a diffraction phenomenon (reducing the light reflectance and preventing the halation effect) when patterning the aluminum alloy film 33B of the intermediate layer, and also for aluminum hilllock. It is formed for the purpose of preventing.

<Final Passivation Film Forming Step> Next, as shown in FIGS. 6, 10 and 11, the final passivation film 34 is formed on the entire surface including the complementary data lines 33. Although the final passivation film 34 does not show a detailed structure, a silicon oxide film, a silicon nitride film, and a resin film are sequentially laminated on each other.
It is composed of a layered structure.

The lower silicon oxide film is formed to have a laminated structure of three layers, and has the same structure as the above-described interlayer insulating film 30. That is, the lower silicon oxide film is a silicon oxide film deposited by a plasma CVD method using tetraethoxysilane gas as a source gas, a silicon oxide film that is etched after application and remains only in the step portion, and tetraethoxysilane gas as a source gas. The silicon oxide films deposited by the plasma CVD method are sequentially laminated. Each of the lower and upper silicon oxide films is a complementary data line 33.
Since it is formed after the aluminum alloy film 33B is formed, the above-mentioned CVD method that can be formed at a low temperature, for example, about 400 [° C.] or lower is used. The lower silicon oxide film is formed to have a thickness of, for example, about 400 to 600 [nm], and the intermediate silicon oxide film is formed to have a thickness of 200 to 300.
The upper silicon oxide film is formed with a film thickness of about [nm].
It is formed with a film thickness of about 00 to 900 [nm].

The intermediate silicon nitride film is formed mainly for the purpose of improving moisture resistance. The intermediate silicon nitride film is deposited by, for example, a plasma CVD method and is 1.0 to 1.4 [μm].
It is formed with a film thickness of about a certain degree.

The upper resin film is formed of, for example, a polyimide resin film, and is mainly formed for the purpose of blocking α rays.
The upper resin film is formed to have a film thickness of, for example, about 2.2 to 2.4 [μm].

When these series of manufacturing processes are performed,
The SRAM of this embodiment is completed.

According to the present invention, in the SRAM described above, the impurity concentration of the p--type well region 2M is formed in the main surface portion of the p--type well region 2M in which the memory cell array MAY of the n--type well isolation region 3i is arranged. A buried p + type semiconductor region having a higher impurity concentration than that of the above may be formed. The buried p + type semiconductor region functions as a potential barrier region for minority carriers, which improves so-called α-ray soft error resistance. In the buried p + type semiconductor region, for example, in the above-described SRAM manufacturing process, after forming the n type semiconductor region 10 shown in FIG. 14G, a mask having the memory cell array MAY opened is formed, It can be formed by using this mask and introducing a p-type impurity into the main surface portion of the p-type well region 2M.
Monovalent B is used as the p-type impurity, and 10 ¹³ [atoms / c
It is introduced by so-called high energy ion implantation of about 200 to 250 [KeV] with an impurity concentration of about m ² ]. The buried p + type semiconductor region formed under these conditions is the n + type semiconductor region 18 of the transfer MISFET Qt of the memory cell MC and the n + type semiconductor region 11 of the driving MISFET Qd.
The peak value of the impurity concentration is set in a region deeper than the peak value of the respective impurity concentrations.

Further, the present invention has a pn junction with the n + type semiconductor region 18 of the transfer MISFET Qt and the n + type semiconductor region 11 of the driving MISFET Qd, which are the information storage nodes of the memory cell MC, and a pn junction therewith. Further, similarly to them, the gate electrodes 7 and 13 may be used as the main body of the impurity introduction mask, and p-type impurities may be introduced by ion implantation to form the buried p + -type semiconductor region.

Further, in the present invention, in the SRAM,
The threshold voltage becomes high on the main surface of the n--type well region 3 formed on the outer peripheral main surface of the p--type well region 2M in which the memory cell array MAY of the n--type well isolation region 3i is arranged. Therefore, a layout in which the p-channel MISFET is not arranged is basically adopted. Further, a p-channel MISFET having a high threshold voltage may be positively arranged in this region.

The present invention also relates to the n + type semiconductor region 1 of the transfer MISFET Qt of the SRAM memory cell MC.
8, n + type semiconductor region 11 of the driving MISFET Qd,
In each connection region of the gate electrode 7 and the conductive layer 23,
The following manufacturing process may be adopted in order to reduce the occurrence of the above-mentioned crystal defects. That is, FIG. 14 (K) described above.
Forming the insulating film 21 and forming the connection hole 22, and thereafter forming the polycrystalline silicon film (23) over the entire surface of the substrate without forming the n + type semiconductor region 21N. Then, the polycrystalline silicon film is patterned to form the conductive layer 23. When the polycrystalline silicon film is subjected to the heat treatment, volumetric volume after the heat treatment occurs in the entire polycrystalline silicon film, so that stress is not concentrated only in the region of the connection hole 22.

The present invention also relates to the n + type semiconductor region 1 of the transfer MISFET Qt of the SRAM memory cell MC.
8. When each of the n + type semiconductor regions 11 of the driving MISFET Qd is stretched and diffused, the heat treatment is sufficiently performed to deepen the junction depth, and the crystal defects in the region of the connection hole 22 are n +.
It may be incorporated in each of the type semiconductor regions 11 and 18. In this case, the above-described step of forming the n + type semiconductor region 21N can be omitted.

Further, in the present invention, in the memory cell MC of the SRAM, the n-type channel forming region 26N, the p-type source region 26P and the p-type drain region 26P of the load MISFET Qp are formed as the third-layer gate material. The gate electrode 23 may be formed in the step, and the gate electrode 23 may be formed in the gate material forming step of the fourth layer. In this case, the gate material forming step of the third layer is not limited to the polycrystalline silicon film, and it suffices to form the semiconductor layer including both the single crystal silicon film and the amorphous silicon film. Similarly, the gate material forming step of the fourth layer is not limited to the polycrystalline silicon film, but includes a refractory metal film, a refractory metal silicide film,
Alternatively, a polycide film in which a refractory metal silicide film is laminated on the polycrystalline silicon film may be formed.

As described above, the SRAM of this embodiment
According to the above, the following effects can be obtained.

(1) An n--type well isolation region 3i is formed in the first region of the main surface of the p--type semiconductor substrate 1, and a p--type well is formed in the second region of the main surface of the p--type semiconductor substrate 1. The region 2 is formed, and the p − type well region 2M is formed on the main surface of the n − type well isolation region 3i. The p − type well region 2 and the p − type well region 2M are respectively formed on the main faces. In an SRAM having an n-channel MISFET, the impurity concentration on the surface of the p-type well region 2M is p-type.
The impurity concentration on the surface of the well region 2 is set to be equal to or higher than that.

With this structure, the following operational effects can be obtained. (1) The impurity concentration of the surface of the p--type well region 2M formed on the main surface of the n--type well isolation region 3i is set to be high (the impurity concentration of the surface is equal to the impurity concentration of the n--type well isolation region 3i). The lowering amount is corrected to increase the impurity concentration on the surface of the p-type well region 2M).
Since the threshold voltage of the n-channel MISFET of the memory cell MC on the main surface of the type well region 2M can be increased,
The cutoff current of the channel MISFET can be reduced, and S
The leak current of the RAM can be reduced. (2) The impurity concentration on the surface of the p-type well region 2 is set independently of the impurity concentration on the surface of the p-type well region 2M formed on the main surface of the n-type well isolation region 3i. , This p
-N-channel MIS of peripheral circuit on main surface of type well region 2
Since the threshold voltage of the FET can be lowered, the switching operation speed of the n-channel MISFET can be increased and the SRA
The circuit operation speed of M can be increased.

(2) SRA described in the means (1)
In M, p of the main surface of the n--type well isolation region 3i
-N-channel MI formed on the main surface of the well region 2M
The SFET constitutes a flip-flop circuit of the SRAM memory cell MC, and the n-channel MISFET formed on the main surface of the p-type well region 2 constitutes a peripheral circuit which directly or indirectly drives the SRAM memory cell MC. To do.

With this structure, in addition to the function and effect of the means (1), the following function and effect can be obtained. (1) Leakage of the information stored in the information storage node of the flip-flop circuit (information storage unit) of the memory cell MC is reduced, and as a result, inversion can be prevented, so that the information retention characteristic of the SRAM can be improved. (2) Since the circuit operation speed of the peripheral circuit can be increased, and both the information write operation speed and the information read operation speed of the memory cell can be increased (the access time can be increased), the SRAM circuit operation speed can be increased. Can be realized. (3) The p-type well region 2M described in the means (1) or (2) is self-aligned with the n-type well isolation region 3i.

With this structure, in addition to the function and effect of the means (1) or (2), the n-type well isolation region 3 is formed.
Since the arrangement position of the p − type well region 2M with respect to the arrangement position of i can be reduced by an amount corresponding to the mask alignment margin in the manufacturing process, a useless area on the main surface of the p − type semiconductor substrate 1 can be saved. Therefore, the integration degree of SRAM can be improved.

(4) The n--type well isolation region 3i is formed in the first region of the main surface of the p--type semiconductor substrate 1, and the p--type well is formed in the second region of the main surface of the p--type semiconductor substrate 1. In the SRAM in which the region 2 is formed and the p − type well region 2M is formed on the main surface of the n − type well isolation region 3i, the p − of the main surface of the n − type well isolation region 3i is formed.
An n-type well region 3 is formed in a region along the outer periphery of the type well region 2M.

With this structure, the impurity concentration around the outer periphery of the p--type well region 2M on the main surface of the n--type well isolation region 3i (in this portion, the impurity concentration is lowered by the deep diffusion of the n--type well isolation region 3i). Is increased in the n-type well region 3 and the depletion region extending from the pn junction between the n-type well region 3 and the p-type well region 2M into the n-type well isolation region 3i can be reduced. The junction breakdown voltage between the p-type well region 2M on the main surface of the n-type well isolation region 3i and the p-type semiconductor substrate 1 can be improved. If this junction breakdown voltage is improved, the distance between the p-type well region 2M on the main surface of the n-type well isolation region 3i and the p-type semiconductor substrate 1, that is, the main dimension of the n-type well isolation region 3i. Surface p-
Since the area occupied by the outer periphery of the type well region 2M can be reduced, useless regions on the main surface of the p-type semiconductor substrate 1 can be eliminated and the degree of integration of the SRAM can be improved.

(5) The n--type well isolation region 3i is formed in the first region of the main surface of the p--type semiconductor substrate 1, and the p--type well is formed in the second region of the main surface of the p--type semiconductor substrate 1. In the method of forming an SRAM in which the region 2 is formed and the p − type well region 2M is formed on the main surface of the n − type well isolation region 3i, the first surface is formed on the main surface of the p − type semiconductor substrate 1. Forming a first mask (50M) having an opening in one region, using the first mask (50M), introducing an n-type first impurity into the main surface of the p--type semiconductor substrate 1, and Diffusing a first impurity to form the n-type well isolation region 3i, the first mask (50M) is used, and a p-type second impurity ( 2Mp), removing the first mask (50M), A second mask having the second region opened on the main surface of the conductor substrate 1, or a second mask (52M) having the second region and the first region opened.
Forming the third impurity (2p), the second mask (52M) is used, and a p-type third impurity (2p) is introduced into the main surface of the p − -type semiconductor substrate 1. Two
Each step of diffusing each of the impurities (2 Mp) and forming each of the p--type well region 2 and the p--type well region 2M is provided.

With this structure, the following operational effects can be obtained. (1) A first mask (50) for forming an n--type well isolation region 3i in a first region of the main surface of the p--type semiconductor substrate 1.
M) is used to form the p-type well region 2M (the second mask 2Mp is introduced using the first mask 50M for introducing the first impurity), so that the p-type well region 2M is formed. Corresponding to the process of forming the mask,
The number of steps in the SRAM manufacturing process can be reduced. (2)
Using the process of diffusing the third impurity (2p) introduced into the second region of the main surface of the p − type semiconductor substrate 1 to form the p − type well region 2, the first impurity introduced into the first region is used. Since two impurities (2Mp) are diffused to form the p-type well region 2M, the number of steps in the SRAM manufacturing process is reduced by the amount corresponding to the step of diffusing the second impurity to form the p-type well region 2M. Can be reduced. (3) The p--type well region 2M formed on the main surface of the n--type well isolation region 3i in the first region of the main surface of the p--type semiconductor substrate 1 and the p--type well region 2 of the second region are formed. Since each is formed in a separate process, the p
The impurity concentrations of the − type well region 2M and the p− type well region 2 can be controlled independently. (4) The n--type well isolation region 3i is formed in the first region of the main surface of the p--type semiconductor substrate 1.
A p-type well region 2M is formed by using a first mask (50M) for forming the n-type well isolation region 3i and the p-type well region 2M. Therefore, the arrangement position of the p-type well region 2M is formed in self-alignment with the arrangement position of the n-type well isolation region 3i, and the arrangement position of the n-type well isolation region 3i is formed. p-type well region 2M
The arrangement position of can be reduced by the amount corresponding to the mask alignment margin in the manufacturing process.

(6) Load MISFETQ in which an n-type channel forming region 26N is formed on the surface of the gate electrode 23 with the gate insulating film 24 interposed therebetween and crossing the gate electrode 23.
In a method of forming an SRAM having p in a memory cell MC, a gate electrode layer (23) is deposited on the entire surface of a substrate,
The step of patterning this gate electrode layer to form the gate electrode 23, oxidizing part of the film thickness of the gate electrode 23 from its surface, and oxidizing it to a film thickness larger than that of the native silicon oxide film. Forming the silicon film 24G and relaxing the shape of the corner portion 23C of the surface of the gate electrode 23, forming the gate insulating film 24 on the surface of the gate electrode 23, upper and side surfaces of the surface of the gate electrode 23 To the gate electrode 2 with the gate insulating film 24 interposed.
3, and each of the steps of forming an n-type channel formation region 26N that crosses 3 is provided.

With this structure, the following operational effects can be obtained. (1) Load MISFETQ generated when the gate electrode layer (23) corresponding to the lower layer is patterned
The shape of the corner portion 23C of the surface of the gate electrode 23 of p is relaxed by the oxidation of the surface. (2) As a result of the action and effect (1),
Since the electric field concentration at the corner portion 23C of the surface of the gate electrode 23 below the load MISFET Qp can be reduced, the load M is reduced.
It is possible to prevent deterioration of the withstand voltage in the region of the corner portion 23C of the gate insulating film 24 of the ISFET Qp. (3) Further, as a result of the action and effect (1), the load MISFET Qp
Since it is possible to prevent the film quality from deteriorating at the corner portion 23C on the surface of the lower gate electrode 23, it is possible to prevent the breakdown voltage from degrading in the region of the corner portion 23C of the gate insulating film 24 of the load MISFET Qp.

(7) In the step of forming the gate insulating film 24 in the step described in the means (6), the surface of the gate electrode 23 is removed after the silicon oxide film 24G on the surface of the gate electrode 23 is removed. This is a step of newly forming the gate insulating film 24.

With this structure, since the gate insulating film 24 is newly formed in an independent process with respect to the silicon oxide film 24G formed on the surface of the gate electrode 23, the controllability of the film thickness of the gate insulating film 24 is improved. Can be improved.

(8) In the step of forming the gate insulating film 24 in the step described in the means (6), the silicon oxide film 24G on the surface of the gate electrode 23 in the step is used as the gate insulating film 24.
Or a composite film in which an insulating film 24F is newly deposited on the surface of the silicon oxide film 24G.
4 is a step of forming.

With this structure, in the step of forming the gate insulating film 24, the silicon oxide film 24G on the surface of the gate electrode 23 formed in the previous step is not removed. The number of steps in the manufacturing process can be reduced.

(9) Load MISFETQ in which an n-type channel forming region 26N is formed on the surface of the gate electrode 23 across the gate insulating film 24 and across the gate electrode 23.
In a method of forming an SRAM having p in a memory cell MC, a gate electrode layer (23) is deposited on the entire surface of a substrate,
This gate electrode layer is patterned to form the gate electrode 23, the sidewall spacer 24S is formed on the side surface of the gate electrode 23, and a part of the film thickness of the gate electrode 23 is oxidized from the surface thereof. , The silicon oxide film 24G having a thickness larger than that of the natural silicon oxide film
And a step of relaxing the shape of the corner portion 23C of the surface of the gate electrode 23, a step of forming a gate insulating film 24 on the surface of the gate electrode 23, and an upper surface and a side surface of the surface of the gate electrode 23. The gate insulating film 2
4, and an n-type channel forming region 26N is formed so as to cross the gate electrode 23.

With this configuration, in addition to the function and effect of the means (6), the step shape of the side surface of the gate electrode 23 of the load MISFET Qp, which occurs when the gate electrode layer 23 corresponding to the lower layer is patterned, has a side shape. It is alleviated by the wall spacer 24S.

(10) Means (6) to (10)
In the SRAM described in any one of 1, the load MISFET Qp constitutes a flip-flop circuit of the memory cell MC.

With this configuration, the load MISFETQ of the flip-flop circuit of the memory cell MC of the SRAM is formed.
In p, the gate electrode 23 and the n-type channel formation region 2
Since a short circuit with 6N (or p-type source region 26P or p-type drain region 26P) can be prevented, a standby current defect can be prevented.

(11) n of the driving MISFET Qd of the memory cell MC formed on the main surface of the p--type well region 2M
The n + type semiconductor region 1 is formed on the main surface of the + type semiconductor region 11.
SRAM to which a conductive layer 23 formed of a silicon film is connected through a connection hole 22 formed in an insulating film 21 on the first main surface of the SRAM 1.
Forming the n + type semiconductor region 11 on the main surface of the p− type well region 2M,
A step of forming an insulating film 21 on the main surface of the type semiconductor region 11, and forming a connection hole 22 on the n + type semiconductor region 11 of the insulating film 21 and a region corresponding to the inside of the connection hole 22. The n + is formed on the main surface of the p-type well region 2M.
N + type semiconductor region 2 having the same conductivity type as that of type semiconductor region 11 and having a deeper junction depth than n + type semiconductor region 11
In the step of forming 1N, a silicon film (which contacts the respective main surfaces of the n + type semiconductor region 11 and the n + type semiconductor region 21N through the contact hole 22 formed in the insulating film 21 on the entire surface of the insulating film 21 ( 23) is deposited by the CVD method, the silicon film is patterned, and the conductive layer 23 is formed.

With this structure, the following operational effects can be obtained. (1) Volume of a silicon film based on cooling after high temperature annealing during the deposition of the silicon film in the above process or high temperature annealing performed after the deposition of the silicon film (both are annealing at a temperature higher than the melting point of aluminum) A crystal defect which is generated by the contraction and which crosses the pn junction between the p @-type well region 2M and the n @ + type semiconductor region 11 from the end of the connection hole 22 of the insulating film 22 is formed in the n @ + type semiconductor region 21N. Can be taken in. (2) The mask 22M for forming the contact hole 22 in the insulating film 21 in the above step is formed on the n + type semiconductor region 2
Since it can be used also as an impurity implantation mask for forming 1N, the mask forming step can be reduced by the amount corresponding to the impurity implantation mask, and the number of steps of the SRAM manufacturing process can be reduced.

(12) n of the driving MISFET Qd of the memory cell MC formed on the main surface of the p--type well region 2M
The n + type semiconductor region 1 is formed on the main surface of the + type semiconductor region 11.
SRAM to which a conductive layer 23 formed of a silicon film is connected through a connection hole 22 formed in the insulating film 21 on the first main surface
Forming the n + type semiconductor region 11 on the main surface of the p− type well region 2M,
Forming an insulating film 21 on the main surface of the type semiconductor region 11, forming a contact hole 22 on the n + type semiconductor region 11 of the insulating film 21, and forming the insulating film 21 on the entire surface of the insulating film 21. A step of depositing a silicon film (23) in contact with the main surface of the n + type semiconductor region 11 through the connection hole 22 formed in the step, a step of performing high temperature annealing for crystallizing the silicon film, and a pattern on the silicon film. And the step of forming the conductive layer 23.

With this structure, the following operational effects can be obtained. (1) After depositing the silicon film (23) on the entire surface of the insulating film 21 in the above step, and before subjecting the silicon film in the step to patterning, the silicon film is subjected to high temperature annealing for the purpose of crystallization, The stress due to the volume contraction when the silicon film is cooled is dispersed in the entire silicon film, and is generated at the opening end of the connection hole 22 formed in the insulating film 21 on the main surface of the n + type semiconductor region 11. Since the concentration of the stress that occurs due to the volume contraction of the silicon film can be reduced, the pn junction between the p − -type semiconductor substrate 1 and the n + -type semiconductor region 11 from the opening end of the connection hole 22 of the insulating film 21 can be reduced. It is possible to prevent the occurrence of crystal defects that cross the portion. (2) The step of performing the high temperature annealing for crystallizing the silicon film in the step, which has been performed after the patterning of the silicon film in the step, is performed after the silicon film in the step is deposited. Since we only changed the silicon film before the patterning process, S
It is possible to prevent an increase in the number of steps in the RAM manufacturing process.

(13) Means (11) or Means (1)
In the SRAM described in 2), the n + type semiconductor region 11 is the drain region of the driving MISFET Qd of the flip-flop circuit of the memory cell MC of SRAM, and the conductive layer 23 is connected to the power supply voltage Vcc.

With this structure, the following operational effects can be obtained. (1) Since the leak current of the power supply supplied to the information storage node of the memory cell MC of the SRAM can be reduced,
The standby current consumption of the SRAM can be reduced.
(2) Since the leak current of the power supply supplied to the information storage node of the memory cell MC of the SRAM can be reduced, the information retention characteristic of the memory cell MC can be improved. (3) In the SRAM described in the means (11), n + is formed in the drain region of the driving MISFET Qd of the memory cell MC.
Since the type semiconductor region 21N is added, the impurity concentration of the region connected to the conductive layer 23 on the surface of the drain region can be increased by the amount corresponding to the n + type semiconductor region 21N.
The impurity concentration of the n-type impurity that reduces the resistance value introduced into the conductive layer 23 (polycrystalline silicon film) can be reduced (the impurity concentration required for ohmic connection is the n + -type semiconductor region 21).
It is possible to reduce the leakage of impurities from the conductive layer 23 to the drain region.

(14) MISF for driving memory cell MC
In a method of manufacturing an SRAM having ETQd (the same applies to the transfer MISFET Qt, the peripheral circuit n-channel MISFET Qn, and the p-channel MISFET Qp),
forming the gate electrode 7 on the main surface of the p-type well region 2M with the gate insulating film 6 interposed therebetween;
A side wall spacer 9 having an insulating property on the side wall in the gate length direction, a step of forming an insulating film 9T covering at least the surface of the side wall spacer 9, the main surface of the p--type well region 2M Of the gate electrode 7, sidewall spacers 9 and insulating film 9T
Each of the steps of introducing an n-type impurity into regions other than the above by ion implantation, forming the n + -type semiconductor region 11 used as each of the source region and the drain region with this n-type impurity, and forming the driving MISFET Qd. It is equipped with.

With this structure, a region in which the maximum stress generated at the open end of the sidewall spacer 9 is concentrated due to the volume change of the gate electrode 7 (due to the difference in the coefficient of thermal expansion with the sidewall spacer 9). On the other hand, regions in which damage is generated due to the implantation of the n-type impurities forming the n + -type semiconductor regions 11 of the source region and the drain region, respectively, can be shifted by the amount corresponding to the film thickness of the insulating film 9T ( Since each of the maximum stress concentration region and the damage generation region can be dispersed), it is generated in the main surface of the p − type well region 2M and the n + type semiconductor region 11 in the open end region of the sidewall spacer 9. It is possible to prevent crystal defects or crystal defects that occur across the pn junction between the p- type well region 2M and the n + type semiconductor region 11.

(Embodiment 2) The present embodiment 2 is a second embodiment of the present invention in which the SRAM of the above-mentioned embodiment 1 is constructed by an n-type semiconductor substrate.

The basic structure of the semiconductor substrate having the SRAM according to the second embodiment of the present invention will be briefly described with reference to FIG. 16 (basic conceptual sectional view).

The SRAM of the second embodiment is composed of an n--type semiconductor substrate (Nsub) 1 as shown in FIG. The memory cell array MAY on the main surface of the n--type semiconductor substrate 1.
The region in which the P-type well region is arranged is a p-type well region (Pwell) 2. Of the peripheral circuits including the direct peripheral circuit and the indirect peripheral circuit, the complementary MISFET of the peripheral circuit to which the power supply voltage Vcc is supplied has substantially the same structure as the p--type well region 2 in which the memory cell array MAY is arranged. Is formed on the main surface of the p-type well region 2 and the main surface of the n-type well region (Nwell) 3.

On the other hand, the p-channel MISFET Qp of the complementary MISFET of the peripheral circuit to which the step-down power supply voltage Vdd stepped down by the power supply voltage conversion circuit VRC is supplied is p-.
N formed on the main surface of the well isolation region (Piso) 2i
-Type well region (Nwell) is formed on the main surface of 3M. The impurity concentration on the surface of the n--type well region 3M is equal to the impurity concentration on the surface of the n--type well region 3 arranged around the outer periphery of the p--type well isolation region 2i, as in the first embodiment. Alternatively, the impurity concentration is set higher than that. p-
In the outer periphery of the n-type well region 3M on the main surface of the type well isolation region 2i, in order to increase the impurity concentration of the surface,
A p-type well region 2 is formed.

The SRAM of the present embodiment has an undershoot resistance slightly lower than that of the first embodiment, but substantially the same effect as that of the first embodiment can be obtained.

Next, a specific manufacturing method of the SRAM,
In particular, p--type well isolation region 2i and n--type well region 3
Each manufacturing method of M will be briefly described with reference to FIG. 17 (cross-sectional view in a predetermined manufacturing process).

First, an n--type semiconductor substrate 1 is prepared, and a mask (indicated by reference numeral 53 in FIG. 17 and shown by a one-dot chain line) 53 in which a part of the main surface of the n--type semiconductor substrate 1 is opened is used. On the main surface of the n − -type semiconductor substrate 1,
Introduce each of the type impurities. As the p-type impurity, for example, B, which is faster than the diffusion rate of the n-type impurity, is used, and as the n-type impurity, As having a lower diffusion rate than the p-type impurity is used.
Is used. The p-type impurity and the n-type impurity are introduced by, for example, ion implantation using the same mask 53.

Next, the mask 53 is removed, and as shown in FIG. 17, p-type impurities and n-type impurities are expanded and diffused, and the p-type well isolation regions 2i and n-type are formed by p-type impurities. Each of the n-type well regions 3M is formed by impurities. p-
The type well isolation region 2i and the n − type well region 3M each have a double well structure as shown in FIG. 17 by utilizing the diffusion rate difference between the p type impurity and the n type impurity.

Thereafter, the n-type well region 3 and the p-type well region 2 are formed, and S is formed in the same manner as in the first embodiment.
The SRAM of the second embodiment is completed by performing the RAM manufacturing process.

As described above, the SRAM of this embodiment
According to the above, the following effects can be obtained.

(1) A p--type well isolation region 2i is formed in the first region of the main surface of the n--type semiconductor substrate 1, and an n--type well is formed in the second region of the main surface of the n--type semiconductor substrate 1. In the SRAM in which the region 3 is formed and the n − type well region 3M is formed on the main surface of the p − type well isolation region 2i, the first region is formed on the main surface of the n − type semiconductor substrate 1. A step of forming an opened first mask (53),
Using the first mask, introducing a p-type impurity into the main surface of the n-type semiconductor substrate 1 and introducing an n-type impurity having a slow diffusion rate with respect to the p-type impurity, the first mask And a second mask in which the second region and the first region are opened on the main surface of the n-type semiconductor substrate 1 (corresponding to 52M in FIG. 15B of Example 1 described above). Forming a n-type well region using the second mask, introducing an n-type impurity into the main surface of the n-type semiconductor substrate 1 and diffusing each of the n-type impurity and the p-type impurity. 3, p- type well isolation region 2i and n- type well region 3M are respectively formed.

With this structure, in addition to the function and effect of the means (5) of the first embodiment, the following function and effect can be obtained.
(1) Using the process of diffusing the n-type impurities introduced into the second region of the main surface of the n-type semiconductor substrate 1 to form the n-type well region 3, the p-type impurity introduced into the first region is used. Impurities are diffused to form p--type well isolation regions 2i, and
Since the n-type impurity introduced into the first region is diffused to form the n-type well region 3M, the p-type impurity and the n-type impurity are diffused to diffuse the p-type well isolation region 2i and the n-type well, respectively. SR corresponding to the process of forming each of the regions 3M
The number of steps in the AM manufacturing process can be reduced. (2) Since the diffusion speed of the n-type impurity is slower than that of the p-type impurity, the main surface of the p-type well isolation region 2i formed by diffusion of the p-type impurity is utilized by utilizing this difference in the diffusion speed. A p-type well region 3M formed by diffusing an n-type impurity can be formed at this point (a double well structure can be formed).

The inventions made by the present inventors are as follows.
Although the specific description has been given based on the above-mentioned embodiment, the present invention is not limited to the above-mentioned embodiment, and needless to say, various modifications can be made without departing from the scope of the invention.

For example, the present invention can be applied to the case where a high resistance element is used as the load element of the above-mentioned SRAM memory cell.

Further, the present invention may be applied to an SRAM mounted on a semiconductor integrated circuit device such as a microprocessor.

The present invention is not limited to SRAM,
D employing the double well structure (D ynamic) storage circuit system and a logic circuit system, such as a RAM is widely applicable to a semiconductor integrated circuit device is mounted.

[0363]

The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.

(1) In the semiconductor integrated circuit device adopting the double well structure, the operational reliability of the circuit arranged on the main surface of the well region in the well isolation region can be improved.
In addition, the operating speed of the circuit arranged on the main surface of the well region outside the well isolation region can be increased.

(2) In a semiconductor integrated circuit device having an SRAM in which memory cells are arranged in the well region in the well isolation region, the information holding characteristic of the SRAM can be improved.

(3) In a semiconductor integrated circuit device adopting a double well structure, the degree of integration can be improved.

(4) In the semiconductor integrated circuit device adopting the double well structure, the breakdown voltage between the well region in the well isolation region and the substrate can be improved.

(5) In the semiconductor integrated circuit device adopting the double well structure, the number of manufacturing process steps can be reduced.

(6) MISFET adopting SOI structure
In a semiconductor integrated circuit device having:
The breakdown voltage of the T gate insulating film can be improved.

(7) The effect (6) can be achieved, and the controllability of the film thickness of the gate insulating film of the MISFET can be improved.

(8) The effect (6) can be achieved, and the number of steps in the manufacturing process of the semiconductor integrated circuit device can be reduced.

(9) The object (6) can be achieved, and the surface of the semiconductor integrated circuit device can be flattened.

(10) MISFE adopting SOI structure
In a semiconductor integrated circuit device having an SRAM having a memory cell of T, standby current failure can be prevented.

(11) In the semiconductor integrated circuit device in which the electrode is connected to the source region or the drain region of the MISFET, it is possible to prevent the occurrence of crystal defects in the connection region.

(12) In the semiconductor integrated circuit device in which the electrodes are connected to the source region or the drain region of the MISFET, the number of manufacturing process steps can be reduced.

(13) MISFET for driving memory cell
In the semiconductor integrated circuit device having the SRAM in which the load element is connected to the drain region of, the power consumption can be reduced.

(14) MISFET for driving memory cell
In the semiconductor integrated circuit device having the SRAM in which the load element is connected to the drain region of the memory cell, the information retention characteristic of the memory cell can be improved.

(15) In the semiconductor integrated circuit device in which the sidewall spacer is formed on the sidewall of the gate electrode of the MISFET and the source region and the drain region are formed using the sidewall spacer as a mask.
It is possible to prevent the occurrence of crystal defects in the source region and the drain region of the ISFET.

[Brief description of drawings]

FIG. 1 is a chip layout diagram of an SRAM according to a first embodiment of the present invention.

FIG. 2A is an enlarged block diagram of a main part of the SRAM, and FIG. 2B is a block circuit diagram showing a power supply system.

FIG. 3 is an enlarged block diagram of a main part of the SRAM.

FIG. 4 is an enlarged block diagram of a main part of the SRAM.

FIG. 5 is a circuit diagram of a memory cell of the SRAM.

FIG. 6 is a sectional view of the memory cell.

FIG. 7 is a plan view of the memory cell.

8A and 8B are plan views of a memory cell shown in each step, and FIG. 8C is a plan view showing a specific layer of the memory cell.

9A to 9D are plan views of an array end portion showing each process.

FIG. 10 is a cross-sectional view of the end portion of the array.

FIG. 11 is a sectional view of a peripheral circuit of the SRAM.

FIG. 12 is an enlarged cross-sectional view of a main part of the memory cell.

FIG. 13 is an impurity concentration distribution diagram of the SRAM substrate and well region.

14A to 14O are cross-sectional views of a memory cell in each step.

FIGS. 15A to 15F are cross-sectional views of the end portion of the array shown in each step.

FIG. 16 is a conceptual cross-sectional view of the SRAM substrate according to the second embodiment of the present invention.

FIG. 17 is a sectional view of a specific process of the substrate.

[Explanation of symbols]

1 ... Semiconductor substrate, 2, 2M, 3, 3M ... Well region, 2
i, 3i ... Well isolation region, 4 ... Element isolation insulating film, 5 ...
Channel stopper region, 6, 12, 24 ... Gate insulating film, 7 ... Gate electrode, 13 ... Gate electrode, word line or wiring 10, 11, 17, 18, 21N, 39, 40 ...
Semiconductor region, 23, 26, 29, 33 ... Conductive layer or wiring, 9, 16 ... Sidewall spacer, 22 ... Connection hole, 9T, 21, 24G, 27, 30 ... Interlayer insulating film, M
C ... Memory cell, Qt ... Transfer MISFET, Qd ... Driving MISFET, Qp ... Load MISFET, C ... Capacitance element, WL ... Word line, DL ... Data line, Gr ... Guard ring region.

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] April 8, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Full text

[Correction method] Change

[Correction content]

[Document name] Statement

Title: Semiconductor integrated circuit device and method for forming the same

[Claims]

Detailed Description of the Invention

[0001]

The present invention relates to relates to a semiconductor integrated circuit device, in particular, SRAM (S tatic R andom A ccess M em
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having an ory).

[0002]

2. Description of the Related Art An SRAM as a volatile semiconductor memory device is described in JP-A-3-234055. In this kind of SRAM, a memory cell for storing 1 [bit] of information is arranged at each intersection of a complementary data line and a word line.

[0003] The memory cell flip-flop circuits and two transfer MOSFET (M etal O xide S emicon
composed of a ductor F ield E ffect T ransistor) . The transfer MOSFET connects one semiconductor region to the input / output terminal of the flip-flop circuit and connects the other semiconductor region to the complementary data line. This transfer MOSFET is
Connect the gate electrode to the word line and conduct with this word line,
Non-conduction is controlled. The flip-flop circuit is configured as an information storage unit and includes two driving MOSFETs and two driving MOSFETs.
It is composed of individual load MOSFETs. Driving MOSF
The ET connects the drain region to one semiconductor region of one transfer MOSFET and connects the source region to the reference voltage line (source line). The gate electrode of the driving MOSFET is connected to one semiconductor region of the other transfer MOSFET. The load MOSFET is one transfer MOSF
The drain region is connected to one semiconductor region of ET, and the source region is connected to the power supply voltage wiring (source line).

Both the transfer MOSFET and the drive MOSFET of the memory cell are of n-channel conductivity type. The load MOSFET of the memory cell is of p-channel conductivity type. That is, the memory cell is a completely complementary M
OSFET (full CMOS: C omplementary M etal O
consisting of xide S emiconductor F ield E ffect T ransistor).

The transfer MOSFET is a so-called LDD ( L i
The ghtly D oped D rain structure is adopted. In the transfer MOSFET adopting the LDD structure, an n-type semiconductor region having a low impurity concentration is formed on the channel forming region side of the n-type semiconductor region having a high impurity concentration in the drain region. That is,
The transfer MOSFET adopting the LDD structure can relax the electric field strength near the drain region, reduce the generation of hot carriers, and prevent the deterioration of the threshold voltage with time. Any improvement in information read characteristics can be achieved.

The driving MOSFET is a so-called DDD ( D oubl
e D iffused D rain) structure is employed. In the driving MOSFET adopting the DDD structure, the diffusion dimension of the region corresponding to the current path of the n-type semiconductor region set to the low impurity concentration of the source region and the drain region is the physical diffusion speed of the impurity. Since the size can be set to a minute size determined by the difference, the parasitic resistance added to the current path can be reduced.
That is, the driving MOSFET adopting the DDD structure can improve the drivability and can improve the information retention characteristic (data retention characteristic) of the memory cell.

The load MOSFET is the drive M
Placed on top of OSFET, so-called SOI (S ilicon O
n I nsulator or Thin Film Transistor) structure is employed. In the load MOSFET, a channel forming region is arranged on the surface of the gate electrode with a gate insulating film interposed.
The source region is connected to one end of the channel forming region and the drain region is connected to the other end. The gate electrode is formed of a lower polycrystalline silicon film, and the channel forming region, the source region and the drain region are formed of an upper polycrystalline silicon film.

A plurality of the memory cells are regularly arranged in a matrix to form a memory cell array. Peripheral circuits are arranged around the outer periphery of the memory cell array. The peripheral circuits mainly include a direct peripheral circuit that directly controls the circuit operation of the memory cell and an indirect peripheral circuit that controls the circuit operation of the direct peripheral circuit. The direct peripheral circuit includes a decoder circuit, a driver circuit, a sense amplifier circuit and the like. The indirect peripheral circuit includes an input / output circuit and an address buffer circuit. The peripheral circuit is mainly composed of complementary MOSFETs for the purpose of low power consumption and high-speed circuit operation.

[0009]

The inventor of the present invention has found that the SRAM
Prior to the development of, the following problems were discovered.

(1) The SRAM is composed of a p-type semiconductor substrate, and has a double well structure in which a p-type well region is formed on the main surface of the n-type well isolation region for the purpose of preventing undershoot. The memory cell array is arranged on the main surface of the p-type well region in the n-type well isolation region. The double well structure is so called because the cross-sectional structure of the n-type well isolation region is composed of double diffusion regions including the p-type well region. When the regions are arranged, this n-type well region is called a triple well structure. The double well structure described above can form a potential barrier region at the pn junction between the p-type semiconductor substrate, the n-type well isolation region, and the p-type well region. That is, α rays are incident on the p-type semiconductor substrate,
When minority carriers are generated by the incidence of α rays, the minority carriers are prevented from invading the p-type well region in which the memory cell array is arranged, so that an SRAM with high α-ray soft error resistance can be constructed.

When an n-type semiconductor substrate is used for the SRAM, the p-type semiconductor substrate on which the n-type semiconductor substrate and the memory cell array are arranged.
Since only one pn junction can be formed with the type well region, if minority carriers are generated in the n-type semiconductor substrate,
Intrusion of minority carriers into the p-type well region is predicted, and α
It is considered that the line soft error resistance is slightly reduced.

Each of the p-type well region inside the n-type well isolation region and the p-type well region outside the n-type well isolation region is
In the SRAM manufacturing process, they are formed in the same process in order to avoid an increase in the number of manufacturing process steps.

However, the impurity concentration on the surface of the p-type well region in the n-type well isolation region is lowered (eroded) by the impurity concentration on the surface of the n-type well isolation region.
The impurity concentration on the surface of the type well region is lower than the impurity concentration on the surface of the p-type well region outside the n-type well isolation region. For this reason, the threshold voltage of each of the transfer MOSFET and the drive MOSFET of the memory cell is lowered, and the noise margin is deteriorated (because the information stored in the memory cell is more likely to be inverted by noise). The information retention characteristic of the SRAM deteriorates.

In order to solve the above problem, if the impurity concentration on the surface of the p-type well region is set to be high overall, the impurity concentration on the surface of the p-type well region outside the n-type well isolation region becomes high. .. Therefore, the n-channel MOSFET of the peripheral circuit arranged on the main surface of the p-type well region
On the contrary, the threshold voltage rises and the switching operation speed decreases, so that the circuit operation speed of the SRAM deteriorates.

(2) n described in the above problem (1)
Since the type well isolation region is diffused deeper than the respective diffusion depths of the p type well region and the n type well region, the impurity concentration on the surface of the n type well isolation region is lowered. For this reason,
In the region where the impurity concentration on the surface of the n-type well isolation region is lowered, the p-type well region and the p-type well region in the n-type well isolation region are formed.
Withstand voltage between the semiconductor substrate and the semiconductor substrate deteriorates.

(3) In the load MOSFET of the memory cell of the SRAM, a channel forming region, a source region and a drain region are arranged on the surface of the gate electrode with a gate insulating film interposed. The gate electrode is formed by depositing a polycrystalline silicon film and then performing patterning by anisotropic etching for the purpose of fine processing. As the gate insulating film, a silicon oxide film deposited by a CVD method or a laminated film mainly containing the silicon oxide film is used mainly for the purpose of making the film thickness uniform.

However, the shape of the corner between the upper surface and the side surface of the gate electrode of the load MOSFET is formed into a sharp shape by anisotropic etching. In particular,
Since the load MOSFET adopts the SOI structure and the gate electrode is formed on the region where the underlying stepped shape exists, when the end of the gate electrode is located in the underlying stepped shape, the corner of the surface of the gate electrode is formed. The part is formed in a sharp shape having an acute angle. Therefore, electric field concentration occurs at the corners of the surface of the gate electrode, or the film quality of the gate insulating film formed along the corners of the surface of the gate electrode deteriorates, and the dielectric strength of the gate insulating film of the load MOSFET is increased. Is significantly deteriorated.

In the worst case, a short circuit occurs between the gate electrode of the load MOSFET and the source or drain region. That is, one load M of the memory cell
The power supply voltage is supplied to the information storage node connected to the drain region of the OSFET, and the power supply voltage is supplied to the information storage node connected to the drain region of the other load MOSFET, which should not be supplied originally, thereby causing a standby current failure. Occurs.

(4) The drain region of the load MOSFET is connected to the drain region (corresponding to an information storage node) of the driving MOSFET of the memory cell of the SRAM. The drain region of this driving MOSFET and the load M
The connection with the drain region of the OSFET is performed via an electrode (polycrystalline silicon film in the same layer) extracted from the gate electrode of another load MOSFET in the memory cell. The drain region of the driving MOSFET and the electrode are connected to each other through an opening (connection hole) formed in the interlayer insulating film covering the main surface of the drain region of the driving MOSFET.

The connection structure of the electrode to the drain region of this driving MOSFET is formed by the following manufacturing process. First, a driving MOSFET is formed on the main surface set in the (100) crystal plane of the p-type well region formed in the n-type well isolation region of the p-type semiconductor substrate. Next, an interlayer insulating film is formed on the main surface of the drain region of this driving MOSFET. The interlayer insulating film is formed of a silicon oxide film deposited by the CVD method. Next, the MOS for driving the interlayer insulating film
An opening is formed on the main surface of the drain region of the FET. Then, a polycrystalline silicon layer is formed on the entire surface of the interlayer insulating film, the polycrystalline silicon layer being in contact with the main surface of the drain region through an opening at a part thereof. The polycrystalline silicon film is deposited by the CVD method, and an n-type impurity that reduces the resistance value is introduced into the polycrystalline silicon film during or after the deposition. Next, the polycrystalline silicon film is subjected to patterning, and the patterned electrode is subjected to heat treatment for the purpose of crystallization to form the gate electrode of the load MOSFET and the above-mentioned electrode.

However, since the electrode connected to the main surface of the drain region of the driving MOSFET is subjected to heat treatment for the purpose of crystallization after patterning of the polycrystalline silicon film, the electrode is voluminous by cooling after the heat treatment. Shrinkage occurs. The stress due to the volume contraction of the electrode has a difference in thermal expansion coefficient between the polycrystalline silicon film of the electrode and the silicon oxide film of the interlayer insulating film. Concentrate on the main surface of the drain region. Therefore, a crystal defect occurs from the main surface of the drain region across the pn junction between the drain region and the p-type well region, so that the amount of leak current at the information storage node of the memory cell increases and the standby current of the SRAM is increased. The amount increases. Also,
The information retention characteristic of the SRAM memory cell deteriorates. It has been confirmed by the present inventor that the above-mentioned crystal defects occur along the (111) crystal plane because the main surface of the p-type well region is set to the (100) crystal plane.

(5) The transfer MOSFET of the SRAM memory cell and the n-channel MOSFET of the peripheral circuit each have an LDD structure. The MOSFET adopting the LDD structure is formed by the following manufacturing process.

First, a gate electrode is formed on the main surface of the p-type well region with a gate insulating film interposed. Next, using the gate electrode or a mask for patterning the gate electrode, an n-type impurity is introduced into the main surface of the p-type well region at a low impurity concentration. Next, a sidewall spacer is formed on the sidewall of the gate electrode in the gate length direction.
The sidewall spacer can be formed only on the sidewall of the gate electrode by depositing a silicon oxide film on the entire surface by the CVD method and performing anisotropic etching on the entire surface of the silicon oxide film by an amount corresponding to the deposited film thickness. .. Next, using the sidewall spacer and the gate electrode as a mask, an n-type impurity is introduced into the main surface of the p-type well region at a high impurity concentration. In any case, the introduction of the n-type impurity is performed by ion implantation with high controllability of the impurity concentration. Next, the introduced n-type impurity is stretched and diffused to form an n-type semiconductor region having a low impurity concentration and an n-type semiconductor region having a high impurity concentration in the MOSFET adopting the LDD structure.

However, in the MOSFET adopting the LDD structure, volume contraction occurs in the gate electrode due to the temperature cycle during the SRAM manufacturing process. The volume contraction of the gate electrode causes stress concentration on the main surfaces of the source region and the drain region at the open end of the side wall of the gate electrode (the side opposite to the side contacting the side wall of the gate electrode). .. In addition, the stress concentration portion of each main surface of the source region and the drain region is
Since the n-type impurity having a particularly high impurity concentration is introduced by ion implantation, damage due to the introduction of the n-type impurity occurs. Therefore, a crystal defect is generated across the pn junction between the main surface of each of the source region and the drain region and the p-type well region. Memory cell transfer memory
At T, when the source region or the drain region is used as the information storage node of the memory cell, the amount of leak current of the information storage node increases and the amount of standby current of the SRAM increases. In addition, the information retention characteristic of the memory cell of the SRAM deteriorates. It has been confirmed by the present inventor that crystal defects are generated along the (111) crystal plane, similarly to the problem (4).

The objects of the present invention are as follows.

(1) In a semiconductor integrated circuit device adopting a double well structure (or a triple well structure), it is possible to improve the operational reliability of the circuit arranged on the main surface of the well region in the well isolation region. In addition, the operating speed of the circuit arranged on the main surface of the well region outside the well isolation region is increased.

(2) In a semiconductor integrated circuit device having an SRAM in which memory cells are arranged in the well region in the well isolation region, the information holding characteristic of the SRAM is improved.

(3) To improve the degree of integration in a semiconductor integrated circuit device which employs a double well structure.

(4) In a semiconductor integrated circuit device adopting a double well structure, the breakdown voltage between the well region in the well isolation region and the substrate is improved.

(5) In the semiconductor integrated circuit device adopting the double well structure, the number of steps in the manufacturing process is reduced.

(6) MISFET adopting SOI structure
(MetalInsulatorSemiconductorFieldEffect
Transistor) in a semiconductor integrated circuit device,
To improve the withstand voltage of the gate insulating film of the MISFET
It

(7) The above object (6) is achieved and the controllability of the film thickness of the gate insulating film of the MISFET is improved.

(8) The object (6) is achieved and the number of steps in the manufacturing process of the semiconductor integrated circuit device is reduced.

(9) The object (6) is achieved, and the surface of the semiconductor integrated circuit device is flattened.

(10) MISFE adopting SOI structure
In a semiconductor integrated circuit device having an SRAM having a memory cell of T, a standby current defect is prevented.

(11) In a semiconductor integrated circuit device in which electrodes are connected to the source region or the drain region of the MISFET, the occurrence of crystal defects in the connection region is prevented.

(12) In the semiconductor integrated circuit device in which the electrodes are connected to the source region or the drain region of the MISFET, the number of manufacturing process steps is reduced.

(13) MISFET for driving memory cell
In the semiconductor integrated circuit device having the SRAM in which the load element is connected to the drain region of, the power consumption is reduced.

(14) MISFET for driving memory cell
In a semiconductor integrated circuit device having an SRAM in which a load element is connected to the drain region of the memory cell, the information retention characteristic of the memory cell is improved.

(15) In the semiconductor integrated circuit device, wherein a sidewall spacer is formed on the sidewall of the gate electrode of the MISFET, and the sidewall spacer is used as a mask to form the source region and the drain region, respectively.
The generation of crystal defects occurring in the source region and the drain region of the ISFET is prevented.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0042]

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) A first semiconductor region of a second conductivity type is formed in a first region of a main surface of a semiconductor substrate of a first conductivity type, and a second semiconductor region of the first conductivity type is formed in a second region of the main surface of the semiconductor substrate. A second semiconductor region that is formed and has a higher impurity concentration than that of the semiconductor substrate is formed, and a third semiconductor region of the first conductivity type is formed on the main surface of the first semiconductor region, and the second semiconductor region is formed. , A semiconductor integrated circuit device in which a first conductivity type channel MISFET is formed on each main surface of the third semiconductor region, the impurity concentration of the surface of the third semiconductor region is the impurity concentration of the surface of the second semiconductor region. Is set equal to or higher than.

(2) The semiconductor integrated circuit device according to the above-mentioned means (1) is equipped with an SRAM, and the first conductivity type channel is formed on the main surface of the third semiconductor region of the main surface of the first semiconductor region. The MISFET constitutes a flip-flop circuit of an SRAM memory cell, and the first conductivity type channel MISFET formed on the main surface of the second semiconductor region is the S-type.
A peripheral circuit that directly or indirectly drives the memory cell of the RAM is configured.

(3) The third semiconductor region described in the means (1) or (2) is formed in self-alignment with the first semiconductor region.

(4) A second conductive type first semiconductor region is formed in the first region of the main surface of the first conductive type semiconductor substrate, and a first conductive type is formed in the second region of the main surface of the semiconductor substrate. A semiconductor integrated circuit device in which a second semiconductor region formed and having a higher impurity concentration than that of the semiconductor substrate is formed, and a third semiconductor region of the first conductivity type is formed on the main surface of the first semiconductor region. A fourth semiconductor region formed of the second conductivity type and having a higher impurity concentration than that of the first semiconductor region in a region of the main surface of the first semiconductor region along the outer periphery of the third semiconductor region. Make up.

(5) A first semiconductor region of the second conductivity type is formed in the first region of the main surface of the semiconductor substrate of the first conductivity type, and a first conductivity type is formed in the second region of the main surface of the semiconductor substrate. In a semiconductor integrated circuit device, a second semiconductor region formed and having a higher impurity concentration than that of the semiconductor substrate is formed, and a third semiconductor region of the first conductivity type is formed on the main surface of the first semiconductor region. In the forming method, a step of forming a first mask having an opening in the first region on the main surface of the semiconductor substrate, the first mask is used, and a second conductive type first mask is formed on the main surface of the semiconductor substrate. A step of introducing an impurity and diffusing the first impurity to form a first semiconductor region of the second conductivity type; and using the first mask, a main surface of the first semiconductor region of the first conductivity type is formed. Introducing a second impurity, removing the first mask, Forming a second mask in which the second region is opened or a second mask in which the second region and the first region are opened on the main surface of the conductor substrate; and using the second mask, the semiconductor A third impurity of the first conductivity type is introduced into the main surface of the substrate, and the third impurity, the second impurity
Each step of diffusing each of the impurities to form each of the second semiconductor region and the third semiconductor region is provided.

(6) A second conductive type first semiconductor region is formed in the first region of the main surface of the first conductive type semiconductor substrate, and the first conductive type is formed in the second region of the main surface of the semiconductor substrate. In a semiconductor integrated circuit device, a second semiconductor region formed and having a higher impurity concentration than that of the semiconductor substrate is formed, and a third semiconductor region of the first conductivity type is formed on the main surface of the first semiconductor region. In the forming method, a step of forming a first mask having an opening in the first region on the main surface of the semiconductor substrate, the first mask is used, and a second conductive type first mask is formed on the main surface of the semiconductor substrate. Introducing an impurity and introducing a second impurity that is of the first conductivity type and has a slow diffusion rate with respect to the first impurity; removing the first mask; and removing the first mask on the main surface of the semiconductor substrate. A second mask in which the second region is opened, or before Forming a second mask having openings in the second region and the first region; using the second mask, introducing a third impurity of the first conductivity type into the main surface of the semiconductor substrate; And diffusing each of the first impurity and the second impurity to form each of the second semiconductor region, the first semiconductor region, and the third semiconductor region.

(7) A semiconductor integrated circuit device having a MISFET in which a gate insulating film is provided on the surface of a channel forming region or a gate electrode and a gate electrode or a channel forming region which crosses the channel forming region or the gate electrode is formed. Forming a channel forming region or a gate electrode by depositing a semiconductor layer or a gate electrode layer on the entire surface of the substrate, patterning the semiconductor layer or the gate electrode layer, and forming the channel forming region or the gate electrode. A part of the film thickness of the electrode is oxidized or nitrided from the surface to form an oxide film or a nitride film having a film thickness larger than that of the native silicon oxide film, and the channel formation region or the surface of the gate electrode. And a step of forming a gate insulating film on the surface of the channel formation region or the gate electrode. , The upper and side surfaces of the channel forming region or the gate electrode, and interposing the gate insulating film comprises a respective step of forming the channel formation region or the gate electrode or the channel forming region across the gate electrode.

(8) In the step of forming the gate insulating film in the step described in the means (7), the channel forming region in the step or the oxide film or the nitride film on the surface of the gate electrode is removed, and then the channel forming region is formed. Alternatively, this is a step of newly forming a gate insulating film on the surface of the gate electrode.

(9) In the step of forming the gate insulating film in the step described in the above means (7), the step of forming the gate insulating film by the oxide film or the nitride film on the surface of the channel forming region or the gate electrode in the step Or a step of forming a gate insulating film with a composite film in which an insulating film is newly deposited on the surface of the oxide film or the nitride film.

(10) A semiconductor integrated circuit device having a MISFET in which a gate insulating film is provided on the surface of a channel forming region or a gate electrode and a gate electrode or a channel forming region which crosses the channel forming region or the gate electrode is formed. Forming a channel forming region or a gate electrode by depositing a semiconductor layer or a gate electrode layer on the entire surface of the substrate, patterning the semiconductor layer or the gate electrode layer, and forming the channel forming region or the gate electrode. A step of forming a side wall spacer on the side surface of the electrode, a part of the film thickness of the channel formation region or the gate electrode is oxidized or nitrided from the surface, and an oxide film having a film thickness larger than that of the native silicon oxide film is formed. A film or a nitride film is formed, and the shape of the corner of the channel formation region or the surface of the gate electrode is changed. The step of forming a gate insulating film on the surface of the channel forming region or the gate electrode, the channel forming region with the gate insulating film interposed on the upper and side surfaces of the surface of the channel forming region or the gate electrode. Alternatively, each step of forming a gate electrode or a channel formation region across the gate electrode is provided.

(11) Means (7) to (10)
The semiconductor integrated circuit device described in any one of
Is mounted, and the MISFET constitutes a load MISFET of the flip-flop circuit of the SRAM memory cell.

(12) On the main surface of the second semiconductor region of the second conductivity type formed on the main surface of the first semiconductor region of the first conductivity type,
In a method of manufacturing a semiconductor integrated circuit device in which a silicon film is connected through an opening formed in an insulating film on the main surface of the second semiconductor region, a second conductive film is formed on the main surface of the first conductive type first semiconductor region. Forming a second semiconductor region of the mold, forming an insulating film on the main surface of the second semiconductor region,
An opening is formed on the second semiconductor region of the insulating film, and a region corresponding to the inside of the opening has the same conductivity type as the second semiconductor region on the main surface of the first semiconductor region and the second semiconductor region. A step of forming a third semiconductor region having a deeper junction depth, and contacting the respective main surfaces of the second semiconductor region and the third semiconductor region through an opening formed in the insulating film on the entire surface of the insulating film. Deposit a silicon film by the CVD method,
Each step of patterning this silicon film to form an electrode or wiring is provided.

(13) On the main surface of the second semiconductor region of the second conductivity type formed on the main surface of the first semiconductor region of the first conductivity type,
In a method of manufacturing a semiconductor integrated circuit device in which a silicon film is connected through an opening formed in an insulating film on the main surface of the second semiconductor region, a second conductive film is formed on the main surface of the first conductive type first semiconductor region. Forming a second semiconductor region of the mold, forming an insulating film on the main surface of the second semiconductor region,
Forming an opening on the second semiconductor region of the insulating film,
Depositing a silicon film in contact with the main surface of the second semiconductor region through an opening formed in the insulating film on the entire surface of the insulating film; performing high temperature annealing for crystallizing the silicon film; Each step of patterning the film to form an electrode or wiring is provided.

(14) Means (12) or means (1)
The semiconductor integrated circuit device described in 3) has an SRAM mounted therein, the second semiconductor region is a drain region of a driving MISFET of a flip-flop circuit of a memory cell of the SRAM, and the electrode is connected to a power supply voltage. ..

(15) In a method of manufacturing a semiconductor integrated circuit device having a MISFET, a step of forming a gate electrode on the main surface of a semiconductor region of the first conductivity type with a gate insulating film interposed, and a gate length of the gate electrode. Forming a sidewall spacer having an insulating property on the side wall in the direction,
Forming a mask covering at least the surface of the sidewall spacer, and ion-implanting a second conductivity type impurity in a region other than the gate electrode, the sidewall spacer and the mask on the main surface of the first conductivity type semiconductor region. Each of the steps includes the step of introducing by implantation, forming the second conductivity type source region and the drain region with the second conductivity type impurity, and forming the MISFET.

[0058]

According to the above-mentioned means (1), the following operational effects can be obtained. (1) The impurity concentration of the surface of the third semiconductor region formed on the main surface of the first semiconductor region is set high (the impurity concentration of the surface is reduced by the impurity concentration of the first semiconductor region, the third semiconductor region is reduced). Of the first conductivity type channel MISFET on the main surface of the third semiconductor region is increased, so that the cutoff current of the first conductivity type channel MISFET is increased. It is possible to reduce the leak current of the semiconductor integrated circuit device. (2) The impurity concentration of the surface of the second semiconductor region is independently set lower than the impurity concentration of the surface of the third semiconductor region formed on the main surface of the first semiconductor region. Since the threshold voltage of the first conductivity type channel MISFET on the main surface can be lowered, the switching operation speed of the first conductivity type channel MISFET can be increased and the circuit operation speed of the semiconductor integrated circuit device can be increased.

According to the above-mentioned means (2), the following function and effect can be obtained in addition to the function and effect of the means (1). (1) Since the leak of the information stored in the information storage node of the flip-flop circuit (information storage section) of the memory cell is reduced and the inversion can be prevented, the information holding characteristic of the SRAM can be improved. (2) Since the circuit operation speed of the peripheral circuit can be increased, and both the information write operation speed and the information read operation speed of the memory cell can be increased (the access time can be increased), the SRAM circuit operation speed can be increased. Can be realized.

According to the above-mentioned means (3), in addition to the function and effect of the means (1) or (2), the arrangement position of the third semiconductor region with respect to the arrangement position of the first semiconductor region is manufactured. Since the size can be reduced by the amount corresponding to the mask alignment margin in the process, useless areas on the main surface of the semiconductor substrate can be eliminated, and the degree of integration of the semiconductor integrated circuit device can be improved.

According to the above-mentioned means (4), the impurity concentration around the outer periphery of the third semiconductor region on the main surface of the first semiconductor region (the impurity concentration in this portion is reduced by diffusion of the first semiconductor region). Is increased in the fourth semiconductor region and the extension of the depletion region extending from the pn junction between the first semiconductor region and the third semiconductor region into the first semiconductor region can be reduced.
The junction breakdown voltage between the third semiconductor region on the main surface of the semiconductor region and the semiconductor substrate can be improved. If the junction breakdown voltage is improved, the distance between the third semiconductor region on the main surface of the first semiconductor region and the semiconductor substrate, that is, the occupied area of the outer periphery of the third semiconductor region on the main surface of the first semiconductor region. Since it is possible to reduce the size, it is possible to eliminate a useless area on the main surface of the semiconductor substrate and improve the degree of integration of the semiconductor integrated circuit device.

According to the above-mentioned means (5), the following operational effects can be obtained. (1) A first mask for forming a first semiconductor region is used in a first region of a main surface of the semiconductor substrate, and a third semiconductor region is formed (using a first mask for introducing a first impurity). Since the second impurity is introduced), the number of steps in the manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of forming the mask for forming the third semiconductor region. (2) Diffusing the third impurity introduced into the second region of the main surface of the semiconductor substrate to form the second semiconductor region, diffusing the second impurity introduced into the first region, Third
Since the semiconductor region is formed, the number of steps in the manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the step of diffusing the second impurity and forming the third semiconductor region. (3) A third semiconductor region formed on the main surface of the first semiconductor region of the first region of the main surface of the semiconductor substrate and a second semiconductor region of the second region
Since the semiconductor regions are formed in separate steps, the impurity concentrations of the third semiconductor region and the second semiconductor region can be independently controlled. (4) A first mask for forming a first semiconductor region is used in the first region of the main surface of the semiconductor substrate, and the third semiconductor region is formed (using the same first mask, the first semiconductor region , And each of the third semiconductor regions are formed)
The placement position of the third semiconductor region is formed in self alignment with respect to the placement position of the semiconductor region, and the placement position of the third semiconductor region with respect to the placement position of the first semiconductor region is a mask alignment margin dimension in a manufacturing process. It can be reduced by a corresponding amount.

According to the above-mentioned means (6), the following function and effect can be obtained in addition to the function and effect of the means (5). (1) diffusing the third impurity introduced into the second region of the main surface of the semiconductor substrate and forming the second semiconductor region, diffusing the first impurity introduced into the first region, First
Since the semiconductor region is formed and the second impurity introduced into the first region is diffused to form the third semiconductor region,
The number of steps in the manufacturing process of the semiconductor integrated circuit device can be reduced by an amount corresponding to the step of diffusing each of the first impurity and the second impurity to form each of the first semiconductor region and the third semiconductor region. (2) Since the diffusion rate of the second impurity is slower than the diffusion rate of the first impurity, the difference in the diffusion rate is used to make the second surface on the main surface of the first semiconductor region formed by the diffusion of the first impurity. A third semiconductor region formed by diffusion of impurities can be formed.

According to the above-mentioned means (7), the following operational effects can be obtained. (1) The shape of the corner portion of the surface of the channel formation region or the gate electrode of the MISFET generated when the semiconductor layer or the gate electrode layer corresponding to the lower layer is patterned is relaxed by the oxidation or nitridation of the surface. (2) As a result of the action and effect (1), electric field concentration can be reduced in the channel formation region in the lower layer of the MISFET or in the corner portion of the surface of the gate electrode, so that in the corner region of the gate insulating film of the MISFET. It is possible to prevent the breakdown voltage from deteriorating. (3) Further, as a result of the action and effect (1), the MISF
Since it is possible to prevent the deterioration of the film quality in the channel formation region of the lower layer of ET or in the corner portion of the surface of the gate electrode, it is possible to prevent the deterioration of the withstand voltage in the corner portion region of the gate insulating film of the MISFET.

According to the above-mentioned means (8), since the gate insulating film is newly formed in an independent process for the oxide film or the nitride film formed on the surface of the channel forming region or the gate electrode, the gate insulating film is formed. The controllability of the thickness of the insulating film can be improved.

According to the above-mentioned means (9), in the step of forming the gate insulating film, the oxide film or the nitride film on the surface of the channel forming region or the gate electrode formed in the previous step is not removed. The number of steps in the manufacturing process of the semiconductor integrated circuit device can be reduced by the amount corresponding to the removing step.

According to the above-mentioned means (10), in addition to the effect of the above-mentioned means (7), M generated when the semiconductor layer or the gate electrode layer corresponding to the lower layer is patterned.
The step shape on the side surface of the channel formation region or the gate electrode of the ISFET is relaxed by the sidewall spacer.

According to the above-mentioned means (11), the SR
MI for load of flip-flop circuit of AM memory cell
In the SFET, it is possible to prevent a short circuit between the gate electrode and the channel formation region (or the source region or the drain region), so that it is possible to prevent a standby current defect.

According to the above-mentioned means (12), the following operational effects can be obtained. (1) Volume of a silicon film based on cooling after high temperature annealing during the deposition of the silicon film in the above process or high temperature annealing performed after the deposition of the silicon film (both are annealing at a temperature higher than the melting point of aluminum) A crystal defect that occurs due to the contraction and that crosses the pn junction between the first semiconductor region and the second semiconductor region from the opening end of the insulating film can be captured in the third semiconductor region. (2) Since a mask for forming an opening in the insulating film and a mask for implanting impurities for forming the third semiconductor region in the above step can both be used, the mask forming step can be reduced by the amount corresponding to the mask for implanting impurities. The number of steps in the manufacturing process of the semiconductor integrated circuit device can be reduced.

According to the above-mentioned means (13), the following operational effects can be obtained. (1) After the silicon film is deposited on the entire surface of the insulating film in the above process, and before the silicon film of the process is subjected to patterning, this silicon film is annealed at a high temperature for the purpose of crystallization. Since stress due to volume contraction during cooling can be dispersed in the entire silicon film and concentration of the stress generated at the opening end formed in the insulating film on the main surface of the second semiconductor region can be reduced. The volume shrinkage of the silicon film can prevent a crystal defect from crossing the pn junction between the first semiconductor region and the second semiconductor region from the opening end of the insulating film. (2) The step of performing the high temperature annealing for crystallizing the silicon film in the step, which has been performed after the patterning of the silicon film in the step, is performed after the silicon film in the step is deposited. Since the silicon film is simply replaced before the patterning step, it is possible to prevent an increase in the number of steps in the manufacturing process of the semiconductor integrated circuit device.

According to the above-mentioned means (14), the following operational effects can be obtained. (1) Since the leak current of the power supply supplied to the information storage node of the memory cell of the SRAM can be reduced, the SRAM
Power consumption of the standby current can be reduced. (2) Since the leak current of the power supply supplied to the information storage node of the memory cell of the SRAM can be reduced, the information retention characteristic of the memory cell can be improved. (3) In the SRAM described in the means (12), a third semiconductor region is added to the drain region of the driving MISFET of the memory cell, and an electrode on the surface of the drain region corresponding to the third semiconductor region. Since the impurity concentration of the region connected to the can be increased, the impurity concentration of the impurity that reduces the resistance value introduced into the electrode (silicon film) can be reduced (the impurity concentration required for ohmic connection is the third
It is ensured in the semiconductor region), and the seeping of impurities from the electrode to the drain region can be reduced.

According to the above-mentioned means (15), the maximum stress generated at the open end of the side wall spacer due to the volume change of the gate electrode (due to the difference in the coefficient of thermal expansion with the side wall spacer) is reduced. Regions in which damages due to implantation of the second conductivity type impurities forming the source region and the drain region are generated with respect to the concentrated regions can be shifted by an amount corresponding to the film thickness of the mask (maximum stress concentration). Region and damage-causing region), crystal defects occurring in the main surface of the first semiconductor region, the source region or the drain region in the open end region of the sidewall spacer, or the first region.
It is possible to prevent crystal defects that occur across the pn junction between the semiconductor region and the source or drain region.

The present invention will be described below in terms of the constitution of the present invention.
A description will be given with an embodiment applied to a RAM.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0075]

(Embodiment 1) FIG. 1 (chip layout diagram) shows an overall schematic configuration of a high-speed SRAM which is Embodiment 1 of the present invention.

The SRAM (semiconductor pellet) shown in FIG. 1 has a large capacity of 4 [Mbit]. This SRAM is
Although not shown, a DIP structure, an SOP structure, or the like is encapsulated in a resin-encapsulated semiconductor device that employs a dual in-line method in which a plurality of leads are arranged on each of two opposing sides of the encapsulation body. The SRAM has a rectangular planar shape. The SRAM of this embodiment has a rectangular long side (in FIG. 1,
The upper and lower sides are 17.41 mm and the short sides (Fig. 1)
Each of the middle, right side, and left side) is 7.55 mm.

The central area of the circuit system mounting surface of the SRAM, specifically, the central area of two long sides of a rectangular shape facing each other, from the left short side to the right short side (hereinafter, X In addition, a plurality of external terminals (bonding pads) BP are arranged, in which the direction from the upper long side to the lower long side is called the Y direction. This external terminal BP
Is electrically connected to the inner lead of the above-mentioned lead. For example, an address signal, a chip select signal, an output enable signal, a write enable signal, and an input / output data signal are applied to each of the plurality of external terminals BP. Further, the power supply voltage Vcc and the reference voltage Vss are applied to the external terminal BP (SRAM
Power is supplied from outside). The power supply voltage Vcc is, for example, the operating voltage of the circuit 5 [V], and the reference voltage Vss is, for example, the ground voltage 0 [V] of the circuit.

A power supply voltage conversion circuit (step-down power supply circuit or regulator) VRC is mounted on the SRAM. The power supply voltage conversion circuit VRC steps down the power supply voltage Vcc (5 [V]) supplied from the outside of the SRAM inside the SRAM, and drops it to a part of the peripheral circuit of the SRAM mainly for the purpose of low power consumption. The step-down power supply voltage Vdd is supplied. As the power supply voltage Vdd, 4 [V] is used in the SRAM of this embodiment. Two power supply voltage conversion circuits VRC are mounted on the circuit system mounting surface of the SRAM, and the central region of the short side on the left side,
At a position close to each of the central regions on the right short side,
Each is arranged.

A part of an indirect peripheral circuit of peripheral circuits such as an address buffer circuit and a predecoder circuit is provided in each of the upper and lower regions of the external terminals BP arranged on the circuit system mounting surface of the SRAM. RCs are arranged respectively.
As shown in FIG. 2B (block circuit diagram showing the power supply system), the indirect peripheral circuit RC is supplied with the step-down power supply voltage Vdd stepped down by the power supply voltage conversion circuit VRC. Peripheral circuits including indirect peripheral circuits other than the indirect peripheral circuit RC and direct peripheral circuits, specifically, decoder circuits (X decoder circuit XDEC, Y decoder circuit YDEC), control circuit CC, sense amplifier circuit SA, output buffer circuit,
Each of the memory cell arrays is basically supplied with a power supply voltage Vcc from the outside. That is, in FIG. 1, the SRAM has the power supply voltage conversion circuit VRC in a circuit arranged in a region surrounded by the virtually drawn dashed line surrounding the external terminal BP, the power supply voltage conversion circuit VRC, and the indirect peripheral circuit RC. The stepped down power supply voltage Vdd is supplied.

In FIG. 1, two memory blocks MB1 and MB2 are arranged between the rectangular long upper side and the indirect peripheral circuit RC on the circuit system mounting surface of the SRAM. Similarly, 2 is provided between the lower long side and the indirect peripheral circuit RC.
Memory blocks MB3 and MB4 are arranged. That is, a total of four memory blocks MB are arranged in the SRAM. Each of the memory blocks MB1 and MB3 is sequentially arranged in the Y direction along the short side on the left side of the rectangular shape, and each of the memory blocks MB2 and MB4 is sequentially arranged in the Y direction along the short side of the right side of the rectangular shape. ..

On the circuit system mounting surface of the SRAM, a Y switch circuit Y-SW, a Y decoder circuit YDEC, and a sense amplifier circuit SA are arranged between the memory blocks MB1 and MB2 and the indirect peripheral circuit RC. Similarly, Y switch circuits Y-SW and Y are provided between the memory blocks MB3 and MB4 and the indirect peripheral circuit RC.
A decoder circuit YDEC and a sense amplifier circuit SA are arranged.

The four memory blocks MB1 to MB4
1 is divided into eight memory mats MM arranged in the X direction, respectively, as shown in FIG. That is, SRA
Since M has four memory blocks MB divided into eight memory mats MM, M is divided into a total of 32 memory mats MM. The four memory blocks MB
In each of 1 to MB4, one X decoder circuit XDEC is arranged between four memory mats MM on the left side and four memory mats MM on the right side arranged in the X direction.

In addition, the memory blocks MB1 and MB2
Between the memory blocks MB3 and MB4, a redundant data line (Y-based redundant circuit) SDB is arranged. Since one redundant data line SDB is provided with four redundant input / output data lines, and four redundant data lines are connected to each redundant input / output data line, a total of 16 redundant data lines are provided. Will be placed. In addition, the memory blocks MB1 to MB1
A redundant word line (X system redundant circuit) SWB is arranged on the side of each Y switch circuit Y-SW and Y decoder circuit YDEC of MB4. In the redundant word line SWB, four redundant sub word lines are arranged for each memory block MB.

The four memory blocks MB1 to MB4
Among them, each of the memory mats MM divided into eight of the one memory block MB has four memories arranged in the X direction as shown in FIG. 2A (enlarged block diagram of a main part). It is composed of a cell array MAY. Each of the four memory cell arrays MAY is arranged in the X direction in the memory mat MM. That is, in the SRAM, each of the four memory blocks MB1 to MB4 is divided into eight memory mats MM, and each of the eight memory mats MM is composed of four memory cell arrays MAY. 128 memory cell arrays MAY are arranged.

Of the 128 memory cell arrays MAY, one memory cell array MAY is further divided into four sub memory cell arrays SMEY, as shown in FIG. 3 (enlarged block diagram of the main part). The sub memory cell arrays SMEY divided into four are arranged in the X direction. The sub memory cell array SMEY is composed of 16 memory cells MC arranged in the X direction (word line extending direction). That is, one memory cell array MAY
Has four sub-memory cell arrays SMEY in which 16 memory cells MC are arranged in the X-direction, a total of 64
(64 [bit]) memory cells MC are arranged. Further, in one memory cell array MAY, 514 (514 [bit]) memory cells MC are arranged in the Y direction (complementary data line extending direction). Of the 514 memory cells MC arranged in the Y direction, 512 (512 [bit]) are configured as regular (actually storing information) memory cells MC, and the remaining two (2 [bit]) Are configured as redundant memory cells MC (redundant word lines SWB).

As shown in FIG. 2 (A) and FIG. 3, 1
A word driver circuit WDR is arranged between the two memory cell arrays MAY on the left side and the two memory cell arrays MAY on the right side of each memory mat MM. FIG. 1
The eight word driver circuits WDR of each of the eight memory mats MM of the one memory block MB of the SRAM shown in FIG. 4 include four memory mats MM on the left side and four memory mats on the right side in the X direction. It is selected by the X decoder circuit XDEC arranged between the MM and the MM. That is,
In one memory block MB, one X decoder circuit XDEC selects one out of a total of eight word driver circuits WDR of eight memory mats MM.

As shown in FIG. 3, the word driver circuit WDR is selected by the X decoder circuit XDEC via the main word line MWL. The word driver circuit WDR is selected by the address signal line AL arranged for each word driver circuit WDR. The main word line MWL extends in the X direction on the memory cell array MAY, and a plurality of main word lines MWL are arranged in the Y direction for every four (4 [bit]) memory cells MC. The address signal lines AL extend in the Y direction and are arranged in the X direction. The address signal line AL is arranged on the right side of the word driver circuit WDR in the memory mat MM.
8 to select the memory cells MC of the memory cell array MAY, and 8 to select the memory cells MC of the two memory cell arrays MAY arranged on the left side.
A total of 16 books will be arranged.

As shown in FIGS. 2A and 3, in the memory mat MM, the word driver circuit WDR
Selects the first word line WL1 and the second word line WL2 extending over one of the four memory cell arrays MAY. First word line WL1
The second word line WL2 is arranged for each memory cell array MAY (for each four sub memory cell arrays SMEY). The first word line WL1 and the second word line WL2 are separated from each other and extend substantially parallel to each other in the X direction.
The first word line WL1 and the second word line WL2 are arranged for each one memory cell MC arranged in the Y direction.
That is, the two first word lines WL1 and the second word lines WL to which the same selection signal is applied to one memory cell MC.
2 are connected.

Of the two memory cell arrays MAY arranged on the right side of the word driver circuit WDR shown in FIGS. 2A and 3 respectively, the word driver circuit WDR
The first word line WL1 and the second word line WL2 extending in the memory cell array MAY on the side closer to are selected by the word driver circuit WDR via the second sub-word line SWL2. The first word line WL1 and the second word line WL2 extending in the memory cell array MAY far away from the word driver circuit WDR are selected by the word driver circuit WDR via the first sub-word line SWL1. The first sub-word line SWL1 and the second sub-word line SWL2 are separated from each other and extend in parallel in the X direction. The first sub-word line SWL1 and the second sub-word line SWL2 are arranged for each one memory cell MC arranged in the Y direction, like the first word line WL1 and the second word line WL2. The first sub-word line SWL1 has one memory cell array M on the side closer to the word driver circuit WDR.
Another memory cell array MA that extends over AY and is far away
First word line WL1 and second word line W arranged in Y
Connect between L2 and the word driver circuit WDR.

In each of the two memory cell arrays MAY arranged on the left side of the word driver circuit WDR, the first word line WL1 and the second word line WL2 are arranged similarly to the right side. The first word line WL1 and the second word line W
L2 is connected to the word driver circuit WDR via the first sub-word line SWL1 or the second sub-word line SWL2.

As shown in FIG. 2 (A), in the memory mat MM, the load circuits LOAD divided respectively are arranged above the four memory cell arrays MAY. Below each of the four memory cell arrays MAY, Y decoder circuits YDEC and Y are divided respectively.
A switch circuit Y-SW is arranged. Further, a sense amplifier circuit SA divided for each of the four memory cell arrays MAY is arranged below each memory cell array MAY. Four sense amplifier circuits SA are arranged for one memory cell array MAY, and 4 [bit] information (four memory cells M
The information stored in C) can be output at one time. A control circuit CC is provided below the word driver circuit WDR.
Are placed. In addition, the memory mat M shown in FIG.
In M, between the two memory cell arrays MAY arranged on the left side and the right side of the word driver circuit WDR, as shown in FIGS. A connecting cell including a connecting connection between the cell arrays MAY is arranged.

As shown in FIGS. 2A and 3, the complementary data lines DL are arranged in the memory cell array MAY in the memory mat MM. Complementary data line DL
Is the main word line MWL, the sub word line SWL,
Crosses the respective extending directions of the word lines WL (substantially orthogonal)
It extends in the Y direction. The complementary data line DL is composed of two data lines, a first data line DL1 and a second data line DL2, which are spaced apart from each other and extend in parallel in the Y direction. As shown in FIG. 3, the complementary data line DL is arranged for each memory cell MC arranged in the X direction. Complementary data line DL
One end side of the upper side of the load circuit LOAD shown in FIG.
Connected to. The other end side below the complementary data line DL is Y
It is connected to the sense amplifier circuit SA via the switch circuit Y-SW.

Peripheral circuits including direct peripheral circuits and indirect peripheral circuits mounted on the circuit system mounting surface of the SRAM,
Each of the memory cells MC arranged in the sub memory cell array SMEY is basically composed of a complementary MISFET. A specific cross-sectional structure of the SRAM will be described later (see FIG. 6,
15 and 16 ), the SRAM is mainly composed of a p-type semiconductor substrate (Psub) 1 made of single crystal silicon.
In this embodiment, the main surface of the SRAM, which is the circuit system mounting surface of the p--type semiconductor substrate 1, is set to the (100) crystal plane (including crystallographically equivalent crystal planes). Also,
In the p − type semiconductor substrate 1, the plane orientation of the (100) crystal plane of the principal plane is 2.5 degrees in a predetermined plane orientation, for example, a [010] plane orientation (including a crystallographically equivalent plane orientation). It is formed of a so-called off-angle wafer inclined at 15 degrees or less. In the SRAM of this embodiment, the p-type semiconductor substrate 1 is formed from a 4 ° off-angle wafer.

As shown in FIG. 3 and FIG. 4 by enclosing the reference numeral 3i in a broken line, in the region where the memory cell array MAY is arranged, n − is formed on the main surface portion of the p − type semiconductor substrate 1.
A type well isolation region (Niso) 3i is arranged. The n--type well isolation region 3i has a sectional structure shown in FIG.
As will be described later with reference to FIG. 15 , the α-ray is a p- type semiconductor substrate 1
The main purpose is to prevent the so-called undershoot (improve the α-ray soft error resistance), which prevents the minority carriers generated when entering the inside from entering the area of the memory cell array MAY.

A p--type well region (Pwell) 2M in which the memory cell array MAY is arranged is arranged on the main surface of the n--type well isolation region 3i. An area other than the memory cell array MAY, specifically, an area in which peripheral circuits including indirect peripheral circuits and direct peripheral circuits are arranged, that is, n-
A p--type well region (Pwell) 2 and an n--type well region (Nwell) 3 are arranged in different regions of the main surface of the p--type semiconductor substrate 1 around the outer periphery of the type well isolation region 3i. An n-channel MISFET forming a peripheral circuit is mainly arranged on the main surface of the p-type well region 2.
A p-channel MISFET forming a peripheral circuit is mainly arranged on the main surface of the n-type well region 3. That is, in the SRAM of this embodiment, the n-type well isolation region 3i is formed on the main surface of the p- type semiconductor substrate 1, and the p- type well region 2M is formed on the main surface of the n- type well isolation region 3i. The double well structure (or the triple well structure including the n-type well region 3) is adopted. In addition, the SRAM of this embodiment has p
A p-type well region 2 and an n-type well region 3 are arranged on the main surface of the --type semiconductor substrate 1 to form a so-called twin well structure.

As shown in FIGS. 3 and 4, the SR
In the memory mat MM of AM, two memory cell arrays M arranged on the left side of the word driver circuit WDR.
AY is arranged on the main surface of one p @-type well region 2M arranged on the main surface of one n @-type well isolation region 3i.
In the outer periphery of the memory cell array MAY (in this case, a region in which the memory cells MC are substantially arranged) is provided, and p
A guard ring region P-GR formed in a plane ring shape is arranged along the contour of the p-type well region 2M in the peripheral region of the -type well region 2M. The guard ring region P-GR supplies a fixed reference voltage Vss to the p-type well region 2M.

Between the two memory cell arrays MAY arranged on the left side of the word driver circuit WDR, a well contact region PWC1 is arranged on the main surface of the p--type well region 2M. The well contact regions PWC1 are arranged in the Y direction at a rate of one for each of the plurality of memory cells MC (for example, one for each of the two memory cells MC), and are arranged in plurality.

Similarly, in the memory mat MM,
The two memory cell arrays MAY arranged on the right side of the word driver circuit WDR are arranged on the main surface of one p--type well region 2M arranged on the main surface of one n--type well isolation region 3i. .. A guard ring region P-GR is arranged in the peripheral region of the p-type well region 2M, and a fixed reference voltage Vss is supplied. Word driver circuit WDR
Between each of the two memory cell arrays MAY arranged on the right side of, the well contact region PWC1 is arranged on the main surface of the p-type well region 2M.

Further, as shown in FIGS. 3 and 4, in the memory cell array MAY, a well contact region PWC2 is arranged between each of the four sub memory cell arrays SMEY. Similar to the well contact region PWC1 described above, the well contact region PWC2 has a ratio of one for each of the plurality of memory cells MC in the Y direction (for example, one for every two memory cells MC). Arranged and arranged in plural.

A well contact region PWC1 arranged between the memory cell array MAY and a well contact region PWC arranged between the sub memory cell arrays SMAY.
2 is a reference voltage V fixed to the p-type well region 2M.
It is arranged for the purpose of supplying ss and stabilizing the potential of the p-type well region 2M.

As shown in FIG. 4, a plurality of p--type well regions 2 and a plurality of n--type well regions 3 are alternately arranged in the X direction in a region of the memory mat MM where the word driver circuits WDR are arranged. It A guard ring region P-GR is arranged in the peripheral region of the p- type well region 2 in which the word driver circuit WDR is arranged, and a guard ring region N-GR is arranged in the peripheral region of the n- type well region 3. It

One memory cell MC arranged in the sub memory cell array SMEY of the memory cell array MAY shown in FIG. 3 has a word line WL and a complementary data line as shown in FIG. 5 (circuit diagram of the memory cell). It is arranged at each intersection with DL. That is, the memory cell MC has the first word line W
It is arranged at the intersection of L1 and the second word line WL2 and the first data line DL1 and the second data line DL2. The memory cell MC includes a flip-flop circuit and two transfer MISFs.
ETQt1 and Qt2. The flip-flop circuit is configured as an information storage unit, and this memory cell M
C stores 1 [bit] of information "1" or "0".

Two transfer MISs of the memory cell MC
Each of the FETs Qt1 and Qt2 connects one semiconductor region to each of the pair of input / output terminals of the flip-flop circuit. The other semiconductor region of the transfer MISFET Qt1 is connected to the first data line DL1 and the gate electrode is connected to the first word line WL1. The other semiconductor region of the transfer MISFET Qt2 is connected to the second data line DL2, and the gate electrode is connected to the second word line WL2. Each of the two transfer MISFEETs Qt1 and Qt2 is an n-channel type.

The flip-flop circuit includes two drive MISFETs Qd1 and Qd2 and two load MISFETs.
ETQp1 and Qp2. MISF for drive
Each of ETQd1 and Qd2 is an n-channel type. Each of the load MISFETs Qp1 and Qp2 is a p-channel type. That is, the memory cell MC of the SRAM of this embodiment is a completely complementary MISFET (so-called full CM).
OS) structure.

The driving MISFET Qd1 and the load M
Each of the ISFETs Qp1 connects their drain regions and their gate electrodes to each other, and has a complementary MISFE
Configure T. Similarly, the drive MISFET Qd2 and the load MISFET Qp2 are connected to each other's drain regions and to each other's gate electrodes.
Configure SFET. The drain regions (input / output terminals) of the drive MISFET Qd1 and the load MISFET Qp1 are connected to one semiconductor region of the transfer MISFET Qt1 and also to the gate electrodes of the drive MISFET Qd2 and the load MISFET Qp2. Drive MISFETQd2, load MISFETQ
The drain regions (input / output terminals) of p2 are M for transfer.
It is connected to one semiconductor region of the ISFET Qt2, and also has a driving MISFET Qd1 and a load MISFET.
It is connected to each gate electrode of Qp1. MIS for drive
The source region of each of the FETs Qd1 and Qd2 is the reference voltage V
It is connected to ss (for example, 0 [V]). MISFE for load
The source regions of TQp1 and Qp2 are the power supply voltage Vcc.
(For example, 5 [V]).

A capacitive element C is formed between a pair of input / output terminals of the flip-flop circuit of the memory cell MC, that is, between two information storage nodes. The capacitor C has one electrode connected to one information storage node and the other electrode connected to the other information storage node. The capacitive element C is basically configured for the purpose of increasing the charge storage amount of the information storage node and enhancing the α-ray soft error resistance. Further, since each electrode of the capacitive element C is connected between the two information storage nodes, the capacity of the capacitive element C is about half that of the case where two capacitive elements are independently formed in each of the two information storage nodes. It can be composed of plane products. That is, since the capacitive element C can reduce the area occupied by the memory cell MC, the integration degree of the SRAM can be improved.

The SRAM having the above-mentioned structure is as follows.
As shown in FIG. 1, FIG. 2A, and FIG. 3, one of a plurality of X decoder circuits XDEC arranged in the Y direction.
The main word line MWL is selected and one of the word driver circuits WDR arranged in the memory mats MM of the memory block MB is selected. By selecting each of the main word line MWL and the word driver circuit WDR, four sets of sub word lines SWL extending to the right side of the word driver circuit WDR of one memory mat MM and four sets of sub word lines extending to the left side SWL is selected. Then, based on the address signal (Y-system address signal) to the selected word driver circuit WDR, one of the four subword lines SWL on either the right side or the left side of the word driver circuit WDR is selected. SWL is selected, two first word lines WL connected to this sub word line SWL and extending one sub memory cell array SMEY
The first and second word lines WL2 are selected. That is, SR
The AM divides the first word line WL1 and the second word line WL2 into a plurality of pieces in the extending direction, and a set of the first word line WL1 and the second word line WL among the plurality of pieces.
2 is a word driver circuit WDR and an X decoder circuit X
The divided word line method selected by DEC is adopted. By adopting the divided word line method, the flow rate of charge / discharge of the selected word line WL can be reduced, so that the power consumption of the SRAM can be reduced.

As shown in FIGS. 2A and 3, the SRAM has a first memory cell array MAY extending from one of the two memory cell arrays MAY arranged at one end of the word driver circuit WDR. The word line WL1 and the second word line WL2 are connected to the word driver circuit WDR via the second sub-word line SWL2, and the other memory cell array M
First word line WL1 and second word line W extending AY
L2 is connected to the word driver circuit WDR via the first sub-word line SWL1. That is, the SRAM has word lines WL divided into memory cell arrays MAY.
Also, a double word line system is adopted in which sub word lines SWL connecting between the plurality of divided word lines WL are arranged. The adoption of the double word line system corresponds to the sub word line SWL, and the word driver circuit WD
Since the resistance value between R and the word line WL can be reduced, the charge / discharge speed of the selected word line WL can be increased and the circuit operation speed of the SRAM can be increased.

The X decoder circuit XDEC, the Y decoder circuit YDEC, the Y switch circuit Y-SW, the sense amplifier circuit SA, the load circuit LOAD, etc. arranged in the peripheral region of the memory cell array MAY of the SRAM constitute a peripheral circuit of the SRAM. .. This peripheral circuit directly or indirectly controls the information writing operation, information holding operation, information reading operation, etc. of the memory cell MC.

Next, the specific structure of the memory cell MC and the memory cell array MAY of the SRAM will be described. The planar structure of the completed state of the memory cell MC is shown in FIG. 7 (plan view), and the planar structure shown for each manufacturing step in the manufacturing process is shown in FIG. 8 and FIG. 9 (plan view), respectively. Memory cell MC
The cross-sectional structure of the completed state is shown in FIG. 6 (a cross-sectional view taken along the line II in FIG. 7).

As shown in FIGS. 6 and 7, the SRAM is mainly composed of the p--type semiconductor substrate 1 made of single crystal silicon as described above. An n--type well isolation region 3i is formed on the main surface of the memory cell array MAY region of the p--type semiconductor substrate 1, and a p--type well region 2M is formed on the main surface of the n--type well isolation region 3i. To be done. In regions other than the region of the memory cell array MAY, as described above, the p − type well region 2 and the n − type well region 3 are formed on the main surface of the p − type semiconductor substrate 1.

18 (impurity concentration distribution diagram of the substrate and the well region), the p--type semiconductor substrate 1, the n--type well isolation region 3i, the p--type well region 2M, the p--type well region 2,
The respective impurity concentrations of the n-type well region 3 are shown. Figure above
The horizontal axis shown in 18 represents the depth [μm] from the main surface of the p − type semiconductor substrate 1, and the vertical axis represents the impurity concentration [atoms / cm ³ ].

As shown in FIG . 18 , p--type semiconductor substrate 1
Is formed with an impurity concentration of about 1 × 10 ¹⁵ [atoms / cm ³ ] and is set to a resistance value of 6 to 12 [Ωcm].

The n--type well isolation region 3i is higher than the impurity concentration of the p--type semiconductor substrate 1 and lower than the impurity concentration of the n--type well region 3, for example, 10 ¹⁵ -1.
The impurity concentration is set to about 0 ¹⁶ [atoms / cm ³ ]. The depth of the pn junction between the n--type well isolation region 3i and the p--type semiconductor substrate 1, that is, the n--type well isolation region 3
The junction depth (xj) of i is set to about 4 to 5 [μm].

P of the main surface of the n--type well isolation region 3i
The -type well region 2M is higher than the impurity concentration of the p-type semiconductor substrate 1, for example, 10 ¹⁶ to 10 ¹⁷ [atoms / cm ³ ].
The impurity concentration on the surface is set to some extent. The junction depth of the p--type well region 2M is the n--type well isolation region because the diffusion of the p-type impurity in the p--type well region 2M is suppressed by the presence of the n-type impurity in the n--type well isolation region 3i. It is shallower than the junction depth of 3i or the diffusion depth of the p-type well region 2, and is set to about 2 [μm], for example. Also, p-
Since the type well region 2M is formed on the main surface of the n-type well isolation region 3i, the impurity concentration on the surface of the p-type well region 2M decreases due to the presence of the n-type impurity in the n-type well isolation region 3i. , P--type well region 2 as shown in FIG.
The impurity concentration on the surface of M is set to be equal to (or higher than) the impurity concentration on the surface of the p--type well region 2 arranged around the outer periphery of the n--type well isolation region 3i.

The n-type well region 3 around the outer periphery of the n-type well isolation region 3i has a surface higher than the impurity concentration of the n-type well isolation region 3i, for example, about 10 ¹⁷ [atoms / cm ³ ]. The impurity concentration of is set. The junction depth of the n-type well region 3 is set to the same depth as the junction depth of the n-type well isolation region 3i.

The p-type well region 2 around the n-type well isolation region 3i is higher than the impurity concentration of the p-type semiconductor substrate 1 and the surface of the p-type well region 2M. The surface impurity concentration is set to be equal to the impurity concentration. The diffusion depth of the p-type well region 2 is regulated by the diffusion rate of the p-type semiconductor substrate 1 having the same conductivity type (diffused into a region where n-type impurities do not exist).
The depth is set deeper than the diffusion depth of the -type well region 2M, for example, about 4 to 5 [μm].

6, 7, and 8 are formed on the main surface of the inactive region of the p--type well region 2M (on the main surface of the n--type well isolation region 3i) in which the memory cell array MAY is arranged .
As shown in, the element isolation insulating film (field silicon oxide film) 4 is formed. Also, the p-type well region 2M
In the main surface portion of the non-active region, that is, under the element isolation insulating film 4, p
The mold channel stopper region 5 is formed. Similarly, n-
An element isolation insulating film 4 and a p-type channel stopper region 5 are formed on the main surface of the inactive region of the p-type well region 2 around the outer periphery of the type well isolation region 3i (see FIG. 16 ). Also,
An element isolation insulating film 4 is formed on the main surface of the inactive region of the n-type well region 3. Compared to the p-type well regions 2 and 2M, the inversion region is less likely to occur in the main surface portion of the inactive region of the n-type well region 3 and element isolation can be reliably performed, thus reducing the number of steps in the manufacturing process. For this purpose, basically no n-type channel stopper region is provided.

One memory cell MC of the SRAM is p
-Configured on the main surface of the active region of the well region 2M. The active region is formed in a defined region surrounded by the element isolation insulating film 4 (particularly the end portion of the element isolation insulating film 4) and the p-type channel stopper region 5. Of the memory cells MC,
As shown in FIGS. 6, 7, 8 and 9 , each of the two driving MISFETs Qd1 and Qd2 has a p-type well region 2M in a region defined by the element isolation insulating film 4. Configured on the main surface. Driving MISFET Qd
Each of 1 and Qd2 mainly comprises a p-type well region 2M, a gate insulating film 6, a gate electrode 7, a source region and a drain region.

The gate length (Lg) directions of the driving MISFETs Qd1 and Qd2 are set to be substantially parallel to each other, and the gate length directions thereof are the X direction (or the word line WL).
(Extending direction) of. The element isolation insulating film 4 (and the p-type channel stopper region 5) is mainly formed in the driving MIS.
The FETs Qd1 and Qd2 are arranged at positions that define the respective gate widths (Lw).

The p--type well region 2M is a driving MIS.
Each of the FETs Qd1 and Qd2 constitutes a channel forming region.

The gate electrode 7 is p- in the active region.
The gate insulating film 6 is formed on the channel forming region of the mold well region 2M. One end side of the gate electrode 7 protrudes in the Y direction on the element isolation insulating film 4 by at least the amount corresponding to the mask alignment margin dimension in the manufacturing process. The other end of the gate electrode 7 of the driving MISFET Qd1 extends in the Y direction through the element isolation insulating film 4 and onto the drain region of the driving MISFET Qd2. Similarly, drive MI
One end side of the gate electrode 7 of the SFET Qd2 projects on the element isolation insulating film 4, and the other end side extends in the Y direction through the element isolation insulating film 4 and onto the drain region of the driving MISFET Qd1.

The gate electrode 7 is formed in the first-layer gate material forming step, and is formed of, for example, a polycrystalline silicon film having a single layer structure. An n-type impurity such as P (or As) that reduces the resistance value is introduced into this polycrystalline silicon film. Since the thickness of the gate electrode 7 having a single-layer structure can be reduced, the surface of the interlayer insulating film serving as the base of the upper conductive layer can be flattened.

Each of the source region and the drain region is composed of an n type semiconductor region 10 having a low impurity concentration and an n + type semiconductor region 11 having a high impurity concentration provided on the main surface thereof. The two types of n-type semiconductor regions 10 and n + -type semiconductor regions 11 having different impurity concentrations are formed on the side of the gate electrode 7 in the gate length direction.
(To be precise, as will be described later, the gate electrode 7, the side wall spacers 9 and the mask 9T covering the side wall spacers 9 are formed in self alignment. That is, each of the source region and the drain region of the driving MISFETs Qd1 and Qd2 has a so-called DDD structure. Each of the source region and the drain region of this DDD structure is formed in the region surrounded by the one-dot chain line shown by DDD in FIG. 8 in the main surface portion of the active region of the p-type well region 2M.

Each of the source region and the drain region is n
The type semiconductor region 10 is formed of P which is an n-type impurity, for example. The n + type semiconductor region 11 is formed of As, which is an n type impurity having a slower diffusion rate than P. In the manufacturing process, when two types of n-type impurities are introduced in the same manufacturing process using the same mask, the n-type semiconductor region 10,
The difference in diffusion distance between the n + type semiconductor regions 11 is governed by the difference in diffusion rate between the two types of n type impurities. In each of the driving MISFETs Qd1 and Qd2 adopting the DDD structure, the substantial dimension in the gate length direction of the n-type semiconductor region 10 between the n + -type semiconductor region 11 and the channel forming region is the same as that of the n-type semiconductor region 10. This corresponds to the dimension obtained by subtracting the diffusion distance of the n + type semiconductor region 11 from the diffusion distance. The n-type semiconductor region 10 has a substantial dimension in the gate length direction smaller than the dimension in the gate length direction of an n-type semiconductor region (17) having a low impurity concentration in the LDD structure, which will be described later, and further has a low LDD structure impurity. Concentration n-type semiconductor region (17)
The impurity concentration is higher than that of. In other words, drive MISFE
In each of TQd1 and Qd2, in the current path between the source region and the drain region, the parasitic resistance added to the n-type semiconductor region 10 is smaller than that of the n-type semiconductor region (17) of the LDD structure, so that the LDD structure described later is used. The drive capability can be made higher than that of each of the transfer MISFETs Qt1 and Qt2 adopting the.

Sidewall spacers 9 are formed on the side walls of the gate electrode 7 in the gate length direction. The sidewall spacer 9 is formed in self-alignment with the gate electrode 7, and is formed of, for example, an insulating film such as a silicon oxide film.

The conductive layer (1 above the gate electrode 7)
An insulating film is formed in the region where 3) is arranged, although no reference numeral is attached. This insulating film is formed mainly for the purpose of electrically separating the lower gate electrode 7 and the upper conductive layer (13) and preventing the surface of the gate electrode 7 from being oxidized. For example, a silicon oxide film. Is formed by.

The memory cell MC is shown in FIG . 7 , FIG. 8 and FIG.
Is arranged in a region defined by a rectangular shape in a plan view surrounded by a chain double-dashed line with a reference numeral MC. The planar shape of one driving MISFET Qd1 of the memory cell MC is configured to be point-symmetric with respect to the central point CP (intersection point of the rectangular diagonal) of the memory cell MC with respect to the planar shape of the driving MISFET Qd2. The center point CP is a point that is virtually drawn for convenience of description, and is not a point that is actually formed as a pattern in the memory cell MC of the SRAM.

As shown in FIGS . 7 , 8 and 9 , in the memory cell array MAY or the sub-memory cell array SMAY, the driving MISFET Qd1 of the memory cell MC,
The planar shape of each Qd2 is the driving MISFETQ.
MISFETQ for driving the other memory cell MC with respect to the X1-X3 axis or the X2-X4 axis between the other memory cell MC adjacent in the X direction that matches the gate length direction of d.
The plane shapes of d1 and Qd2 are line-symmetrical.
Similarly, the driving MISFET Qd1 of the memory cell MC,
The planar shape of each Qd2 is the driving MISFETQ.
MISFETQ for driving the other memory cell MC with respect to the X1-X2 axis or the X3-X4 axis between the other memory cell MC adjacent in the Y direction that matches the gate width direction of d.
The plane shapes of d1 and Qd2 are line-symmetrical.
That is, the driving MISFET Qd of the memory cell MC is X
The memory cells MC in the memory cell MC array are formed in line symmetry in the Y direction and the Y direction.

Of the driving MISFETs Qd of the memory cells MC arranged in the X direction, the mutually facing source regions of the driving MISFETs Qd of the adjacent memory cells MCs are integrally formed (see FIG. 12 ). That is,
Driving MISFETQ of one adjacent memory cell MC
MIS for driving the other memory cell MC in the source region of d
MISFET for driving, which constitutes the source region of FET Qd
The area occupied by the source region of Qd is reduced. In addition, the source region of the driving MISFET Qd of one memory cell MC and the driving MIS of the other memory cell MC facing the source region.
An element isolation insulating film 4 is provided between the FET Qd and the source region.
(And the p-type channel stopper region 5) is not interposed, the memory cell M corresponding to the element isolation insulating film 4 is provided.
The area occupied by C can be reduced.

Two transfer MISs of the memory cell MC
Each of the FETs Qt1 and Qt2 is shown in FIG. 6, FIG. 7 , FIG.
As shown in FIG. 9 , in the region defined by the element isolation insulating film 4, the main surface of the p--type well region 2M is formed. Each of the transfer MISFETs Qt1 and Qt2 is
The p-type well region 2M, the gate insulating film 12, the gate electrode 13, the source region and the drain region are mainly constituted.

The respective gate length (Lg) directions of the transfer MISFETs Qt1 and Qt2 are set substantially parallel to each other, and the respective gate length directions are set in the Y direction (or the extending direction of the complementary data line DL). Match. That is, the transfer MI
The gate length direction of each of the SFETs Qt1 and Qt2 and the gate length direction of the driving MISFETs Qd1 and Qd2 intersect at a substantially right angle. The element isolation insulating film 4 (and the p-type channel stopper region 5) is mainly formed by the transfer MISFET Qt.
The gate widths (Lw) of 1 and Qt2 are defined.

The p--type well region 2M is a transfer MIS.
The respective channel forming regions of the FETs Qt1 and Qt2 are formed.

The gate electrode 13 is p in the active region.
The gate insulating film 12 is formed on the channel forming region of the -type well region 2M. The gate electrode 13 is formed in the second layer gate material forming step, and for example, the polycrystalline silicon film 13A, the polycrystalline silicon film 13B, and the refractory metal silicide film 13 are formed.
Each of the Cs is sequentially laminated to form a three-layer laminated structure (so-called polycide structure). An n-type impurity such as P (or As) that reduces the resistance value is introduced into the lower polycrystalline silicon film 13A. An n-type impurity such as P (or As) that reduces the resistance value is introduced into the polycrystalline silicon film 13B of the intermediate layer.
The upper refractory metal silicide film 13C is formed of, for example, WSix (x is 2). In this gate electrode 13, the specific resistance value of the upper refractory metal silicide film 13C is smaller than that of each of the lower polycrystalline silicon film 13A and the intermediate polycrystalline silicon film 13B, so that the signal transmission speed can be increased. Can be achieved. Also,
The gate electrode 13 has a laminated structure of a polycrystalline silicon film 13A, a polycrystalline silicon film 13B, and a refractory metal silicide film 13C, and can increase the total cross-sectional area and the resistance value. Higher speed can be achieved. The refractory metal silicide film 13C, which is the upper layer of the gate electrode 13, is formed of MoSix, TiSix, or TaSi in addition to the WSix.
x may be used.

The gate width dimension of the gate electrode 13 is as shown in FIG.
As shown in FIG. 8 , the gate width of the gate electrode 7 of the driving MISFET Qd is smaller than that of the gate electrode 7. That is, the transfer MISFETQt is the drive MISFETQt.
Since the drivability is smaller than that of d and the β ratio of the memory cell MC can be increased, the memory cell MC can stably hold the information stored in the information storage node.

Each of the source region and the drain region is
As shown in FIG. 6, the n + type semiconductor region 18 having a high impurity concentration and the n type semiconductor region 17 having a low impurity concentration provided between the n + type semiconductor region 18 and the channel forming region are mainly configured. Of the two types having different impurity concentrations, the n-type semiconductor region 17 is formed on the side portion of the gate electrode 13 in the gate length direction in self-alignment with the gate electrode 13.
The n-type semiconductor region 17 is formed of an n-type impurity, such as P, whose impurity concentration gradient is gentle at the pn junction with the channel formation region. The n + type semiconductor region 18 is formed on the side portion of the gate electrode 13 in the gate length direction with respect to the sidewall spacer 16 (actually, the driving MISFE described above is used.
Like TQd, it is self-aligned (to the mask that covers the sidewall spacers 16). The n + type semiconductor region 18 is formed of an n type impurity such as As that can make the depth of the junction with the p − type well region 2M (junction depth) shallow. That is, each of the transfer MISFETs Qt1 and Qt2 has an LDD structure. Since each of the transfer MISFETs Qt1 and Qt2 adopting this LDD structure can relax the electric field strength in the vicinity of the drain region, it is possible to reduce the amount of hot carriers generated and to reduce the change in the threshold voltage over time.

The sidewall spacers 16 are formed on the sidewalls of the gate electrode 13 in a self-aligned manner.
The sidewall spacers 16 are formed of an insulating film such as a silicon oxide film.

An insulating film 15 is formed on the gate electrode 13. The insulating film 15 is mainly the lower layer gate electrode 1
3. The upper conductive layer (23) is electrically separated from each other and is formed of, for example, a silicon oxide film. The insulating film 15 is formed to have a larger film thickness than the insulating film provided on the gate electrode 7.

As shown in FIG. 8 , the transfer MISFE is used.
One source region or drain region of TQt1 is formed integrally with the drain region of the driving MISFET Qd1. Transfer MISFETQt1, drive MISFETQ
Each of d1 is in each gate length direction (or gate width direction)
, The active region of the driving MISFET Qd1 is oriented in the X direction (direction coinciding with the gate length direction), and the transfer MISF is centered around the integrally formed portion.
The active regions of the ETQt1 are formed in the Y direction (direction matching the gate length direction). That is, transfer M
Each of the active regions of the ISFET Qt1 and the driving MISFET Qd1 is formed in a substantially L shape in plan view. Similarly, one source region or drain region of the transfer MISFET Qt2 is integrally formed with the drain region of the drive MISFET Qd2. That is, the transfer MIS
Each of the active regions of the FET Qt2 and the driving MISFET Qd2 is configured to have a substantially L-shaped planar shape. The element isolation insulating film 4 (and the p-type channel stopper region 5) includes the transfer MISFET Qt and the driving MIS that are integrally formed.
The FET Qd is formed at a position that defines this region along the outer periphery thereof, that is, the periphery of the above-mentioned L-shaped active region.

The plane shapes of the transfer MISFETs Qt1 and Qt2 are point-symmetrical with respect to the center point CP in the memory cell MC, similar to the relationship between the drive MISFETs Qd1 and Qd2. That is, as shown in FIG. 8 , the memory cell MC has a transfer MI.
SFET Qt1 and driving MISF integrated therewith
Each of the ETQd1, the transfer MISFETQt2, and the drive MISFETQd2 integrated with the ETQd1 is the center point CP.
It is configured with point symmetry with respect to (point-symmetrical shape in memory cell). The memory cell MC includes a transfer MISFET Qt1, a drive MISFET Qd1, and a transfer MISFET Qt.
2 and the driving MISFET Qd2 have plane shapes,
Not the unbalanced shape but the same shape. In the memory cell MC, the driving MISFETs Qd1 and Qd2 are arranged between the transfer MISFETs Qt1 and Qt2, and the driving MISFETs Qd1 and Qd2 are arranged to face each other. That is, the transfer M of the memory cell MC
The ISFET Qt1, the driving MISFET Qd1, the transfer MISFET Qt2, and the driving MISFET Qd2 are separated only by the element isolation insulating film 4 and the p-type channel stopper region 5 which are arranged between the driving MISFETs Qd1 and Qd2, respectively. The spacing dimension is limited only by the width dimension of the insulating film 4.

As shown in FIGS . 7 , 8 and 9 , in the memory cell array MAY or the sub memory cell array SMAY, the transfer MISFETQt1 of the memory cell MC,
The plane shape of each Qt2 is the transfer MISFETQ.
The transfer MISFETQ of the other memory cell MC with respect to the X1-X2 axis or the X3-X4 axis between the other memory cell MC adjacent in the Y direction that coincides with the gate length direction of t.
The plane shapes of t1 and Qt2 are line-symmetrical.
Similarly, the transfer MISFET Qt1 of the memory cell MC,
The plane shape of each Qt2 is the transfer MISFETQ.
The transfer MISFETQ of the other memory cell MC with respect to the X1-X3 axis or the X2-X4 axis between another memory cell MC adjacent in the X direction that matches the gate width direction of t.
The plane shapes of t1 and Qt2 are line-symmetrical.
That is, the transfer MISFET Qt of the memory cell MC is X
The memory cells MC in the memory cell MC array are formed in line symmetry in the Y direction and the Y direction.

Of the transfer MISFETs Qt of the memory cells MC arranged in the Y direction, the other drain or source regions of the transfer MISFETs Qt of the adjacent memory cells MC facing each other are integrally formed (see FIG. 12 ). That is, one of the adjacent memory cells M
C transfer MISFET Qt has the other drain region or source region at the other memory cell MC transfer MISFE
Constitutes the other drain region or source region of TQt,
The area occupied by the other drain region or source region of the transfer MISFET Qt can be reduced. Further, the other drain region or source region of the transfer MISFET Qt of one memory cell MC and the other memory cell MC facing the other drain region or source region.
Since the element isolation insulating film 4 is not interposed between the other drain region or source region of the transfer MISFET Qt, the memory cell M corresponding to the element isolation insulating film 4 is provided.
The area occupied by C can be reduced.

MISFET for transfer of the memory cell MC
Qt1, the gate electrode 13 of each of Qt2, the 7,
As shown in FIGS. 8 and 9 , it is connected to the word line (WL) 13 in the X direction that matches the gate width direction. The word line 13 is formed integrally with the gate electrode 13 and is formed of the same conductive layer. Of the memory cells MC,
The first word line (WL1) 13 is connected to the gate electrode 13 of the transfer MISFET Qt1, and the first word line 13 extends on the element isolation insulating film 4 in a substantially straight line in the X direction. The second word line (WL2) 13 is connected to the gate electrode 13 of the transfer MISFET Qt2, and the second word line 1
3 extends substantially linearly in the X direction. That is, in one memory cell MC, two first word lines 13 and two second word lines 13 that are separated from each other and extend in parallel in the same X direction are arranged. In the memory cell array MAY, the planar shapes of the first word line 13 and the second word line 13 are line-symmetric in the X direction with respect to the X1-X3 axis and the X2-X4 axis described above. The planar shape of the first word line 13 and the second word line 13 is X1-X2.
The axis and the X3-X4 axis are line-symmetrical in the Y direction.

The first word line (WL1) 13 is shown in FIG.
And as shown in FIG. 8 , the MIS for driving the memory cell MC
The gate electrode 7 of the FET Qd1 intersects with a portion protruding above the element isolation insulating film 4 in a direction corresponding to the gate width direction of the gate electrode 7. Similarly, the second word line (WL2) is connected to the drive MI.
The gate electrode 7 of the SFET Qd2 intersects with a portion protruding above the element isolation insulating film 4 in a direction coinciding with the gate width direction of the gate electrode 7.

Also, the first word line (WL1) 13 and the second word line (WL2) 1 arranged in the memory cell MC.
A reference voltage line (source line: Vss) 13 is arranged between each of the three. One reference voltage line 13 is arranged in the memory cell MC, and the driving MISFET of the memory cell MC.
It is configured as a common source line for Qd1 and Qd2.
The reference voltage line 13 is formed of the same conductive layer as the word line 13, is separated from the word line 13, and extends on the element isolation insulating film 4 in a substantially straight line in the X direction. In the memory cell array MAY or the sub memory cell array SMEY, the planar shape of the reference voltage line 13 is X1-X3 axis, X2
It is configured to be line-symmetric in the X direction with respect to each of the −X4 axes. The planar shape of the reference voltage line 13 is X1-X2.
The axis and the X3-X4 axis are line-symmetrical in the Y direction.

The reference voltage line 13 is, as shown in FIGS. 6 and 8 , a driving MISFET Qd for the memory cell MC.
On the element isolation insulating film 4 between 1 and Qd2,
Each of the driving MISFETs Qd1 and Qd2 intersects with a portion of the gate electrode 7 protruding in a direction coinciding with the gate width direction.

The reference voltage line 13 is shown in FIG. 6, FIG. 7 and FIG.
8 , the driving MISFETs Qd1 and Qd2 are connected to the respective source regions (n + type semiconductor regions 11). The reference voltage line 13, in particular, as shown in FIG.
Connection is made through a connection hole 14 formed in the insulating film 12 formed in the same step as the step of forming the gate insulating film 12 of TQt. The reference voltage line 13 has a laminated structure of three layers as described above, and the connection hole 14 is formed in the polycrystalline silicon film 13A after forming the polycrystalline silicon film 13A in the lower layer of the reference voltage line 13. . That is, the reference voltage line 13 is
The lower polycrystalline silicon film 13A and the lower insulating film 1
The polycrystalline silicon film 13B of the intermediate layer is directly connected to the source region through the connection hole 14 formed in No. 2, and the refractory metal silicide film 13 of the upper layer is connected through the polycrystalline silicon film 13B of the intermediate layer.
C is connected to the source region.

MISFET for driving this reference voltage line 13
The connection structure of Qd to the source region will be described later in the description of the manufacturing process, and the order of the forming steps will be described later. Since the connection hole 14 is formed,
When performing the photolithography technique and the etching technique, the surface of the gate insulating film 12 of the transfer MISFET Qt can be protected by the lower polycrystalline silicon film 13A. That is, since the film quality of the gate insulating film 12 of the transfer MISFET Qt can be prevented from being deteriorated, the withstand voltage of the gate insulating film 12 can be improved.

Further, the driving MISFE of the reference voltage line 13
The connection structure of TQd to the source region is such that the direct connection between the source region and the refractory metal silicide film 13C in the upper layer is abolished, and the polycrystalline silicon film 13B in the intermediate layer is interposed between the source region and the source region. The contact resistance value with the reference voltage line 13 can be reduced. Polycrystalline silicon film 13B as an intermediate layer of the reference voltage line 13
For the purpose of reducing the contact resistance value, a large amount of impurities for reducing the resistance value are introduced as compared with the lower polycrystalline silicon film 13A. On the contrary, the polycrystalline silicon film 1 under the reference voltage line 13
3A is an intermediate polycrystalline silicon film 13 for the purpose of improving the withstand voltage of the gate insulating film 12 of the transfer MISFET Qt.
Compared to B, less impurities that reduce the resistance value are introduced.

As shown in FIGS. 6, 7 and 9 , the capacitive element C arranged in the memory cell MC mainly comprises a first electrode 7, a dielectric film 21, and a second electrode 23, which are sequentially laminated. Configured. That is, the capacitive element C is stacked.
Composed of structure. Two capacitance elements C are mainly arranged in the memory cell MC, and these two capacitance elements C are connected and arranged in parallel between the information storage nodes of the memory cell MC.

The first electrode 7 of the capacitive element C is a driving MI.
It is composed of a part of the gate electrode of the SFET Qd (polycrystalline silicon film formed in the first layer gate material forming step). That is, one driving MISFET Qd of the memory cell MC
The one gate electrode 7 constitutes the first electrode 7 of one of the two capacitive elements C. The other driving MISFET Qd2
Of the gate electrode 7 constitutes the first electrode 7 of the other capacitive element C.

The dielectric film 21 is formed on the first electrode (gate electrode) 7. The dielectric film 21 is formed in a region other than the first electrode 7, but on the first electrode 7, a region defined by each of the first word line (WL1) 13 and the reference voltage line 13, and A region defined by each of the two word lines (WL2) 13 and the reference voltage line 13 is used as a substantial dielectric film 21 of the capacitive element C. This dielectric film 21
Is formed of, for example, a silicon oxide film.

The second electrode 23 is formed on the first electrode 7 with the dielectric film 21 interposed therebetween. Similar to the dielectric film 21, the second electrode 23 has a region defined by each of the word line (WL) 13 and the reference voltage line 13, which is used as a substantial second electrode 23 of the capacitive element C. The second electrode 23 is formed in the third layer gate material forming step, and is formed of, for example, a single-layer polycrystalline silicon film. An n-type impurity such as P (or As) that reduces the resistance value is introduced into this polycrystalline silicon film.

That is, the capacitive element C is the driving MIS.
The gate electrode 7 of the FET Qd1 is used as the first electrode 7, and the capacitive element C is arranged in the region of the driving MISFET Qd1.
The gate electrode 7 of the driving MISFET Qd2 is replaced with the first electrode 7
And the capacitive element C arranged in the region of the driving MISFET Qd2. The second electrode 2 of this capacitive element C
3, which will be described later, is also configured as the gate electrode 23 of the load MISFET Qp. The second electrode 23 of the capacitive element C is connected to the drain region of the load MISFET Qp (actually the n-type channel forming region 26N) and the transfer MISF.
One semiconductor region of ETQt, driving MISFET Qd
Is also configured as a conductive layer (intermediate conductive layer or coupling conductive layer) 23 that connects the drain region of the gate electrode 7 of the driving MISFET Qd.

The second electrode 23 of the one capacitance element C arranged in the region of the driving MISFET Qd1 has the driving M.
Drain region (11) of ISFET Qd1, transfer MI
One semiconductor region (18) of SFETQt1, drive M
It is connected to each of the gate electrodes 7 of the ISFET Qd2.
These connections connect the second electrode 23 of the capacitive element C to the driving M
The conductive layer 23 is formed in the same layer as and integrally with the second electrode 23, which is drawn out in the X direction that coincides with the gate length direction of the ISFET Qd1. The conductive layer 23 includes the insulating film (the same layer as the dielectric film 21) 21, the connection hole (opening) 22 formed by removing the insulating film 12 and the like, the drain region (11), one semiconductor region (18), It is connected to each of the gate electrodes 7. Similarly, the driving MISFET Q
The second electrode 2 of the other capacitive element C arranged in the region of d2
3 is a drain region (1 of the driving MISFET Qd2
1), one semiconductor region (18) of the transfer MISFET Qt2, and the gate electrode 7 of the drive MISFET Qd1. These connections are the second of the capacitive element C.
This is performed by the conductive layer 23 in which the electrode 23 is drawn out in a direction that coincides with the gate length direction of the driving MISFET Qd2. The conductive layer 23 is connected to the drain region (1
1), one of the semiconductor regions (18) and the gate electrode 7 are connected.

The connection structure between one of the semiconductor regions (18) of the transfer MISFET Qt, the drain region (11) of the driving MISFET Qd, the gate electrode 7 of the driving MISFET Qd and the conductive layer 23 is shown in FIG. The details are shown in the enlarged sectional view). As shown in FIG. 17 , the connection hole 2
In the region whose periphery is defined by 2, an n @ + type semiconductor region 21N having a high impurity concentration is formed in the main surface of the p @-type well region 2M. As will be described later, the n + type semiconductor region 21N is formed by introducing an n type impurity using an etching mask for forming the connection hole 22 in the insulating film 21 as an impurity introduction mask.
Although there is some lateral diffusion, it has a planar shape that is almost the same as the planar shape of the connection hole 22. The gate electrode 7
The gate electrode 7 serves as an impurity introduction mask depending on the condition of impurity introduction, so that the n + -type semiconductor region 21N is not formed under the gate electrode 7.

Each of the n + type semiconductor regions 11 and 18 is formed with a junction depth of, for example, about 0.2 to 0.3 [μm] in the present embodiment.
1N is a junction depth deeper than the junction depth of each of the n + type semiconductor regions 11 and 18, for example, 0.35 to 0.45 [μ
m] is set. That is, the n + type semiconductor region 21
N is from the end of the connection hole 22 of the n + type semiconductor region 11 or 18 (p − type semiconductor substrate 1) to the n + type semiconductor region 1
1 or 18 and the p-type semiconductor substrate 1 are formed to a depth enough to capture the crystal defects generated across the pn junction. Crystal defects mainly occur due to the volume contraction of the conductive layer 23, the difference in thermal expansion coefficient between the conductive layer (polycrystalline silicon film) 23 and the insulating film (silicon oxide film), etc. In the cell MC, n + type semiconductor regions 11 and 18
For driving MISF at the connection between each of the above and the conductive layer 23.
Since the volumetric shrinkage of the gate electrode (polycrystalline silicon film) 7 of ETQd is also added and crystal defects frequently occur, the arrangement of the n + type semiconductor region 21N is effective.

Further, as shown in FIG. 1, in the memory cell MC, a similar connection structure has a transfer MISFETQ.
Intermediate conductive layer 2 when connecting complementary data line (DL) 33 to n + type semiconductor region 18 which is the other semiconductor region of t
Since it exists at the connection portion between the n-type semiconductor regions 3 and 3, the n + type semiconductor region 21N is also formed at this connection portion. In other words, in the SRAM manufacturing process described later, the transfer MIS is used.
N + which is one of the semiconductor regions of the FETQt and the other of the FETQt
The connection hole 22 is formed on the surface of the semiconductor region 18 in the same manufacturing process.
Are formed, the n + type semiconductor regions 2 are formed in the semiconductor regions of the transfer MISFET Qt, respectively.
1N is formed.

In the memory cell array MAY or the sub memory cell array SMEY, the capacitive elements C of the memory cells MC arranged in the X direction are X1 shown in FIGS.
The plane shape of the second electrode 23 (and the conductive layer 23) is line-symmetrical with respect to the −X3 axis or the X2-X4 axis. In addition, the capacitive elements C of the memory cells MC arranged in the Y direction
Is the above-mentioned drive MISFET Qd and transfer MISF.
Unlike the line-symmetrical arrangement of ETQt, the planar shape of the second electrode 23 is non-line-symmetrical. That is, the second capacitance element C of each of the plurality of memory cells MC arranged in the X direction is
The capacitive element C of the plurality of memory cells MC arranged in the X direction of the next stage adjacent in the Y direction with respect to the arrangement of the electrodes 23.
Is the same as the preceding second electrode 23, the plane shape of the second electrode 23 is linearly symmetrical in the X direction, and the plan shape of the second electrode 23 is relative to the array of the preceding memory cells MC. It is constructed by shifting in the X direction by one memory cell MC (one memory cell pitch). In the memory cell array MAY, the capacitive element C of the aforementioned memory cell MC
The arrangement of the second electrodes 23 (and the conductive layers 23) will be described later. The plane shape of the power supply voltage line (Vcc: 26P) and the load MISFET Qp formed mainly on the upper layer of the second electrode 23 is in the Y direction. On the other hand, it is composed of non-line symmetry, so it is composed of non-line symmetry.

Two load MISs of the memory cell MC
Each of the FETs Qp1 and Qp2 is formed on the region of the driving MISFET Qd, as shown in FIGS . 6, 7, and 9 . The load MISFET Qp1 is a drive MISFET.
Loaded MISFET Qp2 formed on the region of Qd2
Is formed on the driving MISFET Qd1. The load MISFET Qp has a so-called SOI structure (or TFT structure). MISFET for load Qp1, Qp2
Of the driving MISFETs Qd1 and Qd2 are arranged such that their gate length directions are substantially orthogonal to each other in a direction coinciding with the gate length directions of the driving MISFETs Qd1 and Qd2. This load MISFET Qp1, Qp2
Of the n-type channel forming region 26N, the gate insulating films 24 and 24G, the gate electrode 23, and the source region 26P.
And a drain region 26P.

The gate electrode 23 is composed of the second electrode (polycrystalline silicon film formed in the third layer gate material forming step) 23 of the capacitive element C. That is, the drive MISF
The second of the one capacitive element C arranged in the region of ETQd1
The electrode 23 is the gate electrode 23 of the load MISFET Qp2.
Make up. The second electrode 23 of the other capacitive element C arranged in the region of the driving MISFET Qd2 is the load MISF.
The gate electrode 23 of ETQp1 is formed.

As shown in FIG. 17 , the load MISF.
ETQp gate electrode 23 (conductive layer 23, intermediate conductive layer 2
(Including all 3), a part of the film thickness of the gate electrode 23 is oxidized (or nitrided) from the surface after patterning,
Corner of surface (corner between upper surface of gate electrode 23 and side surface of patterned surface, reference numeral 2 in FIG. 17)
The cross-sectional shape of the portion 23C (shown with 3C) is relaxed from a sharp projecting shape to a rounded cross-sectional shape. Since the oxidation of the surface of the gate electrode 23 does not sufficiently improve the cross-sectional shape to the extent that a native silicon oxide film having a film thickness of 1 to 3 [nm] is formed, the surface of the gate electrode 23 is naturally oxidized. It is performed to such an extent that a silicon oxide film having a thickness larger than that of the silicon film can be formed. In addition, the gate electrode 23
Is necessary to remain as a conductor region, the oxidation from the surface of the gate electrode 23 is limited to a part of the film thickness of the gate electrode 23. That is, the oxidation of the surface of the gate electrode 23 is
It is performed to the extent that a silicon oxide film having a film thickness equal to or larger than that of the natural silicon oxide film can be formed, and is limited to a part of the film thickness of the gate electrode 23. In the SRAM of this embodiment, oxidation is performed so that a silicon oxide film having a film thickness of about 5 to 15 [nm] can be formed on the surface of the gate electrode 23.

As shown in FIG. 17 , the load MISFE is used.
The gate electrode 23 of TQp is on the gate electrode 7 of the driving MISFET Qd, on the word line 13 having a higher position than the gate electrode 7, on the reference voltage line (Vss) 13, and in the p-type well region 2M. They are arranged over regions having different heights from the main surface. When the end portion of the gate electrode 23 is located in the stepped region of the base shape, the gate electrode 23
Patterning is performed by anisotropic etching for the purpose of microfabrication, the corner portion 23 of the surface of the gate electrode 23
The cross-sectional shape of C is formed to have a sharp protruding shape with an acute angle. Therefore, the above-mentioned gate electrode 2
Of the gate electrode 23 based on the oxidation of part of the film thickness of the surface of No. 3
The improvement of the cross-sectional shape of the corner portion 23C of the surface of the SRAM is particularly the SRAM having the load MISFET Qp having the SOI structure.
Is effective in.

The improvement of the cross-sectional shape of the corner portion 23C on the surface of the gate electrode 23 can reduce the electric field concentration in the area of the corner portion 23C, and the gate insulating film 24 formed along the corner portion 23C. The film quality can be improved, and as a result, the withstand voltage of the gate insulating film 24 can be improved.

The gate electrode 23 (similarly to the conductive layer 2
3, a side wall spacer 24S is formed on the side surface of the surface of each of the intermediate conductive layers 23). The sidewall spacer 24S is formed only on the side surface of the gate electrode 23 by depositing a silicon oxide film by, for example, a CVD method, and anisotropically etching the silicon oxide film by an amount corresponding to the deposited film thickness. .. This sidewall spacer 24S
Can improve the cross-sectional shape of the corner portion 23C on the surface of the gate electrode 23 described above.
The withstand voltage of 4 can be improved.

The gate insulating film 24 is the SR of this embodiment.
In the load MISFET Qp of AM, the gate electrode 2
3 has a three-layer structure in which a natural silicon oxide film (not shown), a silicon oxide film 24G, and a silicon oxide film 24F are sequentially laminated from the surface of No. 3. The natural silicon oxide film below the gate insulating film 24 is the same in the SRAM manufacturing process from the step of depositing the polycrystalline silicon film that is the gate electrode 23 to the step of forming the silicon oxide film 24F above the gate insulating film 24. It can be eliminated if it is carried out in a vacuum system, but it is almost certainly formed if there is an opening to the atmosphere in the middle. The natural silicon oxide film is formed with a very thin film thickness as described above. The intermediate silicon oxide film 24G is the gate electrode 23 described above.
For the purpose of improving the cross-sectional shape of the corner portion 23C on the surface of, the above-mentioned film thickness is formed. The upper silicon oxide film 24F is
It is formed of a silicon oxide film deposited by the CVD method, for example, 50
It is formed with a film thickness of about 70 [nm].

As the gate insulating film 24, a silicon nitride film may be used instead of the intermediate silicon oxide film 24G. That is, in this case, the improvement of the cross-sectional shape of the corner portion 23C on the surface of the gate electrode 23 is performed by nitriding. Further, the gate insulating film 24 may be mainly composed of the silicon oxide film 24F by removing the intermediate silicon oxide film 24G and then depositing the silicon oxide film 24F by the CVD method in the removed region. . In this case, the natural silicon oxide film is very thin, and the gate insulating film 2 has the same thickness as the silicon oxide film 24F.
4 is almost determined, and the silicon oxide film 24
Since F can be formed with a uniform film thickness without being affected by the crystal grains of the underlying gate electrode (polycrystalline silicon film) 23, the controllability of the film thickness of the gate insulating film 24 is extremely high.

The n-type channel forming region 26N is formed on the gate electrode 23 with the gate insulating film 24 interposed therebetween. n
The type channel formation region 26N is arranged so that its gate length direction substantially coincides with the direction in which it coincides with the gate width direction of the driving MISFET Qd. The n-type channel formation region 26N is
It is formed in the gate material forming step of the fourth layer and is made of, for example, a polycrystalline silicon film. MISF for load is used for the polycrystalline silicon film.
An n-type impurity (for example, P) that sets the threshold voltage of ETQp to the enhancement type is introduced. MIS for load
The FET Qp can sufficiently supply the power supply voltage Vcc to the information storage node during operation (ON operation), and can stably hold information. In addition, the load MISFET Qp is
During the FF operation), since the supply of the power supply voltage Vcc to the information storage node can be cut off almost certainly, the standby current amount can be reduced and the power consumption can be reduced. This point, MISF for load
ETQp is different from that of the high resistance element for load (a minute current always flows through the high resistance element for load).

The source region 26P is a p-type conductive layer (26P) integrally formed on one end side (source region side) of the n-type channel forming region 26N and formed of the same conductive layer.
Composed of. That is, the source region (p-type conductive layer) 26
P is formed of a polycrystalline silicon film formed in the fourth layer gate material forming step, and a p-type impurity (for example, BF ₂ ) is introduced into the polycrystalline silicon film. The source region 26P is configured in a region surrounded by a dashed line with reference numeral 26P in FIG. 9 (a part is configured as the power supply voltage line 26P). The drain region 26P is integrally formed on the other end side (drain side) of the n-type channel forming region 26N, and like the source region 26P, is formed of a p-type conductive layer (26P) formed of the same conductive layer. It The drain region 26P is formed within a region surrounded by a chain line with a reference numeral 26P. That is, in the manufacturing process described later, the p-type impurity forming the source region and the drain region 26P is introduced into the region 26P surrounded by the alternate long and short dash line, and the other region is formed as the n-type channel forming region 26N. It

The drain region 26P of the load MISFET Qp1 is connected to one semiconductor region of the transfer MISFET Qt1, the drain region of the drive MISFET Qd1 and the gate electrode 7 of the drive MISFET Qd2. Similarly, the drain region 26P of the load MISFET Qp2 is connected to one semiconductor region of the transfer MISFET Qt2, the drain region of the drive MISFET Qd2, and the gate electrode 7 of the drive MISFET Qd1. These connections are made through the conductive layer 23.

The drain region 26P of the load MISFET Qp is separated from the gate electrode 23 via the n-type channel forming region 26N. In other words, the load MIS
In the FET Qp, the gate electrode 23 and the drain region 26P are separated without overlapping. That is, the load MISF
The drain region 26P side of ETQp has an offset structure. Load MISFETQ with this offset structure
p is an n-type channel forming region 26N−drain region 26P
The breakdown withstand voltage can be improved. That is, this offset structure has the drain region 26P and the gate electrode 2
3 is separated from the n-type channel forming region 26N in which the charge is induced by the drain region 26P.
The breakdown voltage of the pn junction between the n-type channel forming region 26N and the n-type channel forming region 26N can be improved. In the case of this embodiment, the load M
The ISFET Qp is composed of an offset dimension (separation dimension) of about 0.6 [μm] or more.

As described above, the conductive layer 23 is the capacitive element C.
Of the second electrode 23 (polycrystalline silicon film formed in the third layer gate material forming step). Conductive layer 2
3 is formed of the same conductive layer as the gate electrode 23 of the load MISFET Qp. The conductive layer 23 passes through a connection hole 25 formed in the interlayer insulating film 24 and is used as an upper load MISFE.
It is connected to the p-type drain region 26P of TQp. Also,
As described above, the conductive layer 23 is connected to the one semiconductor region (18) of the transfer MISFET Qt, the drain region (11) of the driving MISFET Qd, and the gate electrode 7 through the connection hole 22. Conductive layer 23 configured in this way
Corresponds to the film thickness of the conductive layer 23 and the dimension between the position of the connection hole 25 on the upper side of the conductive layer 23 and the position of the connection hole 22 on the lower side of the conductive layer 23, and is the drain region 26 of the load MISFET Qp.
The other end of P, the one semiconductor region (18) of the transfer MISFET Qt, and the drain region (11) of the driving MISFET Qd can be separated from each other. Since the conductive layer 23 is formed of a polycrystalline silicon film into which an n-type impurity is introduced, each of the one semiconductor region (18) and the drain region (11) of the p-type impurities forming the p-type drain region 26P is formed. The diffusion distance to the conductive layer 23 can be increased. That is, the conductive layer 2
3 is a transfer MISFETQt, a drive MISFETQ
In each channel formation region of d, the load MISFETQ
The diffusion of p-type impurities in the p drain region 26P is reduced, and the transfer MISFET Qt and the drive MISFE are reduced.
It is possible to prevent the variation of each threshold voltage of TQd. The conductive layer 23 is the gate electrode 2 of the load MISFET Qp.
3. Since the second electrode 23 of the capacitive element C is formed of the same conductive layer (the same manufacturing process), the number of conductive layers can be structurally reduced, and the number of manufacturing steps in the manufacturing process can be reduced.

As shown in FIGS. 6, 7 and 9 , the source region (p-type conductive layer 26) of the load MISFET Qp.
A power supply voltage line (Vcc) 26P is connected to P). The power supply voltage line 26P is the p-type conductive layer 26P which is the source region.
And the same conductive layer. That is, the power supply voltage line 26P is formed of the polycrystalline silicon film formed in the fourth layer gate material forming step, and p-type impurities (for example, BF ₂ ) for reducing the resistance value are introduced into this polycrystalline silicon film. To be done.

Two power supply voltage lines (Vcc) 26P are arranged in the memory cell MC. These two power supply voltage lines 26
In the memory cell array MAY or the sub memory cell array SMEY, Ps are separated from each other and extend substantially parallel to the same X direction. One power supply voltage line 26P arranged in the memory cell MC is formed integrally with the source region of the load MISFET Qp2, and the first word line (WL1) 1
3 extends along a direction coinciding with the extending direction.
The other power supply voltage line 26P is connected to the load MISFET Qp1.
Of the second word line (WL
2) Extend on 13 along a direction coinciding with the extending direction.

As shown in FIGS. 7 and 9 , in the memory cell MC, one power supply voltage line 26P extends in the X direction and is complementary to the other semiconductor region (18) of the transfer MISFET Qt1. A connection portion (intermediate conductive layer 2 described later) with the first data line (DL1: 33) of DL
Bypass 9) in the Y direction. That is, one power supply voltage line 2
6P does not pass between the load MISFET Qp1 of the memory cell MC and the connection part, but for the load of another memory cell MC adjacent to this connection part in the Y direction (arranged on the upper side in FIG. 9 ). It passes through between MISFETQp1 and detours. Further, one power supply voltage line 26P is adjacent to the other memory cell M in the Y direction (arranged on the upper side in FIG. 9 ).
It is also used as one power supply voltage line 26P for C. Similarly, the other power supply voltage line 26P extends in the X direction, and
The other semiconductor region (18) of the transfer MISFET Qt2
And the second data line of the complementary data line DL (DL2: 33)
A connecting portion (intermediate conductive layer 29 described later) is detoured in the Y direction. The other power supply voltage line 26P bypasses between the load MISFET Qp2 of the memory cell MC and the connection portion, and is adjacent to this connection portion in the Y direction (disposed on the lower side in FIG. 9 ). MISFET for MC load
It does not pass between Qp2. Similarly, the other power supply voltage line 26P of the other memory cell MC adjacent in the Y direction (arranged on the lower side in FIG. 9 ) is the other power supply voltage line 26P .
Also used as P. In other words, one memory cell MC has 2
Although the two power supply voltage lines 26P are arranged, each of the two power supply voltage lines 26P also serves as the power supply voltage line 26P of the other memory cells MC vertically adjacent to each other in the Y direction. In this memory cell MC, substantially one power supply voltage line 26P is arranged.

The two power supply voltage lines 26P arranged in the memory cell MC are X1 shown in FIG. 9 in the memory cell array MAY or the sub memory cell array SMEY .
The plane shape is line-symmetrical in the X direction with respect to the −X3 axis or the X2-X4 axis. In addition, the two power supply voltage lines 26P arranged in the memory cell MC are connected to the above-mentioned drive MISF.
Different from the line-symmetrical arrangement of the ETQd and the transfer MISFET Qt, and like the arrangement of the second electrode 23 of the capacitive element C, the planar shape is non-axisymmetric in the Y direction. That is, with respect to the planar shape of the power supply voltage line 26P extending the plurality of memory cells MC arranged in the X direction, the memory cells MC arranged in the X direction of the next stage adjacent in the Y direction are extended. The power supply voltage line 26P is configured to be line-symmetric in the X direction similarly to the power supply voltage line 26P extending the memory cell MC of the previous stage, and the power supply voltage line 26P extending the memory cell MC of the previous stage. The memory cells MC are shifted by one memory cell MC (one memory cell pitch) in the column direction. In the memory cell array MAY or the sub memory cell array SMAY, the transfer MISF of the power supply voltage line 26P
The detour of the connection portion (intermediate conductive layer 29) between the other semiconductor region of ETQt and the complementary data line DL is all performed on the upper side in the same Y direction.

Of the capacitive elements C arranged in the memory cell MC described above, the second electrode 23 (and the conductive layer 23) of the capacitive element C arranged on the driving MISFET Qd1 is shown in FIG.
As shown in FIG. 5, one power supply voltage line 26P is connected to the other memory cell M on the upper side in the connection portion (intermediate conductive layer 29).
Detour to C, and the connection part and load MISFET Qp
Since the distance from 1 is reduced, the planar shape of the memory cell MC is reduced by the amount corresponding to this reduced dimension. In addition, the driving MISFET Qd of the memory cell MC
The second electrode 23 (and the conductive layer 23) of the capacitive element C arranged on the upper part 2 detours the other power supply voltage line 26P into the memory cell MC at the connection portion (intermediate conductive layer 29), Since the other power supply voltage line 26P is passed between the connection portion and the load MISFET Qp2, the planar shape of the memory cell MC is increased by the amount corresponding to the passage of the other power supply voltage line 26P. That is, the power supply voltage line 26
Since P always extends over the memory cell MC for the purpose of improving the degree of integration (utilizes the occupied area of the memory cell MC), the power supply voltage line 26P is a side that bypasses over the memory cell MC. With reference to the planar shape of the second electrode 23 (and the conductive layer 23) of the capacitive element C disposed on the driving MISFET Qd2, the second electrode 23 (and the conductive layer of the capacitive element C disposed on the driving MISFET Qd1 is used as a reference. 23)
The planar shape of is reduced because the power supply voltage line 26P does not bypass the memory cell MC. Therefore, the memory cell MC
The second electrode 23 (and the conductive layer 23) of the capacitive element C of
When arranged symmetrically in the direction (X1-X2 axis or X3-X4 axis), the planar shape of the second electrode 23 arranged on the driving MISFET Qd2 is all (the driving MISF).
The planar shape of the second electrode 23 (on the ETQd1) is regulated,
Although the occupied area of the memory cell MC increases, as described above, the power supply voltage line 26P is arranged non-axisymmetrically in the Y direction, so that the second electrode 2 on the driving MISFET Qd1 is formed.
The planar shape of 3 is reduced, and the area occupied by the memory cell MC can be reduced by the amount corresponding to this reduction.

In the memory cell MC, a total of 4 layers including the first conductive layer 7, the second conductive layer 13, the third conductive layer 23, and the fourth conductive layer 26. The so-called gate material of the layer is constituted. As shown in FIGS. 6 and 10 (plan views showing patterns of specific conductive layers), the memory cell M
In C, the second conductive layer 13 is a transfer MISFE.
The gate electrode 13 of TQt, the word line 13, and the reference voltage line 13 are formed. Since the word line (including a gate electrode 13 in a part thereof) 13 and the reference voltage line 13 are the same conductive layer, they have the minimum processing dimension of the photolithography technique or a dimension larger than that in the SRAM manufacturing process. They are separated from each other and extend substantially parallel to the X direction.
In the memory cell MC, the third conductive layer 23 is configured as the gate electrode 23 of the load MISFET Qp, the conductive layer 23, the intermediate conductive layer 23, and the second electrode 23 of the capacitive element C. In the memory cell MC, the fourth conductive layer 2
6 is an n-type channel forming region 2 of the load MISFET Qp
6N, p-type source region 26P, p-type drain region 26P
And a power supply voltage line 26P. MIS for load
Since the FETs Qp1 and Qp2 have the same gate length direction in the Y direction and are the same conductive layer, they are separated from each other by the minimum processing dimension of the photolithography technique or a dimension larger than that in the SRAM manufacturing process. Extend almost parallel to.

A plurality of conductive layers 1 configured as described above
In the memory cell MC in which 3, 23, and 26 are stacked, as shown in FIG. 10 , the lower second conductive layer 13 and the intermediate third conductive layer 23 are separately formed. Since it is formed in the conductive layer of, it is allowed to be separated with a fine dimension Lm smaller than the minimum processing dimension of the photolithography technique. In other words, the memory cell MC is
For the main purpose of reducing the occupied area and improving the degree of integration of the SRAM, each of the conductive layers 13, 23 and 26 of the plurality of layers is positively brought close to each other with a fine dimension Lm. However, between the conductive layer 13 of the second layer and the conductive layer 23 of the third layer, which are separated by the fine dimension Lm, the film thickness is thinner than about one half of the fine dimension Lm. When the interlayer insulating film (21) is formed to have a uniform film thickness (deposited by, for example, the CVD method), a groove having a small opening size and a deep groove (a groove having a crevasse cross-sectional shape) is formed in a region having a fine dimension Lm. ) Occurs. Since the fourth conductive layer 26 is formed of a polycrystalline silicon film deposited by the CVD method, the polycrystalline silicon film is buried in the groove, and the fourth conductive layer 26 is patterned. It cannot be completely removed in the etching process. That is, the load MISFET Q
Each of p1 and Qp2 is left unetched in a groove generated in a region of a fine dimension Lm between the lower second conductive layer 13 and the intermediate third conductive layer 23 between them. As a result, a short circuit occurs through the remaining polycrystalline silicon film.

The memory cell MC of the SRAM of this embodiment is
The main purpose is to cut off the grooves generated between the load MISFETs Qp1 and Qp2, and the symbol O in FIG.
As indicated by S, if there is a portion separated by a fine dimension Lm between each of the second conductive layer 13 and the third conductive layer 23, the second conductive layer is formed. At least a part of the third conductive layer 23 is superposed on the layer 13 (in FIG. 10 , the superposed regions are shaded). Figure
10 , reference numeral NS indicates a region in which the second conductive layer 13 and the third conductive layer 23 are separated from each other with a fine dimension Lm, and an etching residue may occur. Second conductive layer 13 and third conductive layer 23
The respective overlapping is performed in a shape that crosses the region NS (a shape in which etching residue is generated in a part, but this etching residue is cut off in the middle).

MISFET for transfer of the memory cell MC
The other semiconductor region (18) of Qt is connected to the complementary data line (DL) 33, as shown in FIGS.
One transfer MISFET Qt1 of the memory cell MC is connected to the first data line (DL1) of the complementary data line 33. The other transfer MISFET Qt2 is connected to the second data line (DL2) of the complementary data line 33. The other semiconductor region of the transfer MISFET Qt and the complementary data line 33 are connected to each other through the intermediate conductive layers 23 and 29 sequentially stacked from the lower layer side toward the upper layer side.

The intermediate conductive layer 23 is shown in FIG. 6, FIG. 7 and FIG.
As shown in FIG. 9 , it is formed on the interlayer insulating film 21. A part of the intermediate conductive layer 23 is formed by the sidewall spacer 16
In the region defined by, the connection is made to the other semiconductor region (18) of the transfer MISFET Qt through the connection hole 22 formed in the interlayer insulating film 21. The connection hole 2
2 has an opening size larger than the region defined by the sidewall spacers 16 (larger on the gate electrode 12 side). As described above, the sidewall spacers 16 are formed on the sidewalls of the gate electrode 12 of the transfer MISFET Qt in a self-aligned manner. That is, a part of the intermediate conductive layer 23 is in a position regulated by the sidewall spacer 16 and is self-aligned with respect to the position, and the transfer MISFE is formed.
It is connected to the other semiconductor region of TQt. Intermediate conductive layer 2
The other part of 3 is drawn out on the interlayer insulating film 21 by at least the amount corresponding to the mask alignment margin dimension of the manufacturing process of the intermediate conductive layer 23 and the upper intermediate conductive layer 29. The intermediate conductive layer 23 absorbs the mask misalignment in the manufacturing process even if the semiconductor misalignment of the transfer MISFET Qt and the intermediate conductive layer 23 occur, and the other semiconductor region of the transfer MISFET Qt is absorbed. In contrast, the intermediate conductive layer 23 can be apparently connected by self-alignment.

The intermediate conductive layer 23 is the load MISF.
ETQp gate electrode 23, capacitive element C second electrode 2
3 and the conductive layers 23 are formed of the same conductive layer. That is, it is formed of a polycrystalline silicon film formed in the third layer gate material forming step, and an n-type impurity that reduces the resistance value is introduced into this polycrystalline silicon film.

The intermediate conductive layer 29 is formed on the interlayer insulating film 27, as shown in FIGS. One end of the intermediate conductive layer 29 has a connection hole 28 formed in the interlayer insulating film 27.
Through to the intermediate conductive layer 23. The intermediate conductive layer 23 is connected to the other semiconductor region of the transfer MISFET Qt as described above. The other end of the intermediate conductive layer 29 is drawn out in the X direction and connected to the complementary data line 33 through a connection hole 31 formed in the interlayer insulating film 30.

The intermediate conductive layer 29 whose one end side is connected to the other semiconductor region of the transfer MISFET Qt1 is the first of the complementary data lines 33 extending in the Y direction on the other semiconductor region of the transfer MISFET Qt2. Data line (D
L1) It is led out in the X direction to the bottom of 33, and is connected to the first data line 33 in this pulled out region. Similarly, the intermediate conductive layer 29 whose one end side is connected to the other semiconductor region of the transfer MISFET Qt2 is formed of the transfer MISFE.
The complementary data lines 33 extending in the Y direction on the other semiconductor region of TQt1 are led out in the X direction down to the second data line (DL2) 33, and in the pulled out region, the second data line 33 Connected. That is, the intermediate conductive layer 29 includes the transfer MISFET Qt1 of the memory cell MC,
A cross wiring structure that connects each of Qt2 and each of the first data line 33 and the second data line 33 extending to the inversion position in the X direction is configured.

The intermediate conductive layer 29 is formed of a refractory metal film, for example, a W film formed in the metal material forming step of the first layer of the manufacturing process, the forming method of which will be described later.
The W film has a smaller specific resistance value than the polycrystalline silicon film and the refractory metal silicide film.

As shown in FIG. 6, the interlayer insulating film 27, which is the base of the intermediate conductive layer 29, is made of silicon oxide films 27A and BP.
It is composed of a composite film in which the SG films 27B are sequentially laminated. The BPSG film 27B, which is the upper layer of the interlayer insulating film 27, is subjected to glass flow, and the surface is subjected to flattening processing.

As shown in FIG. 6, the interlayer insulating film 30 is composed of a deposition type silicon oxide film 30A and a coating type silicon oxide film 3.
0B and the deposition type silicon oxide film 30C are sequentially laminated, and each layer has a three-layer laminated structure. Lower silicon oxide film 30
A, Each of the upper layer of the silicon oxide film 30C, as described later, tetra lizard silane (TEOS: T etra E thoxy S ilan
e) It is deposited by a plasma CVD method using a gas as a source gas. The lower silicon oxide film 30A is deposited with a uniform film thickness along the stepped shape of the base, and particularly in the recessed part of the stepped shape of the base, the overhang shape above the recessed portion is unlikely to occur. That is, the lower silicon oxide film 30A can reduce the generation of cavities due to the overhang shape.
The intermediate silicon oxide film 30B is formed on the spin-on-glass ( S pi
coated with n O n G lass) method, after the baking process is performed, it is entirely etched (etch back). The intermediate silicon oxide film 30B is intensively formed (remains) on the step-shaped portion of the surface of the lower silicon oxide film 30A, and the surface of the interlayer insulating film 30 can be flattened. The intermediate silicon oxide film 30B is basically formed on the stepped portion on the surface of the lower silicon oxide film 30A except the region of the connection hole 31 which connects the intermediate conductive layer 29 and the complementary data line 33. To be done.
That is, it is possible to prevent the complementary data line (aluminum alloy) 33 from being corroded due to the moisture contained in the intermediate silicon oxide film 30B. The upper silicon oxide film 30C covers the surface of the intermediate silicon oxide film 30B.
The deterioration of the film quality of 0B can be prevented.

The complementary data line (DL) 33 is shown in FIG.
As shown in, it is formed on the interlayer insulating film 30. The complementary data line 33 is connected to the extended portion of the intermediate conductive layer 29 through the connection hole 31. The complementary data line 33 is formed in the metal material forming step of the second layer of the manufacturing process. The complementary data line 33 includes a lower metal film 33A, an intermediate aluminum alloy film 33B, and an upper metal film 33C.
Each of these is sequentially laminated to form a three-layer laminated structure. The lower metal film 33A is basically a transfer MISFE.
A barrier metal film for preventing mutual diffusion of the other semiconductor region (18) of TQt, silicon (Si) of the intermediate conductive layer 23, and aluminum (AL) of the aluminum alloy film 33B of the intermediate layer, and so-called alloy spike. To form as. The lower metal film 33A is formed of, for example, a TiW film.
The aluminum alloy film 33B of the intermediate layer has a smaller specific resistance value than the polycrystalline silicon film, the refractory metal film, and the refractory metal silicide film. The aluminum alloy film 33B is made of Cu, S
It is made of aluminum to which at least one of i is added. Cu basically has the effect of improving electromigration resistance. Si basically has the function of preventing alloy spikes. The upper metal film 33C is basically the intermediate aluminum alloy film 33.
It is configured for the purpose of preventing the aluminum hilllock phenomenon of B. Further, the upper metal film 33C is used for the purpose of reducing the reflectance of the surface of the intermediate aluminum alloy film 33B and preventing the diffraction phenomenon (halation) in the exposure process at the time of patterning by the photolithography technique. It is formed.

The complementary data line 33 may be formed by using the aluminum alloy film 33B as an aluminum film or by removing the lower metal film 33A and forming a single-layer aluminum alloy film.

The complementary data line 33 extends in the Y direction on the memory cell MC as shown in FIG. One of the complementary data lines 33, the first data line (DL1) 33
Extends in the Y direction on the driving MISFET Qd1, the transfer MISFET Qt2, and the load MISFET Qp2 of the memory cell MC. The other second data line (DL2) 33
Extends in the Y direction on the driving MISFET Qd2, the transfer MISFET Qt1 and the load MISFET Qp1 of the memory cell MC. That is, the first complementary data line 33
The data line 33 and the second data line 33 are separated from each other and extend substantially parallel to each other in the Y direction.

As shown in FIG. 7, the memory cell array M
In the AY or sub memory cell array MAY, the complementary data lines 33 of the memory cells MC arranged in the X direction are arranged in line symmetry with respect to the X1-X3 axis or the X2-X4 axis. The planar shape of the complementary data line 33 of the memory cells MC arranged in the Y direction is X1-X2 axis or X3-.
They are arranged in line symmetry with respect to the X4 axis.

On the memory cell MC, as shown in FIGS.
As shown in, the main word line (MWL) 29 and the sub word line (SWL1) 29 are arranged. Each of the main word line 29 and the sub word line 29 has the same conductive layer (first
It is made of a high melting point metal film formed in the metal material forming step of the second layer, and is made of the same conductive layer as the intermediate conductive layer 29. That is, each of the main word line 29 and the sub word line 29 is formed in a layer between the word line (WL) 13 and the complementary data line 33. Each of the main word line 29 and the sub word line 29 has a transfer MISFET for the memory cell MC.
Intermediate conductive layer 29 connected to Qt1 and transfer MISFE
It is arranged between the intermediate conductive layer 29 connected to TQt2. The main word line 29 and the sub word line 29 are separated from each other, and the memory cell array MAY extends substantially in parallel in the X direction.

As shown in FIGS. 2A and 3 described above,
There are four main word lines 29 (4 [bi
t]), one is arranged for each memory cell MC. One main word line 29 corresponds to the memory block M shown in FIG.
Since the four memory mats MM of B extend over a total of 16 memory cell arrays MAY, the wiring width is made thicker than that of the sub word line 29 for the purpose of reducing the resistance value.

As shown in FIGS. 2A and 3 described above, the sub word line (SWL1) 29 is arranged in the Y direction in the memory cell array MAY arranged on the side close to the word driver circuit WDR of the memory mat MM. One is arranged for each arranged memory cell MC. The sub-word line 29 has a length that extends over one memory cell array MAY and is shorter than the main word line 29. Therefore, the wiring width is smaller than that of the main word line 29. Composed. As shown in FIGS. 6 and 7, in each of the main word line 29 and the sub word line 29, the reference voltage line (Vss) 13 connected to the memory cell MC is formed of the same conductive layer as the word line (WL) 13. , This reference voltage line 1
Since the conductive layer extending 3 has been used as an empty region, it is arranged using this empty region (a region where two wirings can be arranged). That is, the memory cell MC has a word line (W
L) 13 and the reference voltage line 13, a main word line 29 used in the divided word line system in the X direction and a sub word line 29 used in the double word line system.
2 word lines can be extended.

Complementary data line 33 of the memory cell MC
On the entire surface of the substrate including the above (excluding the area of the external terminal BP),
As shown in FIG. 6, a final passivation film (final protective film) 34 is formed. The final passivation film 34 has a three-layer laminated structure in which a silicon oxide film, a silicon nitride film, and a resin film are sequentially laminated, though its structure is not shown in detail.

The silicon oxide film below the final passivation film 34 has a laminated structure of three layers and has the same structure as the interlayer insulating film 30. That is, the lower silicon oxide film is a silicon oxide film deposited by a CVD method using tetraethoxysilane gas as a source gas, a silicon oxide film etched after coating, and a CVD method using a tetraethoxysilane gas as a source gas. Formed of each of the silicon oxide films. That is, the lower silicon oxide film flattens the surface and prevents the formation of cavities in the upper silicon nitride film. The intermediate silicon nitride film is formed by the plasma CVD method. The intermediate silicon nitride film has the function of increasing the moisture resistance. The upper resin film is formed of, for example, a polyimide resin. This resin film shields alpha rays emitted from a small amount of radioactive elements contained in the resin encapsulation portion of the resin encapsulation type semiconductor device, and can improve the alpha ray soft error resistance of SRAM. Further, the resin film prevents the filler contained in the resin sealing portion from causing cracks in the interlayer film such as the final passivation film 34.

Next, the well structure and the structure of the memory cell MC in the peripheral region (end portion) of the memory cell array MAY of the memory mat MM of SRAM will be described.

SR shown in FIGS. 2 (A), 3 and 4
The peripheral structure of the memory cell array MAY of the AM memory mat MM or the sub memory cell array SMEY is shown in FIG.
To FIG. 14 (enlarged plan view of the peripheral region) and FIG. 15 (cross-sectional view of main parts). FIG. 11 shows a planar shape of the active region whose peripheral shape is defined by the element isolation insulating film 4. FIG. 12 shows the planar shapes of the driving MISFET Qd and the transfer MISFET Qt which are superposed on the active region. FIG. 13 shows the active region, the driving MISFET Qd, and the transfer MISFE.
The plane shape of load MISFETQp piled up on TQt is shown. FIG. 14 shows the active region and the driving MISFETQ.
d, transfer MISFETQt and load MISFETQ
Sub word line (SWL) 29, main word line (MWL) 29 and complementary data line (DL) 33 superimposed on p
The plane shape of is shown.

As shown in FIG. 11 , in the central area of the memory cell array MAY or the sub memory cell array SMEY, some active areas of four memory cells MC adjacent in the X and Y directions are integrally formed. The plane shape is a ring shape. Specifically, with respect to the memory cell MC2 indicated by reference numeral MC2 in FIG. 11 , the memory cell MC2 and the memory cell M adjacent to the right side of the memory cell MC2.
C, two memory cells MC adjacent to the lower side of these two memory cells MC, and a total of four memory cells MC, one of the four memory cells MC is a transfer MIS.
FETQt and one driving MISFETQd, total 4
Transfer MISFETs Qt and 4 drive MISFs
The active regions of the ETQd are integrally configured to form a ring-shaped active region (a partially filled region in FIG. 11 ).

In other words, the above-mentioned four transfer MISFEs
TQt and each of the four driving MISFETs Qd (total 8
Each MISFET) has a source region or a drain region facing each other integrally, and is also electrically connected in series in a ring shape. That is, in the four memory cells MC adjacent to each other in the X direction and the Y direction, one transfer MISFET Qt and the driving M of the memory cell MC.
One L-shaped active region composed of the ISFET Qd is continuous with each other, and there is no termination in the direction in which the active regions extend (direction coinciding with the gate length direction of a plurality of MISFETs connected in series), The pattern of the active area is composed of a closed ring shape. The inner frame side and the outer frame side of the ring-shaped active region facing each other (transfer MISFE
Regions defining the gate widths of TQt and the driving MISFET Qd) are defined by the element isolation insulating film 4 and the p-type channel stopper region 5. The transfer MISFET Qt of each of the four memory cells MC has the gate length direction aligned with the Y direction, and the drive MISFET Qd has the gate length direction aligned with the X direction. Therefore, the ring shape is circular or elliptical. Rather, it is configured by a planar shape that is close to a rectangular shape (rectangular shape).

The active region formed in the ring shape is X
In the direction (direction matching the gate width direction of the transfer MISFET Qt or the gate length direction of the driving MISFET Qd), a plurality of shapes are arranged at the same pitch. This X
The element isolation insulating film 4 (and the p-type channel stopper region 5) is disposed between each of the plurality of ring-shaped active regions adjacent to each other in the direction, and is electrically isolated. The ring-shaped active region at the next stage adjacent to the ring-shaped active region in the Y direction (the direction matching the gate length direction of the transfer MISFET Qt or the gate width direction of the driving MISFET Qd) is
Similar to the array in the previous stage, a plurality of arrays having the same shape and the same pitch in the X direction are arranged and X
They are arranged so as to be offset by a half pitch (half pitch) in the direction. That is, the ring-shaped active region is formed as shown in FIG.
As shown in FIG. 1 , the memory cell array MAY (or the sub-memory cell array SMEY) is arranged in a zigzag manner while ensuring periodicity.

As shown in FIGS. 11 and 15 , the memory cell array MAY (or the sub memory cell array SMA) is
Y), that is, the end portion of the memory cell array MAY, in the region close to the guard ring region P-GR arranged on the outer periphery of the memory cell array MAY, the periodicity of the arrangement of the ring-shaped active regions. A layout is provided to ease the disturbance of the. Specifically, FIG. 11 and FIG.
As shown in FIG. 5, between the memory cell array MAY and the guard ring region P-GR, a dummy active region having the same or similar shape as a part of the shape of the ring-shaped active region arranged in the central region of the memory cell array MAY. Each of 4D1 to 4D3 is arranged.

[0204] The guard ring region P-GR surrounding the two memory cell array MAY memory mat MM shown in FIG. 4, as shown in FIGS. 11 and 15, p-
In the peripheral region of the main surface of the mold well region 2M, the periphery is defined by the element isolation insulating film 4 (a part is defined by the active region 4D). Guard ring area P-G
R is p + formed on the main surface of the p- well region 2M.
The p-type well region 2M is mainly composed of the type semiconductor region 40 and supplies a fixed reference voltage Vss to the p-type well region 2M.

The guard ring area P-GR is shown in FIG.
15 , the reference voltage line (Vss) 33 is electrically connected via the reference voltage line (Vss) 29.
The reference voltage line 29 is the main word line (MWL) 2 described above.
9, the sub-word line (SWL) 29 and the like are formed of the same conductive layer and extend along the periphery of the memory cell array MAY. The reference voltage line 29 is connected to the guard ring region P-GR through a connection hole 28 formed in the interlayer insulating film 27. The reference voltage line 33 is formed of the same conductive layer as the complementary data line (DL) 33. Since the complementary data line 33 extends in the Y direction in the memory cell array MY, the reference voltage line 33 is set to Y in order to avoid contact with the complementary data line 33.
Extend in the direction. The reference voltage line 33 is connected to the reference voltage line 29 in the lower layer through a connection hole 31 formed in the interlayer insulating film 30.

Further, as shown in FIGS. 11 to 15 , the memory cell array MAY is basically arranged on the main surface of the p--type well region 2M which is the main surface of the n--type well isolation region 3i.
An n-type well region 3 is formed on the outer periphery of the p-type well region 2M in which the memory cell array MAY is arranged and on the main surface of the n-type well isolation region 3i. The n-type well region 3 disposed on the main surface of the n-type well isolation region 3i has a higher impurity concentration than that of the surface of the n-type well isolation region 3i as shown in FIG. Therefore, the impurity concentration of the main surface of the n-type well isolation region 3i can be set high (correction can be made to increase the impurity concentration). In other words, the n-type well isolation region 3i
The impurity concentration of the n-type well region 3 is added to the main surface of the outer peripheral portion of the p-type well region 2M, which is set to a high impurity concentration. As a result, the p-type well regions 2M and n-of the main surface of the n-type well isolation region 3i in the double well structure are formed.
It is possible to improve the dielectric isolation breakdown voltage between the p-type semiconductor substrate 1 and the outer periphery of the type well isolation region 3i.

As shown in FIGS. 11 and 15 , n-
A guard ring region NG is formed in the peripheral region of the mold well region 3.
R is placed. The guard ring region N-GR is formed in the peripheral region of the main surface of the n-type well region 3 in a region defined by the element isolation insulating film 4. The guard ring region N-GR is mainly composed of the n + type semiconductor regions 11 and 18 formed in the main surface portion of the n- type well region 3 and supplies a fixed power supply voltage Vcc to the n- type well region 3. .

The guard ring region N-GR is shown in FIG.
15 , the power supply voltage line (Vcc) 33 is electrically connected via the power supply voltage line (Vcc) 29.
The power supply voltage line 29 is formed of the same conductive layer as the reference voltage line 29, and the power supply voltage line 33 is formed of the same conductive layer as the reference voltage line 33.

Further, as shown in FIG. 12 , the memory cell array MAY is provided in order to reduce the disturbance of the periodicity at the end.
Dummy gate electrode 7D is arranged. The dummy gate electrode 7D is arranged at the end portion of the memory cell array MAY and has the same or similar plane shape as the plane shape of the gate electrode 7 of the driving MISFET Qd of the memory cell MC arranged in the central region of the memory cell array MAY. Configured. Similarly, in order to reduce the disturbance of the periodicity at the end of the memory cell array MAY, the dummy word line 13D
1 and the dummy reference voltage line 13D2 are arranged. The dummy word line 13D1 and the dummy reference voltage line 13D2
Are arranged at the ends of the memory cell array MAY, and are configured to have the same or similar planar shape as that of the word line 13 and the reference voltage line 13 arranged in the central region of the memory cell array MAY. .

Next, FIG. 16 shows a specific structure of the complementary MISFET which constitutes the peripheral circuit of the SRAM described above .
A brief description will be given using (enlarged cross-sectional view of a main part).

As shown in FIG. 16 , the complementary MISFET of the peripheral circuit including the direct peripheral circuit and the indirect peripheral circuit of the SRAM has p-type well regions 2 and n-types on the main surface of the p-type semiconductor substrate 1, respectively. It is arranged in the mold well region 3. That is,
The complementary MISFET of the peripheral circuit has an n-type well region 2M in which the memory cell array MAY is arranged.
The p-type well region 2 and the n-type well region 3 are arranged around the outer periphery of the -type well isolation region 3i.

Of the complementary MISFETs, the n-channel MISFET Qn is the element isolation insulating film 4 in the inactive region.
And in the region surrounded by the p-type channel stopper region 5 on the main surface of the p-type well region 2.
That is, the n-channel MISFET Qn is mainly composed of the p-type well region 2 (channel forming region), the gate insulating film 12, the gate electrode 13, the source region and the drain region. The n-channel MISFET Qn is the memory cell M.
The gate electrode 13 of the n-channel MISFET Qn is formed of the same conductive layer as the gate electrode 13 of the transfer MISFET Qt. Similarly, the n-channel MISFETQ
n has an LDD structure, and each of the source region and the drain region is composed of an n-type semiconductor region 17 having a low impurity concentration and an n + -type semiconductor region 18 having a high impurity concentration.

In the n-channel MISFET Qn, a wiring 29 or a wiring 33 is electrically connected to the n + type semiconductor region 18 of at least one of the source region and the drain region through the wiring 29.

Of the complementary MISFETs, p
The channel MISFET Qp is arranged on the main surface of the n--type well region 3 in the region surrounded by the element isolation insulating film 4 in the inactive region. That is, p-channel MIS
The FET Qp mainly includes an n-type well region 3 (channel forming region), a gate insulating film 12, a gate electrode 13, a source region and a drain region. p channel MI
Although the SFET Qp has a different channel conductivity type, it has substantially the same structure as the n-channel MISFET Qn.
That is, the p-channel MISFET Qp has an LDD structure, and the source region and the drain region each have a low impurity concentration p-type semiconductor region 39 and a high impurity concentration n +.
It is composed of the type semiconductor region 40.

In the p-channel MISFET Qp, the wiring 29 or the wiring 33 is electrically connected to the p + type semiconductor region 40 of at least one of the source region and the drain region through the wiring 29.

The transfer MISFET Qt and the drive MI of the memory cell MC of the SRAM memory cell array MAY.
P-type well region 2M in which each of SFETQd is arranged
Is the n-channel MISF of the complementary MISFET of the peripheral circuit
The impurity concentration on the surface is set independently of the impurity concentration on the surface of p @-type well region 2 in which ETQn is arranged.
That is, the impurity concentration on the surface of the p-type well region 2M is
The impurity concentration on the surface of the p-type well region 2 can be set to be equal to or higher than that, and as a result, the memory cell M can be set.
C transfer MISFETQt, drive MISFETQd
The threshold voltage of each can be raised. This memory cell M
C transfer MISFETQt, drive MISFETQd
If each of the threshold voltages can be set high, malfunction due to noise can be prevented, so that the information held in the information storage node of the memory cell MC can be stably held.

The impurity concentration on the surface of the p-type well region 2 in which the n-channel MISFETQn is arranged is determined by the transfer MISFETQt and the driving MIS of the memory cell MC.
The impurity concentration of the surface is set independently of the impurity concentration of the p-type well region 2M in which each of the FETs Qd is arranged. That is, the impurity concentration on the surface of the p-type well region 2 can be set to be equal to or lower than the impurity concentration on the surface of the p-type well region 2M, and as a result, the threshold voltage of the n-channel MISFET Qn can be set. Can be lowered. If the threshold voltage of the n-channel MISFETQn can be set low, the operating speed of the n-channel MISFETQn can be increased.

Next, regarding a specific method of manufacturing the SRAM described above, FIGS. 19 to 33 (cross-sectional views of the principal part shown in each step in the central region of the memory cell array) and FIG.
It will be briefly described with reference to FIGS. 39A to 39C ( partial sectional views showing each step at each end of the memory cell array).

<< Step of Forming Well Isolation Region >> First, the p--type semiconductor substrate 1 made of single crystal silicon is prepared ( FIG. 19 ) .
And FIG. 34 ). As described above, the p − type semiconductor substrate 1 has the main surface set to the (100) crystal plane, and a so-called off-angle wafer is used.

Next, a silicon oxide film 50 is formed on the main surface of the p--type semiconductor substrate 1. The silicon oxide film 50 is formed by, for example, a thermal oxidation method and has a film thickness of about 20 to 25 [nm].

Next, as shown in FIGS. 19 and 34 , a silicon nitride film is formed on the main surface of the formation region of the n--type well isolation region 3i of the p--type semiconductor substrate 1 with the silicon oxide film 50 interposed therebetween. 51 is formed. This silicon nitride film 51 is used as an oxidation resistant mask. The silicon nitride film 51 is deposited by, for example, a CVD method and is formed to have a film thickness of about 40 to 60 [nm]. The silicon nitride film is patterned by an etching technique using a mask formed by a photolithography technique after the deposition.

Next, the silicon nitride film 51 is used as an oxidation resistant mask, and the region other than the silicon nitride film 51, that is, n.
In a region other than the region where the -type well isolation region 3i is formed, the silicon oxide film 50 on the main surface of the p-type semiconductor substrate 1 is grown to a thick silicon oxide film 50M. This silicon oxide film 5
0M is formed with a film thickness of, for example, about 120 to 150 [nm] for the purpose of using it as an impurity introduction mask for introducing impurities by utilizing the film thickness difference from the above-mentioned silicon oxide film 50. The silicon oxide film 50M used as the impurity introduction mask is the silicon nitride film 5 used as the oxidation resistant mask.
1 is self-aligned. After that, the silicon nitride film 51 is removed.

Next, using the silicon oxide film 50M as an impurity introduction mask, n − of the main surface of the p − type semiconductor substrate 1 is formed.
An n-type impurity is introduced into the formation region of the type well isolation region 3i, and the n-type impurity is expanded and diffused to form the n-type well isolation region 3i (see FIGS . 20 and 35 ).
The n-type impurities are, for example, 10 ¹² to 10 ¹³ [atoms / c
m ² ], and an impurity concentration of P is used, 50 to 70 [Ke
V] is introduced by ion implantation with energy. The introduced n-type impurities are stretched and diffused for about 150 to 200 [min] at a temperature of about 1100 to 1300 [° C].

Next, as shown in FIGS. 20 and 35 , n
The silicon oxide film 50M used as the impurity introduction mask of the n-type impurity for forming the -type well isolation region 3i is used (using the same mask), and the p-type impurity 2Mp is formed on the main surface portion of the n-type well isolation region 3i. Introduce. p-type impurity 2M
Since p is introduced using the silicon oxide film 50M forming the n-type well isolation region 3i, it is formed in self-alignment with the n-type well isolation region 3i. Moreover, since the p-type impurity 2Mp is introduced by using the silicon oxide film 50M forming the n-type well isolation region 3i, the p-type impurity 2Mp also serves as an impurity introduction mask and is used only for introducing the p-type impurity 2Mp. The step of forming the formed impurity introduction mask can be eliminated. The p-type impurity 2Mp forms the p-type well region 2M in which the memory cell array MAY is arranged.
This is performed by utilizing the extension diffusion of each of the type well region 2 and the n-type well region 3.

The p-type impurity 2Mp is, for example, 10 ¹² to
BF ₂ having an impurity concentration of about 10 ¹³ [atoms / cm ² ] is used, and ion implantation is performed with an energy of about 50 to 70 [KeV].

Next, each of the silicon oxide films 50 and 50M is removed.

<< Well Forming Step >> Next, a silicon oxide film 52 is formed on the entire main surface of the p--type semiconductor substrate 1 including the main surface of the n--type well isolation region 3i. Silicon oxide film 5
2 is formed by, for example, a thermal oxidation method, and is formed with a film thickness of about 40 to 50 [nm].

Next, a region of the main surface of the n--type well isolation region 3i in which the p-type impurity 2Mp is introduced (this region is formed by the p-type impurity 2Mp during the thermal oxidation step for forming the silicon oxide film 52). Is slightly diffused to form the p-type well region 2M), and on the formation region of the p-type well region 2 on the main surface of the p-type semiconductor substrate 1 except the n-type well isolation region 3i. A silicon nitride film 53 is formed on each of them. This silicon nitride film 53 is used as an impurity introduction mask and an oxidation resistant mask. The silicon nitride film 53 is deposited by, for example, a CVD method and is formed to have a film thickness of about 40 to 60 [nm]. The silicon nitride film 53 is patterned by the etching technique using a mask formed by the photolithography technique after the deposition.

Next, as shown in FIGS. 21 and 36 , the silicon nitride film 53 is used as an impurity introduction mask and p
An n-type impurity 3n is introduced into the main surface portion of the formation region of the n--type well region 3 of the --type semiconductor substrate 1. n-type impurity 3n
As shown in FIG. 36 , is the outer periphery of the region into which the p-type impurity 2Mp is introduced (formation region of the p-type well region 2M) and is also introduced into the main surface of the n-type well isolation region 3i. To be done. The n-type impurity 3n is, for example, 1 × 10 ^{13 to} 3 × 10.
Use P with an impurity concentration of about ¹⁴ [atoms / cm ² ]
It is introduced by ion implantation with an energy of about 0 to 130 [KeV]. The n-type impurity 3n is introduced into the main surface portion of the p-type semiconductor substrate 1 through the silicon oxide film 52.

Next, using the silicon nitride film 53 as an oxidation resistant mask, the region of the p--type semiconductor substrate 1 into which the n-type impurity 3n is introduced and the n--type well isolation region 3i of the n-type impurity 3n are introduced. In each of the formed regions, the silicon oxide film 5 is formed.
2 is grown to form a thick silicon oxide film 52M.
The growth of the silicon oxide film 52M is performed by a thermal oxidation method using the silicon nitride film 53 as an oxidation resistant mask. The silicon oxide film 52M is formed to have a film thickness of about 130 to 140 [nm]. After that, the silicon nitride film 53 is removed.

Next, as shown in FIGS. 22 and 37 , the grown silicon oxide film 52M is used as an impurity introduction mask to form the p--type well region 2 on the main surface of the p--type semiconductor substrate 1. A p-type impurity 2p is formed in each of the main surface portion of the region and the main surface portion of the p--type well region 2M of the n--type well isolation region 3i.
To introduce. The p-type impurity 2p is 1 × 10 ^{13 to} 3 × 10.
Use BF ₂ with an impurity concentration of about ¹³ [atoms / cm ² ],
It is introduced by ion implantation with an energy of about 50 to 70 [KeV]. The p-type impurity 2p is introduced into the main surface portion of each of the p--type semiconductor substrate 1 and the p--type well region 2M through the silicon oxide film 52.

Next, as shown in FIGS. 23 and 38 , p
N-type impurities 3 introduced into the main surface of the -type semiconductor substrate 1
Each of the n-type impurity 2p and the n-type well 2p and the p-type impurity 2Mp introduced into the main surface of the n-type well isolation region 3i is stretched and diffused.
The p-type well region 2 is formed by diffusion of the p-type impurity 2p, and the p-type well region 2M is formed by diffusion of the p-type impurity 2Mp. That is, when this step is completed, the double well structure formed by the n-type well isolation region 3i and the p-type well region 2M is completed in the main surface portion of the p- type semiconductor substrate 1, and p
A twin well structure is completed in which the n − type well region 3 and the p − type well region 2 are formed in different regions of the main surface of the − type semiconductor substrate 1. The stretch diffusion is, for example, about 100 to 200 at a temperature of 1100 to 1300 [° C.].
[Minutes] After that, the silicon oxide film 52 is removed.

<< Device Isolation Region Forming Step >> Next, p
A silicon oxide film is formed on the entire surface of the p − type semiconductor substrate 1 including the main surfaces of the − type well region 2, the n − type well region 3 and the p − type well region 2M. This silicon oxide film is formed by a thermal oxidation method, and has a film thickness of, for example, about 15 to 20 [nm].

Then, a silicon nitride film is formed on the main surface of the active region forming regions of the p--type well region 2, n--type well region 3 and p--type well region 2M. The silicon nitride film is used as an impurity introduction mask and an oxidation resistant mask. The silicon nitride film is deposited by, for example, a CVD method,
It is formed with a film thickness of about 150 [nm]. The silicon nitride film is
Using photolithography technology and etching technology,
Patterned.

Next, when the silicon nitride film is patterned, the silicon oxide film or a part thereof is removed in the inactive region exposed from the silicon nitride film, so that the inactive region is newly oxidized. The silicon film is formed again. This newly formed silicon oxide film is formed by, for example, a thermal oxidation method,
It is formed with a film thickness of about 8 to 12 [nm]. The newly formed silicon oxide film is formed for the purpose of removing etching damage when the silicon nitride film is patterned and preventing contamination when introducing impurities.

Next, using the silicon nitride film as an impurity introduction mask, p-type impurities are added to the formation regions of the inactive regions (element isolation regions) of the p--type well region 2 and the p--type well region 2M. Introduce. The p-type impurity is, for example, 10 ¹³ to
BF ₂ having an impurity concentration of about 10 ¹⁴ [atoms / cm ² ] is used, and ion implantation is performed with energy of about 30 to 50 [KeV]. This p-type impurity is introduced into the main surface portions of the p-type well region 2 and the p-type well region 2M through the silicon oxide film. The main surface of the n-type well region 3 is covered with a mask (not shown) formed by a photolithography technique, and p-type impurities are not introduced. This mask is removed after the introduction of the p-type impurity.

Next, using the silicon nitride film as an oxidation resistant mask, on the main surface of each inactive region of the p--type well region 2, n--type well region 3 and p--type well region 2M. A silicon oxide film is grown to form the element isolation insulating film 4 (see FIGS . 24 and 39 ). The element isolation insulating film 4 is
For example, it is formed of a silicon oxide film formed by the thermal oxidation method (selective thermal oxidation method of the substrate) and has a film thickness of about 400 to 500 [nm].

When the heat treatment process for forming the element isolation insulating film 4 is performed, the p-type impurities introduced into the respective inactive regions of the p-type well region 2 and the p-type well region 2M are previously introduced. to pull enlargement spreading is applied, as shown in FIGS. 24 and 39, p-type channel stopper region 5 are formed.

After forming the element isolation insulating film 4 and the p-type channel stopper region 5, the silicon nitride film used as the oxidation resistant mask is removed.

In the manufacturing process thereafter, the manufacturing process of the memory cell MC of the memory cell array MAY is used (there is a part of the same manufacturing process).
Therefore, the memory cell array MAY will be described mainly with reference to the drawings, and the peripheral circuits will be described without reference to the drawings, only the parts that are basically different from the manufacturing process of the memory cell array MAY.

<< Formation Step of First Gate Insulating Film >> Next, a silicon oxide film on the main surface of each active region of the p--type well region 2, n--type well region 3 and p--type well region 2M. To remove. By the step of removing the silicon oxide film, p-
The main surfaces of the active regions of the type well region 2, the n-type well region 3 and the p-type well region 2M are exposed.

Next, a new silicon oxide film is formed on the main surfaces of the active regions of the p--type well region 2, the n--type well region 3 and the p--type well region 2M. The silicon oxide film is formed mainly for the purpose of preventing contamination at the time of introducing impurities and removing the so-called white ribbon of the silicon nitride film at the end of the element isolation insulating film 4 which cannot be completely removed at the time of removing the silicon nitride film. . The silicon oxide film is formed by, for example, a thermal oxidation method and has a thickness of 18 to
It is formed with a film thickness of about 20 [nm].

Then, threshold voltage adjusting impurities are introduced into the main surface portions of the active regions of the p--type well region 2, the n--type well region 3, and the p--type well region 2M. A p-type impurity such as BF ₂ is used as the threshold voltage adjusting impurity. This BF ₂ is introduced by ion implantation and is, for example, 10 ¹² to 1 at an energy of about 40 to 50 [KeV].
The impurity concentration is about 0 ¹³ [atoms / cm ² ]. This BF ₂ is introduced into the main surface portions of the p − type well region 2, the n − type well region 3 and the p − type well region 2M through the silicon oxide film.

Next, the silicon oxide film on the main surface of each active region of the p--type well region 2, the n--type well region 3 and the p--type well region 2M is removed, and the p--type well region 2 is removed. , N
The main surfaces of the active regions of the -type well region 3 and the p-type well region 2M are exposed. Thereafter, a gate insulating film 6 is formed on the main surfaces of the active regions of the exposed p--type well region 2, n--type well region 3 and p--type well region 2M. The gate insulating film 6 is formed by a thermal oxidation method,
It is formed with a film thickness of about 5 [nm]. The gate insulating film 6 is a MIS for driving the memory cells MC of the memory cell array MAY.
It is used as the gate insulating film 6 of the FET Qd.

<< First Layer Gate Material Forming Step >> Next, a polycrystalline silicon film (7) is deposited on the entire main surface of the p--type semiconductor substrate 1 including the gate insulating film 6. This polycrystalline silicon film is formed in the first layer gate material forming step.
The polycrystalline silicon film is formed by so-called doped polysilicon, which is deposited by the CVD method, and an impurity for reducing the resistance value is introduced during the deposition. This polycrystalline silicon film is made of disilane (Si ₂
It is deposited by a CVD method using H ₆ ) and phosphine (PH ₃ ) as source gases. In the case of the present embodiment, P, which is an n-type impurity, is introduced into the polycrystalline silicon film, and P is 10 ²⁰ -1.
The impurity concentration is about 0 ²¹ [atoms / cm ³ ]. The polycrystalline silicon film is formed to have a relatively thin film thickness of about 100 [nm] when used as the gate electrode 7 of the driving MISFET Qd and the first electrode 7 of the capacitive element C in the memory cell MC. To be done. The polycrystalline silicon film is an insulator for the dielectric film (21) formed thereabove or the underlying gate insulating film (6) as long as it does not impair the operating speed when used as the gate electrode 7 of the driving MISFET Qd. The withstand voltage can be secured and the upper layer can be made flat by thinning.

After the polycrystalline silicon film formed in the gate material forming step of the first layer is formed, this polycrystalline silicon film is heat-treated. This heat treatment is performed by using, for example, nitrogen (N ₂ )
8 to 12 [min] at a temperature of 700 to 950 [° C] in gas
After that, the P introduced into the polycrystalline silicon film is activated and the quality of the film is stabilized.

Next, an insulating film (no reference numeral) is formed on the entire main surface of the p--type semiconductor substrate 1 including the polycrystalline silicon film.
To form. This insulating film electrically separates the lower polycrystalline silicon film and the upper conductive layer (13) from each other. The insulating film uses inorganic silane (SiH ₄ or SiH ₂ Cl ₂ ) as a source gas,
It is formed of a silicon oxide film deposited by a CVD method using a nitrogen oxide (N ₂ O) gas as a carrier gas. Silicon oxide film is about 8
It is deposited at a temperature of 00 [° C.]. The insulating film is, for example, 130
It is formed with a film thickness of about 160 nm.

Next, the insulating film and the polycrystalline silicon film are sequentially patterned to form a gate electrode 7 of the polycrystalline silicon film (see FIG. 25 ). The patterning is performed by anisotropic etching such as RIE using a mask formed by a photolithography technique. Gate electrode 7
Is configured as the gate electrode 7 of the driving MISFET Qd of the memory cell MC. Although not shown, the dummy gate electrode 7D of the memory cell array MAY shown in FIG. 12 , the gate electrode 7 of the MISFET forming the peripheral circuit, and the like are also formed by the step of forming the gate electrode 7.

<< Step of Forming First Source Region and Drain Region >> Next, sidewall spacers 9 are formed on the sidewalls of the gate electrode 7 and the insulating film formed thereon. The sidewall spacer 9 is formed by depositing a silicon oxide film on the entire main surface of the p − type semiconductor substrate 1 including the insulating film, and etching the entire surface of the silicon oxide film by an amount corresponding to the deposited film thickness. It is formed by The silicon oxide film is deposited by a CVD method using an inorganic silane gas as a source gas as described above, and has a thickness of, for example, 140 to 160 [nm].
It is formed with a film thickness of about a certain degree. For the etching, anisotropic etching such as RIE is used.

Next, during the etching for forming the sidewall spacer 9, the main surface of the active region of the p--type well region 2M in the region other than the region where the gate electrode 7 and the sidewall spacer 9 are formed is exposed. Therefore, a silicon oxide film (no reference numeral is formed) is formed in this exposed region. This silicon oxide film is mainly used for the purpose of preventing contamination when introducing impurities, and preventing damage to the main surface of the active region due to the introduction of impurities. This silicon oxide film is formed by, for example, a thermal oxidation method and has a film thickness of about 8 to 12 [nm].

Next, as shown in FIG. 25 , the main surface of the p--type semiconductor substrate 1 including the gate electrode 7 (actually, the upper silicon oxide film) and the surface of the sidewall spacer 9 are included. An insulating film 9T is formed on the entire upper surface. Insulation film 9T
Is the open end of the sidewall spacer 9 (gate electrode 7
Of the maximum stress generated in the main surface of the p--type well region 2M at the end portion on the side opposite to the side contacting the side wall of the p-type well region, which defines the introduction region of the n-type impurity in the subsequent step). Impurities (semiconductor regions 10, 11, 1)
The main purpose is to shift the position where damage occurs on the main surface of the p-type well region 2M when introducing the n-type impurities forming each of 7 and 18. At the open end of the sidewall spacer 9, the p-type well region 2 is formed.
The concentration of the maximum stress generated on the main surface of M is caused by the volume contraction of the gate electrode 7 based on the thermal expansion coefficient difference between the sidewall spacer (silicon oxide film) 9 and the gate electrode (polycrystalline silicon film) 7. . When the position where the maximum stress is concentrated and the position where damage due to the introduction of impurities are generated coincide with each other, p− from the open end of the sidewall spacer 9
Crystal defects occur on the main surface of the mold well region 2M. The insulating film 9T is formed by CVD using inorganic silane gas as a source gas.
Method, and is formed with a film thickness of, for example, about 15 to 25 [nm].

Next, although not shown, the memory cell array M
In the formation regions of the AY transfer MISFET Qt, the n-channel MISFET Qn of the peripheral circuit, and the p-channel MISFET Qp (excluding the formation region of the DDD structure),
An impurity introduction mask is formed. Memory cell array MAY
In FIG. 8 , the impurity introduction mask has a reference numeral DDD in FIG.
Is formed outside the area surrounded by the one-dot chain line. The impurity introduction mask is formed by photolithography, for example.

Next, using the impurity introduction mask (mainly the mask with the reference numeral DDD), an n-type impurity is formed in the main surface portion of the p--type well region 2M in the formation region of the driving MISFET Qd of the memory cell array MAY. To introduce. This n-type impurity forms the n-type semiconductor region 10 having a low impurity concentration in each of the source region and the drain region of the driving MISFET Qd which mainly adopts the DDD structure, and P having a high diffusion rate is used. P uses ion implantation, for example, with an energy of about 30 to 40 [KeV], 10
It is introduced at an impurity concentration of about ¹⁴ to 10 ¹⁵ [atoms / cm ² ]. When introducing P, the impurity introduction mask (DD
Together with D), the gate electrode 7, the side wall spacer 9 formed on the side wall thereof, and the insulating film 9T formed along the surface of the side wall spacer 9 are also used as an impurity introduction mask. After the introduction of P, the impurity introduction mask is removed.

Next, P as the n-type impurity is stretched and diffused to form an n-type semiconductor region 10 having a low impurity concentration as shown in FIG . This n-type semiconductor region 1
Since 0 uses the sidewall spacer 9 as an impurity introduction mask, the amount of diffusion toward the channel formation region side is regulated by the sidewall spacer 9 in the formation region of the driving MISFET Qd. That is, the n-type semiconductor region 10 can reduce the amount of diffusion toward the channel formation region side by an amount corresponding to the film thickness of the sidewall spacer 9, as compared with the case where the gate electrode 7 is used as an impurity introduction mask. The reduction of the diffusion amount to the channel formation region side can increase the effective gate length dimension (channel length dimension) of the driving MISFET Qd, so that the short channel effect of the driving MISFET Qd can be prevented.

As described above, the n-type semiconductor region 10
The n-type impurity forming the is formed into the insulating film 9T on the surface of the sidewall spacer 9, and is introduced into the main surface portion of the p--type well region 2M by using the impurity introduction mask mainly including this insulating film 9T. .. That is, at the position where the maximum stress generated in the main surface of the p-type well region 2M at the open end of the sidewall spacer 9 is concentrated, the main surface portion of the p-type well region 2M is introduced when the n-type impurity is introduced. Displace the position where damage occurs.

<< Step of Forming Second Gate Insulating Film >> Next, the transfer MISFET Qt of the memory cell array MAY, the n-channel MISFET Qn of the peripheral circuit, and the p-channel MIS.
In each forming region of the FET Qp, a threshold voltage adjusting impurity is introduced into the main surface portion of each active region of the p--type well region 2M, the p--type well region 2 and the n--type well region 3. A p-type impurity such as BF ₂ is used as the threshold voltage adjusting impurity. BF ₂ uses ion implantation, for example, with energy of about 40 to 60 [KeV]
It is introduced at an impurity concentration of about 0 ¹² to 10 ¹³ [atoms / cm ² ]. BF ₂ is introduced into the main surface portions of the p − type well region 2M, the p − type well region 2 and the n − type well region 3 through a silicon oxide film formed on the main surface of the active region.

Next, the transfer MISFET Qt of the memory cell array MAY and the n-channel MISFE of the peripheral circuit.
In the respective formation regions of TQn and p-channel MISFETQp, the silicon oxide film on the main surface of each active region of p--type well region 2M, p--type well region 2 and n--type well region 3 is removed, and The main surface is exposed.

Next, the exposed p--type well region 2 is formed.
A gate insulating film 12 is formed on the main surface of each active region of the M, p-type well region 2 and the n-type well region 3. The gate insulating film 12 is formed by a thermal oxidation method, for example, 13 to 14
It is formed with a film thickness of about [nm]. The gate insulating film 12 is
MISFETQt for transfer of memory cell MC, n-channel MISFETQn of peripheral circuit, p-channel MISFET
Used as each gate insulating film of Qp.

<< Step of Forming Second Layer Gate Material >> Next, a polycrystalline silicon film 13A (electrode layer having a three-layer structure) is formed on the entire main surface of the p--type semiconductor substrate 1 including the gate insulating film 12. Bottom layer). This polycrystalline silicon film 13A is the second
It is formed by the gate material forming step of the first layer. The polycrystalline silicon film 13A is deposited by the CVD method using Si ₂ H ₆ and PH ₃ as the source gas, like the polycrystalline silicon film of the gate electrode 7. In the case of this embodiment, the polycrystalline silicon film 13A is
For the purpose of improving the withstand voltage of the underlying gate insulating film 13A, P is introduced at an impurity concentration of, for example, about 1 × 10 ^{20 to} 3 × 10 ²⁰ [atoms / cm ³ ]. In addition, the polycrystalline silicon film 1
3A is, for example, 30 to 50 for the purpose of flattening the upper layer.
It is formed with a thin film thickness of about [nm].

Next, the source region (10) of the driving MISFET Qd of the memory cell MC of the memory cell array MAY.
In the connection region between the upper source region and the reference voltage line (Vss, 13), the polycrystalline silicon film 13A and the gate insulating film 12 therebelow are sequentially removed to form a connection hole 14.
The connection hole 14 is formed by performing anisotropic etching such as RIE using a mask formed by photolithography. This connection hole 14 is for driving MISFETQ.
The source region of d and the reference voltage line (13) are connected to each other. After forming a clean gate insulating film 12, directly
Since the polycrystalline silicon film 13A is formed on the gate insulating film 12 and the connection hole 14 is formed after this, the mask forming the connection hole 14 does not directly contact the surface of the gate insulating film 12. That is, in the step of forming the connection hole 14, the gate insulating film 12 is not contaminated due to the formation of the mask and the peeling of the mask, so that the withstand voltage of the gate insulating film 12 does not deteriorate.

Next, p including the polycrystalline silicon film 13A is formed.
The polycrystalline silicon film 13 is formed on the entire main surface of the-type semiconductor substrate 1.
B and the refractory metal silicide film 13C are sequentially formed. The polycrystalline silicon film 13B is formed by the gate material forming step of the second layer. The polycrystalline silicon film 13B is deposited by the CVD method using Si ₂ H ₆ and PH ₃ as the source gas, like the polycrystalline silicon film of the gate electrode 7. In the case of the present embodiment, the polycrystalline silicon film 13B is directly connected to the surface of the source region (10) as the reference voltage line (13), and therefore, for the purpose of improving the contact resistance value in this connection, for example, 4 × 1
P to an impurity concentration of about 0 ^{20 to} 6 × 10 ²⁰ [atoms / cm ³ ].
Will be introduced. That is, P is introduced into the intermediate polycrystalline silicon film 13B at a higher impurity concentration than the impurity concentration of P introduced into the lower polycrystalline silicon film 13A. The polycrystalline silicon film 13B is formed with a thin film thickness of, for example, about 30 to 50 [nm] for the purpose of flattening the upper layer. The refractory metal silicide film 13C is formed in the second layer gate material forming step. A part of the refractory metal silicide film 13C is connected to the source region of the driving MISFET Qd through the connection hole 14 and the intermediate polycrystalline silicon film 13B. The refractory metal silicide film 13C is formed of WSi ₂ deposited by the CVD method or the sputtering method. WSi ₂ is a highly stable gate material in mass production. Refractory metal silicide film 13C
Has a smaller specific resistance than the polycrystalline silicon films 13A and 13B, and is formed with a relatively thin film thickness of, for example, about 80 to 100 [nm] in order to suppress the growth of the step shape of the upper layer. It

Next, an insulating film 15 is formed on the entire main surface of the p--type semiconductor substrate 1 including the refractory metal silicide film 13C. This insulating film 15 is, for example, 200 to 400 [n
The film thickness is about m]. The insulating film 15 uses, for example, organic silane (Si (OC ₂ H ₅ ) ₄ ) as a source gas, and has a high temperature (eg, 700 to 850 [° C.]) and a low pressure (eg, 1.0 [torr]) CVD method. It is formed of a silicon oxide film deposited by.

Next, as shown in FIG. 27 , the insulating film 1
5, the refractory metal silicide film 13C, the polycrystalline silicon film 13B, and the polycrystalline silicon film 13A are sequentially patterned,
Polycrystalline silicon films 13A and 13B and refractory metal silicide film 13
A gate electrode 13 having a laminated structure made of C is formed.
The gate electrode 13 is a transfer MISFET of the memory cell MC.
It is used as the gate electrode of each of Qt, the n-channel MISFET Qn and the p-channel MISFET Qp of the peripheral circuit. In the same manufacturing process as the process of forming the gate electrode 13, the word line (WL) 13 and the reference voltage line (Vss) 1
Each of the three is formed. The patterning is performed by using a mask formed by a photolithography technique and performing RIE.
Etching is performed by anisotropic etching. Further, the dummy word line 13D1 and the like shown in FIG. 12 described above are formed by the step of forming the gate electrode 13.

<< Step of Forming Second Source Region and Drain Region >> Next, the memory cell MC of the memory cell array MAY.
Transfer MISFETQt, drive MISFETQd,
In each formation region of the n channel MISFETQn of the peripheral circuit, an n type impurity is introduced into the main surface portion of the active region of the p--type well region 2M. This n-type impurity is introduced for the purpose of forming the n-type semiconductor region (17) having a low impurity concentration of the LDD structure, and the impurity concentration gradient is set to be P gentler than As in order to weaken the electric field strength near the drain region. use. P uses ion implantation, for example 40-60
1 × 10 ^{13 to} 3 × 10 with energy of about [KeV]
It is introduced with an impurity concentration of about ¹³ [atoms / cm ² ]. P
Is a driving MI using the gate electrode 13 (actually the insulating film 15 or a mask for patterning the same) as an impurity introduction mask in the formation regions of the transfer MISFET Qt and the n-channel MISFET Qn of the memory cell MC.
In the formation region of the SFET Qd, the gate electrode 7 (actually the insulating film 9T) is used as an impurity introduction mask,
The gate electrodes 13 and 7 are introduced in a self-aligned manner.

Thereafter, heat treatment is performed to elongate and diffuse the P to form an n-type semiconductor region 17 having a low impurity concentration (see FIG. 28 ). The heat treatment is performed, for example, in argon (Ar) at a high temperature of 900 to 1000 [° C.] for about 15 minutes.
~ 25 [minutes]. Based on this heat treatment, the n-type semiconductor region 17 has the transfer MISFET Qt, the n-channel M
The amount of diffusion of the ISFET Qn toward each channel formation region increases, and the ISFET Qn appropriately overlaps the gate electrode 13 after the manufacturing process is completed.

Next, although not shown, in the formation region of p channel MISFETQp of the peripheral circuit, p type impurities are introduced into the main surface portion of the active region of n--type well region 3.
This p-type impurity is introduced for the purpose of forming a p-type semiconductor region (39) having a low impurity concentration in the LDD structure ( FIG. 16 ) .
reference). BF ₂ is used as the p-type impurity. This BF
₂ uses ion implantation, for example, 30 to 50 [Ke
V] energy of 3 × 10 ^{12 to} 7 × 10 ¹² [atoms
/ Cm ² ]. BF ₂ is introduced in self-alignment with the gate electrode 13 using the gate electrode 13 as an impurity introduction mask. By introducing this p-type impurity, L of the p-channel MISFET Qp
Low impurity concentration p-type semiconductor region 3 forming a DD structure
9 is formed. Since the diffusion rate of p-type impurities is higher than that of n-type impurities, the p-type semiconductor region can form a sufficient overlap with the gate electrode 13 without heat treatment.

Next, the above-mentioned gate electrode 13 and insulating film 15 are formed.
Sidewall spacers 16 are formed on the respective side walls. The sidewall spacer 16 is formed by depositing a silicon oxide film on the entire main surface of the p − type semiconductor substrate 1 including the insulating film 15, and etching the entire surface of the silicon oxide film by an amount corresponding to the deposited film thickness. It is formed by The silicon oxide film is deposited by a CVD method using an inorganic silane gas as a source gas as described above, and is, for example, 250 to 300 [nm].
It is formed with a film thickness of about. For the etching, anisotropic etching such as RIE is used.

Next, at the time of etching for forming the sidewall spacers 16, the p--type well regions 2M, p--type well regions 2, n-- in the regions other than the regions where the gate electrodes 13 and the sidewall spacers 16 are formed. Type well region 3
Since the main surface of each active region is exposed, a silicon oxide film (no reference numeral is formed) is formed on the entire main surface of p--type semiconductor substrate 1 including the exposed region. This silicon oxide film is formed along the surface of the sidewall spacer 16 as in the above-described insulating film 9T. The silicon oxide film is used for the purpose of preventing contamination when introducing impurities and preventing damage to the main surface of the active region due to the introduction of impurities. Further, this silicon oxide film is formed in the p-type well region 2 at the open end of the sidewall spacer 16 like the insulating film 9T.
The position of the region of damage generated when the impurities (the respective impurities forming the semiconductor regions 18 and 40 respectively) introduced in the subsequent step are introduced with respect to the position of the maximum stress concentration on the main surface of M. Also used for the purpose of shifting. The silicon oxide film is formed by, for example, a thermal oxidation method and has a film thickness of about 10 to 20 [nm].

Next, the transfer MISFET Qt and the drive MISFET of the memory cell MC of the memory cell array MAY.
In each of the formation regions of Qd and the n-channel MISFET Qn of the peripheral circuit, an n-type impurity is introduced into the main surface portion of each active region of the p-type well region 2M and the p-type well region 2. As the n-type impurity, As having a slower diffusion rate than P is used for the purpose of making the pn junction depth shallow. As is ion-implanted and is introduced with an energy of about 30 to 50 [KeV] and an impurity concentration of about 1 × 10 ^{15 to} 5 × 10 ¹⁵ [atoms / cm ² ]. This As is the gate electrode 7,
13, side wall spacers 9 and 16 and insulating film 9T
Etc. are used as an impurity introduction mask, and they are introduced in self-alignment with respect to them.

Thereafter, heat treatment is performed to extend and diffuse the n-type impurities to form n + -type semiconductor regions 11 and 18 having high impurity concentrations, respectively, as shown in FIG .
The heat treatment is performed, for example, in nitrogen gas at a high temperature of 800 to 900 [° C.] for about 15 to 20 [minutes]. Each of the n + type semiconductor regions 11 and 18 is used as a source region and a drain region.

By the step of forming the n + type semiconductor region 11, the driving MISFET Qd adopting the DDD structure of the memory cell MC is completed, and by the step of forming the n + type semiconductor region 18, the transfer adopting the LDD structure is performed. For MIS
FETQt is completed. Further, the n-channel MISFET Qn adopting the LDD structure of the peripheral circuit is completed by the process of forming the n + type semiconductor region 18 (see FIG. 16 ). Also, as shown in FIGS. 11 to 15 , the n +
By forming the type semiconductor regions 11 and 18, n-
Guard ring region N-GR formed of n + type semiconductor regions 11 and 18 arranged in the peripheral region of the type well region 3.
Is completed.

<< Third Layer Gate Material Forming Step >> Next, p
Etching the whole main surface of the -type semiconductor substrate 1,
The insulating film formed on the gate electrode 7 of the driving MISFET Qd of the memory cell MC of the memory cell array MAY is mainly removed. The removal of this insulating film is performed by the gate electrode 1
3, the insulating film 15 and the sidewall spacers 16 formed on the word line 13 and the reference voltage line 13, respectively, are used as an etching mask (the regions defined by these masks are removed). That is, the insulating film existing under each of the gate electrode 13, the word line 13, and the reference voltage line 13 remains. This removal of the insulating film is mainly performed by the drive MI which becomes the first electrode 7 of the capacitive element C of the memory cell MC.
This is performed for the purpose of exposing the surface of the gate electrode 7 of the SFET Qd. The insulating film above the gate electrode 7, that is, the first electrode 7 is formed of the silicon oxide film as described above, and
Insulating film 15 and side wall spacers 16 above
Is formed of a silicon oxide film as described above, and an etching rate difference cannot be secured, but since the insulating film 15 and the sidewall spacers 16 are formed to be thick, this insulating film 1
5 and the sidewall spacers 16 can remove only the insulating film on the first electrode 7 in a state where they remain.

Next, the gate electrode 7, that is, the first electrode 7
An insulating film 21 is formed on the entire main surface of the p- type semiconductor substrate 1 including the exposed surface of the. The insulating film 21 is mainly used as the dielectric film 21 of the capacitive element C of the memory cell MC. The insulating film 21 is formed of, for example, a silicon oxide film deposited by a CVD method using inorganic silane as a source gas. The first electrode 7 of the capacitive element C is a CV whose source gas is Si ₂ H _6.
The insulating film 21 is deposited by the D method and can flatten the surface.
The withstand voltage can be improved, and as a result, the film thickness of the insulating film 21 can be reduced. Further, since the insulating film 21 is formed of a single-layer silicon oxide film, it can be formed with a thin film thickness, for example, 40 to 50.
It is formed with a thin film thickness of about [nm].

Next, transfer MISFE of the memory cell MC
On one semiconductor region (18) and the other semiconductor region (18) of TQt, the insulating film 21 and the insulating film below it are removed to form a connection hole 22 (see FIG. 29 ). The connection hole 22 formed on one semiconductor region of the transfer MISFET Qt includes the one semiconductor region, the drain region (11) of the driving MISFET Qd, the gate electrode 7, and the second electrode (23) of the capacitor C, respectively. Are formed for the purpose of connecting (the connection points of the four elements of the memory cell MC). The connection hole 22 formed on the other semiconductor region of the transfer MISFET Qt is formed for the purpose of connecting the other semiconductor region and the intermediate conductive layer (23).
The connection hole 22 formed in the latter insulating film 22 is formed with a larger opening size on the gate electrode 13 side than the side wall spacer 16 provided on the side wall of the gate electrode 13 of the transfer MISFET Qt. That is, the insulating film 21
The surface of the side wall spacer 16 is exposed in the connection hole 22 formed in the above, and the substantial opening size of the connection hole 22 on the other semiconductor region (18) is defined by the side wall spacer 16. Therefore, the substantial connection hole 22
Since the side wall spacer 16 is formed in self alignment with the gate electrode 13, the opening position on the side of the gate electrode 13 is consequently defined in self alignment with the gate electrode 13. For the connection hole 22, a mask formed by a photolithography technique (in FIG. 29 , reference numeral 22M is attached and a part of the mask is shown by a broken line) is used, and the insulating film 21 is removed by anisotropic etching such as RIE. Is formed by. Further, since the insulating film 21 is thin as described above,
The contact hole 22 may be formed by using isotropic etching.

Next, the above-mentioned mask in which the connection hole 22 is formed (in FIG. 29 , a mask denoted by reference numeral 22M and shown by a broken line).
In the area defined by the mask (at the substantially same pattern and substantially the same position as the connection holes 22), the n-type semiconductor substrate 1 is provided with n on the main surface.
A type impurity is introduced to form an n + type semiconductor region 21N as shown in FIG . This n + type semiconductor region 21N
Is formed to a depth such that crystal defects generated from the main surface of the p − type semiconductor substrate 1 can be taken in at the opening end of the connection hole 22. As the n-type impurity forming the n + -type semiconductor region 21N, for example, P whose diffusion rate is faster than As is used,
12 at an impurity concentration of about 10 ¹⁴ to 10 ¹⁵ [atoms / cm ² ].
It is introduced by ion implantation with an energy of about 0 to 130 [KeV]. The junction depths of the n + type semiconductor region 18 of the transfer MISFET Qt and the n + type semiconductor region 11 of the driving MISFET Qd are formed to be about 0.2 to 0.3 [μm]. On the other hand, the n + type semiconductor region 21N formed under the above conditions is the same as the n + type semiconductor region 1
The junction depth is deeper than the respective junction depths of 1 and 18, for example, about 0.3 to 0.4 [μm].

Since the n + type semiconductor region 21N is formed by using the mask (22M) for forming the contact hole 22 in the insulating film 21, another mask other than the mask for forming the contact hole 22 is used. Since it is not necessary to form it, the number of manufacturing process steps can be reduced.

In the connection hole 22, the n-type transfer MISFET Qt is formed on the main surface of the p--type semiconductor substrate 1.
In addition to the + type semiconductor region 18 and the n + type semiconductor region 11 of the driving MISFET Qd, an n + type semiconductor region 21
N is added to the n + type semiconductor regions 11, 18 and 21N.
Since the impurity concentration of the synthesized surface can be increased, the contact resistance value with the conductive layer 23 formed in a later step can be reduced. In other words, the conductive layer 23 is formed of a polycrystalline silicon film, and the n-type impurity is introduced into the polycrystalline silicon film to the saturation region or to a degree close to the saturation region. The impurity concentration of can be reduced. If the impurity concentration of the n-type impurities introduced into the conductive layer 23 can be reduced, the flow-out (diffusion) of the n-type impurities from the conductive layer 23 to the p-type semiconductor substrate 1 side can be reduced.
N-type semiconductor region (LD with low impurity concentration of SFET Qt
The D part 17 is converted into a region having a high impurity concentration (apparently, the n-type semiconductor region 17 has a high impurity concentration n).
(Eating by the + type semiconductor region 18) can be prevented.

In the n + type semiconductor region 21N, after the insulating film 21 is formed, the mask (22M) is formed, and before the connection hole 22 is formed, an n type impurity is passed through the insulating film 21. You may form by introducing.
In this case, as described above, the number of steps of the manufacturing process can be reduced, and the insulating film 21 can be introduced when the n-type impurity is introduced.
Is present, the contamination due to the introduction of the n-type impurity can be prevented, and the main surface of the p- type semiconductor substrate 1 (actually, the main surface of the n + type semiconductor regions 11 and 18) is damaged. Can be prevented.

Then, a polycrystalline silicon film (23) is deposited on the entire main surface of the p--type semiconductor substrate 1 including the insulating film 21 serving as the dielectric film (see FIG. 30 ). This polycrystalline silicon film is formed in the gate material forming step of the third layer. A part of the polycrystalline silicon film is transferred through the connection hole 22 to the transfer MIS.
One semiconductor region (18) of the FET Qt, drive MIS
It is connected to the drain region (11) of the FET Qd and the gate electrode 7. This polycrystalline silicon film is a load MISFETQ.
p gate electrode (23), capacitive element C second electrode (2
3), the conductive layer (23) and the intermediate conductive layer (23), respectively. Particularly, the polycrystalline silicon film is used for the load MI.
Since it is used as the gate electrode (23) of the SFET Qp and the second electrode (23) of the capacitive element C, S
It is deposited by a CVD method using i ₂ H ₆ and PH ₃ as a source gas (doped polysilicon). The deposition temperature of the polycrystalline silicon film by the CVD method is set to about 680 to 720 [° C.]. The polycrystalline silicon film is formed with a thin film thickness of, for example, about 60 to 80 [nm] in order to suppress the growth of the step shape of the upper layer, and has a P concentration of about 10 ²⁰ to 10 ²¹ [atoms / cm ³ ]. Will be introduced.

Next, the polycrystalline silicon film is patterned to form the gate electrode 23 of the load MISFET Qp, the second electrode 23 of the capacitive element C, the conductive layer 23, and the intermediate conductive layer 23.
Form each of. This polycrystalline silicon film is patterned by using a mask formed by, for example, a photolithography technique and performing anisotropic etching such as RIE.

By the step of forming the second electrode 23,
The capacitive element C in which the first electrode 7, the dielectric film 21, and the second electrode 23 are sequentially laminated is completed.

Next, the gate electrode 23 of the load MISFET Qp, the second electrode 23 of the capacitive element C, the conductive layer 23,
Each surface of the intermediate conductive layer 23 is subjected to thermal oxidation treatment to form a silicon oxide film 24G on each surface (see FIG. 30 ).
The thermal oxidation treatment is performed in an oxygen gas atmosphere (O ₂ dry) of 800 to 900 ° C. for about 15 to 25 minutes, and the silicon oxide film 24G has a thickness of about 5 to 15 nm as described above. Formed in thickness. By forming the silicon oxide film 24G, the gate electrode 23, the second electrode 23 of the capacitor C, the conductive layer 23,
The cross-sectional shape of the corner portion (corresponding to the corner portion 23C shown in FIG. 17 ) of each surface of the intermediate conductive layer 23 can be improved. This silicon oxide film 24G is used in the SRAM of this embodiment.
It is also used as the gate insulating film (24) of the load MISFET Qp formed in a later step.

<< Step of Forming Third Source Region and Drain Region >> Next, in the formation region of the p-channel MISFET Qp of the peripheral circuit, p-type impurities are introduced into the main surface portion of the active region of the n--type well region 3 (see FIG. 16 ). BF ₂ is used as the p-type impurity. BF ₂ uses ion implantation and is 2 × with energy of, for example, about 50 to 70 [KeV].
The impurity concentration is about 10 ^{15 to} 6 × 10 ¹⁵ [atoms / cm ² ]. BF ₂ is introduced in self-alignment with the gate electrode 13 and the sidewall spacer 16 using the gate electrode 13 and the sidewall spacer 16 as an impurity introduction mask. By introducing this p-type impurity, the p + -type semiconductor region 40 having a high impurity concentration is formed, and the p-channel MISFET Qp adopting the LDD structure of the peripheral circuit is completed.

The p + type semiconductor region 40 is the outer periphery of the memory cell array MAY and is located in the p − type well region 2.
Also formed on the main surface of the peripheral region of M, this p + type semiconductor region 40 forms a guard ring region P-GR ( FIG. 1 ) .
5 ).

Next, as shown in FIG. 30 , the load M
Sidewall spacers (reference numeral 24S in FIG. 17 above) are formed on the respective side walls of the gate electrode 23 of the ISFET Qp, the second electrode 23 of the capacitor C, the conductive layer 23, and the intermediate conductive layer 23 .
Are shown). The side wall spacer 24S alleviates the steep step shape of the side walls of the gate electrode 23, the second electrode 23, etc., and flattens the upper layer (especially, the fourth layer including the channel formation region 26N of the load MISFET Qp). It is formed for the purpose of flattening the gate material).
The side wall spacers 24S are formed by depositing a silicon oxide film on the entire main surface of the p − type semiconductor substrate 1 including the upper layer of the gate electrode 23, and an anisotropic etching such as RIE corresponding to the deposited film thickness. It is formed by applying. The silicon oxide film of the sidewall spacer 24S is deposited by, for example, a CVD method using inorganic silane as a source gas, and has a thickness of 80 to 120.
It is deposited with a film thickness of about [nm].

Further, in the SRAM of this embodiment, the cross section of the corner portion 23C on the surface of each of the gate electrode 23 of the load MISFET Qp, the second electrode 23 of the capacitive element C, the conductive layer 23, and the intermediate conductive layer 23 described above. The step of forming the silicon oxide film 24G for improving the shape is performed by the sidewall spacer 24S.
It may be performed after the formation of.

<< Step of Forming Third Gate Insulating Film >> Next, on the main surface of the p--type semiconductor substrate 1 including the upper portions of the gate electrode 23, the second electrode 23, the conductive layer 23, and the intermediate conductive layer 23, respectively. An insulating film 24 is formed on the entire surface of the. The insulating film 24 includes a conductive layer such as the lower gate electrode 23 and an upper conductive layer (2
Each of 6) is electrically separated and the load MIS
It is used as the gate insulating film 24 of the FET Qp. The insulating film 24 is formed of a silicon oxide film deposited by a CVD method using an inorganic silane gas as a source gas, like the dielectric film 21 of the capacitive element C described above. The insulating film 24 has, for example, 50 to 70 [n] for the purpose of ensuring the withstand voltage and ensuring the conduction characteristic (ON characteristic) of the load MISFET Qp.
The film thickness is about m].

<< Fourth Layer Gate Material Forming Step >> Next, a connection hole 25 is formed in the insulating film 24 above the conductive layer 23 of the memory cell MC of the memory cell array MAY. The connection holes 25 are formed by the lower conductive layer 23 and the upper conductive layer (2
6. Actually, it is formed for the purpose of connecting each of the n-type channel forming regions 26N) of the load MISFET Qp.

Next, a polycrystalline silicon film is formed on the entire surface including the insulating film 24. This polycrystalline silicon film is formed by the gate material forming step of the fourth layer. The polycrystalline silicon film serves as an n-type channel forming region (26
N), source region (26P), power supply voltage line (Vcc: 26)
Form each of P). The polycrystalline silicon film is different from the above-mentioned polycrystalline silicon films (7, 13A, 13B and 23, respectively).
It is formed of so-called non-doped polysilicon deposited by a CVD method using Si ₂ H ₆ as a source gas. This polycrystalline silicon film is formed with a thin film thickness of, for example, about 30 to 50 nm. That is, the polycrystalline silicon film is formed with a film thickness larger than the film thickness of the crystal grains that does not affect the uniformity of the film thickness and smaller than the film thickness that can reduce the leakage current of the load MISFET Qp. It is formed.

<< Formation Step of Fourth Source Region and Drain Region >> Next, although not shown, the polycrystalline silicon film (26) is formed.
An insulating film is formed thereover. This insulating film is formed for the purpose of preventing contamination that occurs when impurities are introduced in a later step and mitigating surface damage. The insulating film is formed of, for example, a silicon oxide film formed by a thermal oxidation method, and has a thin film thickness of about 4 to 6 [nm]. Further, since this insulating film is formed by using a thermal oxidation method using an oxygen gas atmosphere, oxygen in the oxygen gas atmosphere is bonded to a dangling bond of silicon in the polycrystalline silicon film, This dangling bond can be reduced. By reducing the dangling bonds, the amount of current flowing between the source region and the drain region of the load MISFET Qp can be increased, and the current of the load MISFET Qp-
The voltage characteristics can be improved.

Next, a threshold voltage adjusting impurity is introduced into the entire surface of the polycrystalline silicon film. An n-type impurity such as P is used as the threshold voltage adjusting impurity. P is for load M
It is introduced for the purpose of enhancing the threshold voltage of ISFET Qp. The enhancement type threshold voltage is obtained with an impurity concentration of about 10 ¹⁷ to 10 ¹⁸ [atoms / cm ³ ]. Therefore, P uses ion implantation and has an energy of about 20 to 40 [KeV] and is about 10 ¹² to
It is introduced with an impurity concentration of about 10 ¹³ [atoms / cm ² ].
The impurity concentration of P introduced into the polycrystalline silicon film is 10 ¹⁸ [at
oms / cm ³ ], the polycrystalline silicon film acts as a high resistance element because the threshold voltage rises (becomes larger in absolute value). That is, the load MISFET Qp has the n-type channel formation region (2
Since the power supply voltage Vcc can be supplied to the information storage node region of the memory cell MC only in a current corresponding to the leakage current in 6N), the information retention characteristic deteriorates. Further, when the impurity concentration of P introduced into the polycrystalline silicon film is further increased and the threshold voltage is increased, the amount of leak current increases. This increase in leak current hinders power consumption. By the step of introducing the threshold voltage adjusting impurities, the n-type channel forming region 26N is formed (see FIG. 31 ).

Next, the source region (26 of the load MISFET Qp of the memory cell MC of the memory cell array MAY).
In the formation region of P) and the formation region of the power supply voltage line (Vcc: 26P), p-type impurities are introduced into the polycrystalline silicon film (26). The p-type impurity is introduced into the region surrounded by the alternate long and short dash line with reference numeral 26P in FIGS . 7 and 9 using BF ₂ , for example. This BF ₂ is introduced by ion implantation, for example, with an energy of about 20 to 40 [KeV] and an impurity concentration of about 10 ¹⁴ to 10 ¹⁵ [atoms / cm ² ]. A mask formed by a photolithography technique is used for introducing the p-type impurity.

Next, the silicon oxide film formed on the surface of the polycrystalline silicon film (26) is removed. The stepped shape of the underlying layer is transmitted to the surface of the polycrystalline silicon film formed on the surface of the underlying insulating film (gate insulating film) 24 having the stepped shape. The silicon oxide film formed on the surface of the polycrystalline silicon film to which the step shape has been transferred can be removed by anisotropic etching in the flat area, but the film thickness in the step area becomes apparently thick. However, it cannot be removed by anisotropic etching. Therefore, the silicon oxide film formed on the surface of the polycrystalline silicon film is isotropically etched for the purpose of removing both the flat region and the step region. To be done. If it is not removed by isotropic etching, the silicon oxide film is not removed in the step region, and this silicon oxide film serves as an etching mask to form the polycrystalline silicon film in the patterning step of the lower polycrystalline silicon film. Etching residue occurs.

Then, as shown in FIG. 31 , the polycrystalline silicon film is patterned to form the n-type channel forming region 2.
6N, the source region 26P, and the power supply voltage line 26P are formed. For patterning the polycrystalline silicon film, for example, a mask formed by a photolithography technique is used and RI is used.
An anisotropic etching such as E is performed. When the n-type channel forming region 26N and the source region 26P are formed, the load MISFET Qp of the memory cell MC is completed. The memory cell MC is completed by the completion of the load MISFET Qp.

<< First Layer Metal Wiring Forming Step >> Next, an interlayer insulating film 27 is formed on the entire surface including the memory cell MC. The interlayer insulating film 27 is formed of the silicon oxide film 27A and the BPSG film 2
7B, each of which has a laminated structure of two layers.

The lower silicon oxide film 27A is formed of the upper BPSG film.
It is formed for the purpose of preventing leakage of B and P contained in the film 27B to the lower layer side. The silicon oxide film 27A uses, for example, Si (OC ₂ H ₅ ) ₄ as a source gas, and has a high temperature (for example, 600 to 800 [° C.]) and a low pressure (for example, 1.0 [tor].
r]) is deposited by the CVD method. The silicon oxide film 27A is formed with a film thickness of, for example, about 140 to 160 [nm].

The upper BPSG film 27B is formed for the purpose of flattening the surface and suppressing the growth of the step shape of the upper layer. B
The PSG film 27B is mainly deposited by a CVD method using an inorganic silane (for example, SiH ₄ ) as a source gas. BPSG film 2
7B is deposited with a film thickness of, for example, about 280 to 320 [nm], and then glass flow is performed to flatten the surface. The glass flow is, for example, 800 to 900 [° C] in nitrogen gas.
At a high temperature of about 10 minutes.

Next, a connection hole 28 is formed in the interlayer insulating film 27. The connection hole 28 is formed on the intermediate conductive layer 23 formed on the other semiconductor region (18) of the transfer MISFET Qt of the memory cell MC in the memory cell array MAY. Further, the connection hole 28 is formed in the peripheral region of the memory cell array MAY, that is, in the upper part of the p + type semiconductor region 40 of the guard ring region P-GR, in the guard ring region N-G.
The n + type semiconductor regions 11 and 18 of R are also formed on the respective upper portions. The connection hole 28 is formed by anisotropic etching such as RIE using a mask formed by photolithography.

Next, a refractory metal film 29 is formed on the entire surface including the interlayer insulating film 27. The refractory metal film 29 is the first
It is formed in the metal wiring forming process of the first layer. The refractory metal film 29 is formed of, for example, a W film deposited by a sputtering method.
When deposited by the CVD method, the W film has good step coverage in the step-shaped portion, but is easily peeled off from the surface of the interlayer insulating film 27. The W film deposited by the sputtering method has an advantage that it has high adhesiveness on the surface of the interlayer insulating film 27, but has a drawback that step coverage is poor and, if the film thickness is large, internal stress increases. Therefore, the SRAM of this embodiment
Takes advantage of the high adhesiveness of the W film, flattens the surface of the interlayer insulating film 27 underlying the W film (steps of glass flow using the BPSG film 27B), and copes with the step coverage of the W film. Deal with internal stress by making it thinner. The W film is formed as a thin metal wiring with a film thickness of, for example, about 280 to 320 [nm].

Next, as shown in FIG. 32 , the refractory metal film 29 is patterned to form a memory cell array M.
In AY, the main word line (MWL) 29, the sub word line (SWL) 29, and the intermediate conductive layer 29 are formed. A part of the intermediate conductive layer 29 is connected to the lower intermediate conductive layer 23 through the connection hole 28. This intermediate conductive layer 23
Is connected to the other semiconductor region (18) of the transfer MISFET Qt of the memory cell MC. Further, in regions other than the memory cell array MAY, for example, in the upper part of the p + type semiconductor region 40 of the guard ring region P-GR, the reference voltage line (Vss) 29 is formed, and the n + type semiconductor of the guard ring region N-GR is formed. It is formed as a power supply voltage line (Vcc) 29 in the upper part of the regions 11 and 18 (see FIG.
15 and FIG. 14 ). The refractory metal film 29 is patterned by anisotropic etching using a mask formed by photolithography, for example.

<< Step of Forming Second Layer Metal Wiring >> Next, an interlayer insulating film 30 is formed on the entire surface including the main word lines 29, the sub word lines 29, the intermediate conductive layer 29 and the like.
The interlayer insulating film 30 includes a silicon oxide film 30A and a silicon oxide film 30.
B and the silicon oxide film 30C are sequentially laminated to form a three-layer laminated structure.

The lower silicon oxide film 30A is deposited by the plasma CVD method using tetraethoxysilane gas (TEOS: Si (OC ₂ H ₅ ) ₄ ) as a source gas. Silicon oxide film 3
0A can form a uniform film thickness in each of the flat portion and the step portion. For example, a concave portion (corresponding to the minimum wiring interval) between the main word line 29 and the sub word line 29 is buried and the surface thereof is covered. In the case of flattening, almost no overhang shape is generated, so a so-called nest is not generated. The silicon oxide film 30A is formed with a film thickness that is ½ or more of the minimum wiring interval, for example, about 400 to 600 [nm], for the purpose of filling the minimum wiring interval and flattening its surface. .

The silicon oxide film 30B of the intermediate layer is applied by spin-on-glass method to a film thickness of, for example, about 200 to 300 [nm], baked, and then entirely etched. The silicon oxide film 30B is mainly used for the interlayer insulating film 30.
Is formed for the purpose of flattening the surface of the. The entire surface etching is performed by using the lower conductive layer (29) and the upper conductive layer (3).
It is carried out under the condition that it is not left in the respective connection portions (inside the connection holes 31) of 3) and is left in the step portions.

Like the lower silicon oxide film 30A, the upper silicon oxide film 30C is deposited by the plasma CVD method using tetraethoxysilane gas as a source gas. The silicon oxide film 30C is formed to have a film thickness of, for example, about 300 to 500 [nm]. The silicon oxide film 30C mainly secures a film thickness necessary for insulation separation between upper and lower wiring layers as the interlayer insulating film 30, and covers the intermediate silicon oxide film 30B,
It is formed for the purpose of preventing the deterioration of the film quality of the intermediate silicon oxide film 30B.

Next, a connection hole 31 is formed in the interlayer insulating film 30. The connection hole 31 is formed by anisotropic etching such as RIE using a mask formed by photolithography, for example.

Next, as shown in FIG. 33 , complementary data lines (DL) 33 are formed on the interlayer insulating film 30 in the memory cell array MAY. In addition, as shown in FIG.
As shown in FIG. 15 , in the peripheral region of the memory cell array MAY, for example, on the p + type semiconductor region 40 of the guard ring region P-GR, the reference voltage line (Vss) 33 and the n + type semiconductor of the guard ring region N-GR are provided. Regions 11 and 1
Each of the power supply voltage lines (Vcc) 33 is formed on the wiring 8.

The complementary data line 33 (and the wiring 33)
Is formed in the second-layer metal wiring forming process. The complementary data line 33 passes through the connection hole 31 and is connected to the lower intermediate conductive layer 29.
Connected to. The complementary data line 33 is connected to the lower metal film 3
3A, an aluminum alloy film 33B as an intermediate layer, and a metal film 33C as an upper layer are sequentially laminated to form a two-layer laminated structure. The lower metal film 33A is formed of, for example, a TiW film deposited by a sputtering method and has a film thickness of about 30 to 50 [nm]. Since the lower metal film 33A mainly functions as a barrier metal film, a film other than the TiW film,
For example, it may be formed of a TiN film or the like. The intermediate aluminum alloy film 33B is formed by sputtering, and C
It is formed of aluminum to which at least one of u and Si is added, and has a film thickness of about 700 to 900 [nm]. The upper metal film 33C is formed of, for example, a TiW film deposited by a sputtering method, and is, for example, 150 to 2
It is formed with a film thickness of about 50 [nm]. The upper metal film 33C is mainly for the purpose of preventing a diffraction phenomenon (reducing the light reflectance and preventing the halation effect) when patterning the aluminum alloy film 33B of the intermediate layer, and also for aluminum hilllock. It is formed for the purpose of preventing.

<Final Passivation Film Forming Step> Next, as shown in FIGS . 6, 15 and 16 , the final passivation film 34 is formed on the entire surface including the complementary data lines 33. Although the final passivation film 34 does not show a detailed structure, a silicon oxide film, a silicon nitride film, and a resin film are sequentially laminated on each other.
It is composed of a layered structure.

The lower silicon oxide film is formed to have a laminated structure of three layers, and has the same structure as the above-described interlayer insulating film 30. That is, the lower silicon oxide film is a silicon oxide film deposited by a plasma CVD method using tetraethoxysilane gas as a source gas, a silicon oxide film that is etched after application and remains only in the step portion, and tetraethoxysilane gas as a source gas. The silicon oxide films deposited by the plasma CVD method are sequentially laminated. Each of the lower and upper silicon oxide films is a complementary data line 33.
Since it is formed after the aluminum alloy film 33B is formed, the above-mentioned CVD method that can be formed at a low temperature, for example, about 400 [° C.] or lower is used. The lower silicon oxide film is formed to have a thickness of, for example, about 400 to 600 [nm], and the intermediate silicon oxide film is formed to have a thickness of 200 to 300.
The upper silicon oxide film is formed with a film thickness of about [nm].
It is formed with a film thickness of about 00 to 900 [nm].

The intermediate silicon nitride film is formed mainly for the purpose of improving moisture resistance. The intermediate silicon nitride film is deposited by, for example, a plasma CVD method and is 1.0 to 1.4 [μm].
It is formed with a film thickness of about a certain degree.

The upper resin film is formed of, for example, a polyimide resin film, and is mainly formed for the purpose of blocking α rays.
The upper resin film is formed to have a film thickness of, for example, about 2.2 to 2.4 [μm].

When these series of manufacturing processes are performed,
The SRAM of this embodiment is completed.

According to the present invention, in the SRAM described above, the impurity concentration of the p--type well region 2M is formed in the main surface portion of the p--type well region 2M in which the memory cell array MAY of the n--type well isolation region 3i is arranged. A buried p + type semiconductor region having a higher impurity concentration than that of the above may be formed. The buried p + type semiconductor region functions as a potential barrier region for minority carriers, which improves so-called α-ray soft error resistance. For the buried p + type semiconductor region, for example, in the above-described SRAM manufacturing process, after forming the n type semiconductor region 10 shown in FIG. 25 , a mask having an opening in the memory cell array MAY is formed, and this mask is used. It can be formed by introducing a p-type impurity into the main surface of the p-type well region 2M. As the p-type impurity, monovalent B is used and is introduced by so-called high-energy ion implantation of about 200 to 250 [KeV] with an impurity concentration of about 10 ¹³ [atoms / cm ² ]. The buried p + type semiconductor region formed under these conditions is the memory cell M.
N + type semiconductor region 18 of C transfer MISFET Qt,
The peak value of the impurity concentration is set in a region deeper than the peak value of the impurity concentration of each of the n + type semiconductor regions 11 of the driving MISFET Qd.

Further, the present invention has a pn junction with the n + type semiconductor region 18 of the transfer MISFET Qt and the n + type semiconductor region 11 of the driving MISFET Qd, which are the information storage nodes of the memory cell MC, and a pn junction therewith. Further, similarly to them, the gate electrodes 7 and 13 may be used as the main body of the impurity introduction mask, and p-type impurities may be introduced by ion implantation to form the buried p + -type semiconductor region.

Further, in the present invention, in the SRAM,
The threshold voltage becomes high on the main surface of the n--type well region 3 formed on the outer peripheral main surface of the p--type well region 2M in which the memory cell array MAY of the n--type well isolation region 3i is arranged. Therefore, a layout in which the p-channel MISFET is not arranged is basically adopted. Further, a p-channel MISFET having a high threshold voltage may be positively arranged in this region.

The present invention also relates to the n + type semiconductor region 1 of the transfer MISFET Qt of the SRAM memory cell MC.
8, n + type semiconductor region 11 of the driving MISFET Qd,
In each connection region of the gate electrode 7 and the conductive layer 23,
The following manufacturing process may be adopted in order to reduce the occurrence of the above-mentioned crystal defects. That is, the insulating film 21 shown in FIG. 29 is formed, the connection hole 22 is formed, and then n
Without forming the + type semiconductor region 21N, a polycrystalline silicon film (23) is formed on the entire surface of the substrate, the polycrystalline silicon film is heat treated, and then the polycrystalline silicon film is patterned to form the conductive layer 23. Form. When the polycrystalline silicon film is subjected to the heat treatment, volumetric volume after the heat treatment occurs in the entire polycrystalline silicon film, so that stress is not concentrated only in the region of the connection hole 22.

The present invention also relates to the n + type semiconductor region 1 of the transfer MISFET Qt of the SRAM memory cell MC.
8. When each of the n + type semiconductor regions 11 of the driving MISFET Qd is stretched and diffused, the heat treatment is sufficiently performed to deepen the junction depth, and the crystal defects in the region of the connection hole 22 are n +.
It may be incorporated in each of the type semiconductor regions 11 and 18. In this case, the above-described step of forming the n + type semiconductor region 21N can be omitted.

Further, in the present invention, in the memory cell MC of the SRAM, the n-type channel forming region 26N, the p-type source region 26P and the p-type drain region 26P of the load MISFET Qp are formed as the third-layer gate material. The gate electrode 23 may be formed in the step, and the gate electrode 23 may be formed in the gate material forming step of the fourth layer. In this case, the gate material forming step of the third layer is not limited to the polycrystalline silicon film, and it suffices to form the semiconductor layer including both the single crystal silicon film and the amorphous silicon film. Similarly, the gate material forming step of the fourth layer is not limited to the polycrystalline silicon film, but includes a refractory metal film, a refractory metal silicide film,
Alternatively, a polycide film in which a refractory metal silicide film is laminated on the polycrystalline silicon film may be formed.

As described above, the SRAM of this embodiment
According to the above, the following effects can be obtained.

(1) An n--type well isolation region 3i is formed in the first region of the main surface of the p--type semiconductor substrate 1, and a p--type well is formed in the second region of the main surface of the p--type semiconductor substrate 1. The region 2 is formed, and the p − type well region 2M is formed on the main surface of the n − type well isolation region 3i. The p − type well region 2 and the p − type well region 2M are respectively formed on the main faces. In an SRAM having an n-channel MISFET, the impurity concentration on the surface of the p-type well region 2M is p-type.
The impurity concentration on the surface of the well region 2 is set to be equal to or higher than that.

With this structure, the following operational effects can be obtained. (1) The impurity concentration of the surface of the p--type well region 2M formed on the main surface of the n--type well isolation region 3i is set to be high (the impurity concentration of the surface is equal to the impurity concentration of the n--type well isolation region 3i). The lowering amount is corrected to increase the impurity concentration on the surface of the p-type well region 2M).
Since the threshold voltage of the n-channel MISFET of the memory cell MC on the main surface of the type well region 2M can be increased,
The cutoff current of the channel MISFET can be reduced, and S
The leak current of the RAM can be reduced. (2) The impurity concentration on the surface of the p-type well region 2 is set independently of the impurity concentration on the surface of the p-type well region 2M formed on the main surface of the n-type well isolation region 3i. , This p
-N-channel MIS of peripheral circuit on main surface of type well region 2
Since the threshold voltage of the FET can be lowered, the switching operation speed of the n-channel MISFET can be increased and the SRA
The circuit operation speed of M can be increased.

(2) SRA described in the means (1)
In M, p of the main surface of the n--type well isolation region 3i
-N-channel MI formed on the main surface of the well region 2M
The SFET constitutes a flip-flop circuit of the SRAM memory cell MC, and the n-channel MISFET formed on the main surface of the p-type well region 2 constitutes a peripheral circuit which directly or indirectly drives the SRAM memory cell MC. To do.

With this structure, in addition to the function and effect of the means (1), the following function and effect can be obtained. (1) Leakage of the information stored in the information storage node of the flip-flop circuit (information storage unit) of the memory cell MC is reduced, and as a result, inversion can be prevented, so that the information retention characteristic of the SRAM can be improved. (2) Since the circuit operation speed of the peripheral circuit can be increased, and both the information write operation speed and the information read operation speed of the memory cell can be increased (the access time can be increased), the SRAM circuit operation speed can be increased. Can be realized. (3) The p-type well region 2M described in the means (1) or (2) is self-aligned with the n-type well isolation region 3i.

With this structure, in addition to the function and effect of the means (1) or (2), the n-type well isolation region 3 is formed.
Since the arrangement position of the p − type well region 2M with respect to the arrangement position of i can be reduced by an amount corresponding to the mask alignment margin in the manufacturing process, a useless area on the main surface of the p − type semiconductor substrate 1 can be saved. Therefore, the integration degree of SRAM can be improved.

(4) The n--type well isolation region 3i is formed in the first region of the main surface of the p--type semiconductor substrate 1, and the p--type well is formed in the second region of the main surface of the p--type semiconductor substrate 1. In the SRAM in which the region 2 is formed and the p − type well region 2M is formed on the main surface of the n − type well isolation region 3i, the p − of the main surface of the n − type well isolation region 3i is formed.
An n-type well region 3 is formed in a region along the outer periphery of the type well region 2M.

With this structure, the impurity concentration around the outer periphery of the p--type well region 2M on the main surface of the n--type well isolation region 3i (in this portion, the impurity concentration is lowered by the deep diffusion of the n--type well isolation region 3i). Is increased in the n-type well region 3 and the depletion region extending from the pn junction between the n-type well region 3 and the p-type well region 2M into the n-type well isolation region 3i can be reduced. The junction breakdown voltage between the p-type well region 2M on the main surface of the n-type well isolation region 3i and the p-type semiconductor substrate 1 can be improved. If this junction breakdown voltage is improved, the distance between the p-type well region 2M on the main surface of the n-type well isolation region 3i and the p-type semiconductor substrate 1, that is, the main dimension of the n-type well isolation region 3i. Surface p
Since the area occupied by the outer periphery of the − type well region 2M can be reduced, it is possible to eliminate a useless region on the main surface of the p − type semiconductor substrate 1 and improve the integration degree of the SRAM.

(5) The n--type well isolation region 3i is formed in the first region of the main surface of the p--type semiconductor substrate 1, and the p--type well is formed in the second region of the main surface of the p--type semiconductor substrate 1. In the method of forming an SRAM in which the region 2 is formed and the p − type well region 2M is formed on the main surface of the n − type well isolation region 3i, the first surface is formed on the main surface of the p − type semiconductor substrate 1. Forming a first mask (50M) having an opening in one region, using the first mask (50M), introducing an n-type first impurity into the main surface of the p--type semiconductor substrate 1, and Diffusing a first impurity to form the n-type well isolation region 3i, the first mask (50M) is used, and a p-type second impurity ( 2Mp), removing the first mask (50M), A second mask having the second region opened on the main surface of the conductor substrate 1, or a second mask (52M) having the second region and the first region opened.
Forming the third impurity (2p), the second mask (52M) is used, and a p-type third impurity (2p) is introduced into the main surface of the p − -type semiconductor substrate 1. Two
Each step of diffusing each of the impurities (2 Mp) and forming each of the p--type well region 2 and the p--type well region 2M is provided.

With this structure, the following operational effects can be obtained. (1) A first mask (50) for forming an n--type well isolation region 3i in a first region of the main surface of the p--type semiconductor substrate 1.
M) is used to form the p-type well region 2M (the second mask 2Mp is introduced using the first mask 50M for introducing the first impurity), so that the p-type well region 2M is formed. Corresponding to the process of forming the mask,
The number of steps in the SRAM manufacturing process can be reduced. (2)
Using the process of diffusing the third impurity (2p) introduced into the second region of the main surface of the p − type semiconductor substrate 1 to form the p − type well region 2, the first impurity introduced into the first region is used. Since two impurities (2Mp) are diffused to form the p-type well region 2M, the number of steps in the SRAM manufacturing process is reduced by the amount corresponding to the step of diffusing the second impurity to form the p-type well region 2M. Can be reduced. (3) The p--type well region 2M formed on the main surface of the n--type well isolation region 3i in the first region of the main surface of the p--type semiconductor substrate 1 and the p--type well region 2 of the second region are formed. Since each is formed in a separate process, the p
The impurity concentrations of the − type well region 2M and the p− type well region 2 can be controlled independently. (4) The n--type well isolation region 3i is formed in the first region of the main surface of the p--type semiconductor substrate 1.
A p-type well region 2M is formed by using a first mask (50M) for forming the n-type well isolation region 3i and the p-type well region 2M. Therefore, the arrangement position of the p-type well region 2M is formed in self-alignment with the arrangement position of the n-type well isolation region 3i, and the arrangement position of the n-type well isolation region 3i is formed. p-type well region 2M
The arrangement position of can be reduced by the amount corresponding to the mask alignment margin in the manufacturing process.

(6) Load MISFETQ in which an n-type channel forming region 26N is formed on the surface of the gate electrode 23 with the gate insulating film 24 interposed therebetween and crossing the gate electrode 23.
In a method of forming an SRAM having p in a memory cell MC, a gate electrode layer (23) is deposited on the entire surface of a substrate,
The step of patterning this gate electrode layer to form the gate electrode 23, oxidizing part of the film thickness of the gate electrode 23 from its surface, and oxidizing it to a film thickness larger than that of the native silicon oxide film. Forming the silicon film 24G and relaxing the shape of the corner portion 23C of the surface of the gate electrode 23, forming the gate insulating film 24 on the surface of the gate electrode 23, upper and side surfaces of the surface of the gate electrode 23 To the gate electrode 2 with the gate insulating film 24 interposed.
3, and each of the steps of forming an n-type channel formation region 26N that crosses 3 is provided.

With this structure, the following operational effects can be obtained. (1) Load MISFETQ generated when the gate electrode layer (23) corresponding to the lower layer is patterned
The shape of the corner portion 23C of the surface of the gate electrode 23 of p is relaxed by the oxidation of the surface. (2) As a result of the action and effect (1),
Since the electric field concentration at the corner portion 23C of the surface of the gate electrode 23 below the load MISFET Qp can be reduced, the load M is reduced.
It is possible to prevent deterioration of the withstand voltage in the region of the corner portion 23C of the gate insulating film 24 of the ISFET Qp. (3) Further, as a result of the action and effect (1), the load MISFET Qp
Since it is possible to prevent the film quality from deteriorating at the corner portion 23C on the surface of the lower gate electrode 23, it is possible to prevent the breakdown voltage from degrading in the region of the corner portion 23C of the gate insulating film 24 of the load MISFET Qp.

(7) In the step of forming the gate insulating film 24 in the step described in the means (6), the surface of the gate electrode 23 is removed after the silicon oxide film 24G on the surface of the gate electrode 23 is removed. This is a step of newly forming the gate insulating film 24.

With this structure, since the gate insulating film 24 is newly formed in an independent process with respect to the silicon oxide film 24G formed on the surface of the gate electrode 23, the controllability of the film thickness of the gate insulating film 24 is improved. Can be improved.

(8) In the step of forming the gate insulating film 24 in the step described in the means (6), the silicon oxide film 24G on the surface of the gate electrode 23 in the step is used as the gate insulating film 24.
Or a composite film in which an insulating film 24F is newly deposited on the surface of the silicon oxide film 24G.
4 is a step of forming.

With this structure, in the step of forming the gate insulating film 24, the silicon oxide film 24G on the surface of the gate electrode 23 formed in the previous step is not removed. The number of steps in the manufacturing process can be reduced.

(9) Load MISFETQ in which an n-type channel forming region 26N is formed on the surface of the gate electrode 23 across the gate insulating film 24 and across the gate electrode 23.
In a method of forming an SRAM having p in a memory cell MC, a gate electrode layer (23) is deposited on the entire surface of a substrate,
This gate electrode layer is patterned to form the gate electrode 23, the sidewall spacer 24S is formed on the side surface of the gate electrode 23, and a part of the film thickness of the gate electrode 23 is oxidized from the surface thereof. , The silicon oxide film 24G having a thickness larger than that of the natural silicon oxide film
And a step of relaxing the shape of the corner portion 23C of the surface of the gate electrode 23, a step of forming a gate insulating film 24 on the surface of the gate electrode 23, and an upper surface and a side surface of the surface of the gate electrode 23. The gate insulating film 2
4, and an n-type channel forming region 26N is formed so as to cross the gate electrode 23.

With this configuration, in addition to the function and effect of the means (6), the step shape of the side surface of the gate electrode 23 of the load MISFET Qp, which occurs when the gate electrode layer 23 corresponding to the lower layer is patterned, has a side shape. It is alleviated by the wall spacer 24S.

(10) Means (6) to (10)
In the SRAM described in any one of 1, the load MISFET Qp constitutes a flip-flop circuit of the memory cell MC.

With this configuration, the load MISFETQ of the flip-flop circuit of the memory cell MC of the SRAM is formed.
In p, the gate electrode 23 and the n-type channel formation region 2
Since a short circuit with 6N (or p-type source region 26P or p-type drain region 26P) can be prevented, a standby current defect can be prevented.

(11) n of the driving MISFET Qd of the memory cell MC formed on the main surface of the p--type well region 2M
The n + type semiconductor region 1 is formed on the main surface of the + type semiconductor region 11.
SRAM to which a conductive layer 23 formed of a silicon film is connected through a connection hole 22 formed in an insulating film 21 on the first main surface of the SRAM 1.
Forming the n + type semiconductor region 11 on the main surface of the p− type well region 2M,
A step of forming an insulating film 21 on the main surface of the type semiconductor region 11, and forming a connection hole 22 on the n + type semiconductor region 11 of the insulating film 21 and a region corresponding to the inside of the connection hole 22. The n + is formed on the main surface of the p− type well region 2M.
Forming an n + type semiconductor region 21N having the same conductivity type as the type semiconductor region 11 and a junction depth deeper than that of the n + type semiconductor region 11, and forming the insulating film 21 on the entire surface of the insulating film 21. A silicon film (23) contacting the respective main surfaces of the n + type semiconductor region 11 and the n + type semiconductor region 21N through the formed connection hole 22 is deposited by the CVD method, and the silicon film is patterned to form a conductive layer. Each of the steps of forming 23 is provided.

With this structure, the following operational effects can be obtained. (1) Volume of a silicon film based on cooling after high temperature annealing during the deposition of the silicon film in the above process or high temperature annealing performed after the deposition of the silicon film (both are annealing at a temperature higher than the melting point of aluminum) A crystal defect which is generated by the contraction and which crosses the pn junction between the p @-type well region 2M and the n @ + type semiconductor region 11 from the end of the connection hole 22 of the insulating film 22 is formed in the n @ + type semiconductor region 21N. Can be taken in. (2) The mask 22M for forming the contact hole 22 in the insulating film 21 in the above step is formed on the n + type semiconductor region 2
Since it can be used also as an impurity implantation mask for forming 1N, the mask forming step can be reduced by the amount corresponding to the impurity implantation mask, and the number of steps of the SRAM manufacturing process can be reduced.

(12) n of the driving MISFET Qd of the memory cell MC formed on the main surface of the p--type well region 2M
The n + type semiconductor region 1 is formed on the main surface of the + type semiconductor region 11.
SRAM to which a conductive layer 23 formed of a silicon film is connected through a connection hole 22 formed in the insulating film 21 on the first main surface
Forming the n + type semiconductor region 11 on the main surface of the p− type well region 2M,
Forming an insulating film 21 on the main surface of the type semiconductor region 11, forming a contact hole 22 on the n + type semiconductor region 11 of the insulating film 21, and forming the insulating film 21 on the entire surface of the insulating film 21. A step of depositing a silicon film (23) in contact with the main surface of the n + type semiconductor region 11 through the connection hole 22 formed in the step, a step of performing high temperature annealing for crystallizing the silicon film, and a pattern on the silicon film. And the step of forming the conductive layer 23.

With this structure, the following operational effects can be obtained. (1) After depositing the silicon film (23) on the entire surface of the insulating film 21 in the above step, and before subjecting the silicon film in the step to patterning, the silicon film is subjected to high temperature annealing for the purpose of crystallization, The stress due to the volume contraction when the silicon film is cooled is dispersed in the entire silicon film, and is generated at the opening end of the connection hole 22 formed in the insulating film 21 on the main surface of the n + type semiconductor region 11. Since the concentration of the stress that occurs due to the volume contraction of the silicon film can be reduced, the pn junction between the p − -type semiconductor substrate 1 and the n + -type semiconductor region 11 from the opening end of the connection hole 22 of the insulating film 21 can be reduced. It is possible to prevent the occurrence of crystal defects that cross the portion. (2) The step of performing the high temperature annealing for crystallizing the silicon film in the step, which has been performed after the patterning of the silicon film in the step, is performed after the silicon film in the step is deposited. Since we only changed the silicon film before the patterning process, S
It is possible to prevent an increase in the number of steps in the RAM manufacturing process.

(13) Means (11) or Means (1)
In the SRAM described in 2), the n + type semiconductor region 11 is the drain region of the driving MISFET Qd of the flip-flop circuit of the memory cell MC of SRAM, and the conductive layer 23 is connected to the power supply voltage Vcc.

With this structure, the following operational effects can be obtained. (1) Since the leak current of the power supply supplied to the information storage node of the memory cell MC of the SRAM can be reduced,
The standby current consumption of the SRAM can be reduced.
(2) Since the leak current of the power supply supplied to the information storage node of the memory cell MC of the SRAM can be reduced, the information retention characteristic of the memory cell MC can be improved. (3) In the SRAM described in the means (11), n + is formed in the drain region of the driving MISFET Qd of the memory cell MC.
Since the type semiconductor region 21N is added, the impurity concentration of the region connected to the conductive layer 23 on the surface of the drain region can be increased by the amount corresponding to the n + type semiconductor region 21N.
The impurity concentration of the n-type impurity that reduces the resistance value introduced into the conductive layer 23 (polycrystalline silicon film) can be reduced (the impurity concentration required for ohmic connection is the n + -type semiconductor region 21).
It is possible to reduce the leakage of impurities from the conductive layer 23 to the drain region.

(14) MISF for driving memory cell MC
In a method of manufacturing an SRAM having ETQd (the same applies to the transfer MISFET Qt, the peripheral circuit n-channel MISFET Qn, and the p-channel MISFET Qp),
A step of forming a gate electrode 7 on the main surface of the p− type well region 2M with a gate insulating film 6 interposed therebetween, and a step of forming an insulating sidewall spacer 9 on a side wall of the gate electrode 7 in the gate length direction. A step of forming an insulating film 9T covering at least the surface of the sidewall spacer 9, the gate electrode 7, the sidewall spacer 9 and the insulating film 9 on the main surface of the p--type well region 2M.
An n-type impurity is ion-implanted into a region other than T, and the n + -type semiconductor region 11 used as each of the source region and the drain region is formed by the n-type impurity.
Each step of forming the driving MISFET Qd is provided.

With this structure, a region in which the maximum stress generated at the open end of the sidewall spacer 9 is concentrated due to the volume change of the gate electrode 7 (due to the difference in the coefficient of thermal expansion with the sidewall spacer 9). On the other hand, regions in which damage is generated due to the implantation of the n-type impurities forming the n + -type semiconductor regions 11 of the source region and the drain region, respectively, can be shifted by the amount corresponding to the film thickness of the insulating film 9T ( Since each of the maximum stress concentration region and the damage generation region can be dispersed), it is generated in the main surface of the p − type well region 2M and the n + type semiconductor region 11 in the open end region of the sidewall spacer 9. It is possible to prevent crystal defects or crystal defects that occur across the pn junction between the p- type well region 2M and the n + type semiconductor region 11.

(Embodiment 2) The present embodiment 2 is a second embodiment of the present invention in which the SRAM of the above-mentioned embodiment 1 is constructed by an n-type semiconductor substrate.

The basic structure of the semiconductor substrate having the SRAM according to the second embodiment of the present invention will be briefly described with reference to FIG. 40 (basic conceptual sectional view).

The SRAM of the second embodiment is composed of an n--type semiconductor substrate (Nsub) 1 as shown in FIG . The memory cell array MAY on the main surface of the n--type semiconductor substrate 1.
The region in which the P-type well region is arranged is a p-type well region (Pwell) 2. Of the peripheral circuits including the direct peripheral circuit and the indirect peripheral circuit, the complementary MISFET of the peripheral circuit to which the power supply voltage Vcc is supplied has substantially the same structure as the p--type well region 2 in which the memory cell array MAY is arranged. Is formed on the main surface of the p-type well region 2 and the main surface of the n-type well region (Nwell) 3.

On the other hand, the p-channel MISFET Qp of the complementary MISFET of the peripheral circuit to which the step-down power supply voltage Vdd stepped down by the power supply voltage conversion circuit VRC is supplied is p-.
N formed on the main surface of the well isolation region (Piso) 2i
-Type well region (Nwell) is formed on the main surface of 3M. The impurity concentration on the surface of the n--type well region 3M is equal to the impurity concentration on the surface of the n--type well region 3 arranged around the outer periphery of the p--type well isolation region 2i, as in the first embodiment. Alternatively, the impurity concentration is set higher than that. p-
In the outer periphery of the n-type well region 3M on the main surface of the type well isolation region 2i, in order to increase the impurity concentration of the surface,
A p-type well region 2 is formed.

The SRAM of the present embodiment has an undershoot resistance slightly lower than that of the first embodiment, but substantially the same effect as that of the first embodiment can be obtained.

Next, a specific manufacturing method of the SRAM,
In particular, p--type well isolation region 2i and n--type well region 3
Each manufacturing method of M will be briefly described with reference to FIG. 41 (cross-sectional view in a predetermined manufacturing process).

First, an n--type semiconductor substrate 1 is prepared, and a mask (indicated by reference numeral 53 in FIG. 41 and shown by a one-dot chain line) 53 in which a part of the main surface of the n--type semiconductor substrate 1 is opened is used. On the main surface of the n − -type semiconductor substrate 1,
Introduce each of the type impurities. As the p-type impurity, for example, B, which is faster than the diffusion rate of the n-type impurity, is used, and as the n-type impurity, As having a lower diffusion rate than the p-type impurity is used.
Is used. The p-type impurity and the n-type impurity are introduced by, for example, ion implantation using the same mask 53.

Next, the mask 53 is removed, and as shown in FIG. 41 , p-type impurities and n-type impurities are expanded and diffused, and the p-type well isolation regions 2i and n-type are formed by the p-type impurities. Each of the n-type well regions 3M is formed by impurities. p-
The type well isolation region 2i and the n − type well region 3M are formed as a double well structure as shown in FIG. 41 by utilizing the diffusion rate difference between the p type impurity and the n type impurity.

Thereafter, the n-type well region 3 and the p-type well region 2 are formed, and S is formed in the same manner as in the first embodiment.
The SRAM of the second embodiment is completed by performing the RAM manufacturing process.

As described above, the SRAM of this embodiment
According to the above, the following effects can be obtained.

(1) A p--type well isolation region 2i is formed in the first region of the main surface of the n--type semiconductor substrate 1, and an n--type well is formed in the second region of the main surface of the n--type semiconductor substrate 1. In the SRAM in which the region 3 is formed and the n − type well region 3M is formed on the main surface of the p − type well isolation region 2i, the first region is formed on the main surface of the n − type semiconductor substrate 1. A step of forming an opened first mask (53),
Using the first mask, introducing a p-type impurity into the main surface of the n-type semiconductor substrate 1 and introducing an n-type impurity having a slow diffusion rate with respect to the p-type impurity, the first mask Is removed to form a second mask (corresponding to 52M in FIG. 35 of the above-described first embodiment) on the main surface of the n − type semiconductor substrate 1 in which the second region and the first region are opened . Step, using the second mask, introducing an n-type impurity into the main surface of the n-type semiconductor substrate 1 and diffusing each of the n-type impurity and the p-type impurity,
Each of the steps of forming the p-type well isolation region 2i and the n-type well region 3M is provided.

With this structure, in addition to the function and effect of the means (5) of the first embodiment, the following function and effect can be obtained.
(1) Using the process of diffusing the n-type impurities introduced into the second region of the main surface of the n-type semiconductor substrate 1 to form the n-type well region 3, the p-type impurity introduced into the first region is used. Impurities are diffused to form p--type well isolation regions 2i, and
Since the n-type impurity introduced into the first region is diffused to form the n-type well region 3M, the p-type impurity and the n-type impurity are diffused to diffuse the p-type well isolation region 2i and the n-type well, respectively. SR corresponding to the process of forming each of the regions 3M
The number of steps in the AM manufacturing process can be reduced. (2) Since the diffusion speed of the n-type impurity is slower than that of the p-type impurity, the main surface of the p-type well isolation region 2i formed by diffusion of the p-type impurity is utilized by utilizing this difference in the diffusion speed. A p-type well region 3M formed by diffusing an n-type impurity can be formed at this point (a double well structure can be formed).

The inventions made by the present inventors are as follows.
Although the specific description has been given based on the above-mentioned embodiment, the present invention is not limited to the above-mentioned embodiment, and needless to say, various modifications can be made without departing from the scope of the invention.

For example, the present invention can be applied to the case where a high resistance element is used as the load element of the above-mentioned SRAM memory cell.

Further, the present invention may be applied to an SRAM mounted on a semiconductor integrated circuit device such as a microprocessor.

The present invention is not limited to SRAM,
D employing the double well structure (D ynamic) storage circuit system and a logic circuit system, such as a RAM is widely applicable to a semiconductor integrated circuit device is mounted.

[0363]

The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.

(1) In the semiconductor integrated circuit device adopting the double well structure, the operational reliability of the circuit arranged on the main surface of the well region in the well isolation region can be improved.
In addition, the operating speed of the circuit arranged on the main surface of the well region outside the well isolation region can be increased.

(2) In a semiconductor integrated circuit device having an SRAM in which memory cells are arranged in the well region in the well isolation region, the information holding characteristic of the SRAM can be improved.

(3) In a semiconductor integrated circuit device adopting a double well structure, the degree of integration can be improved.

(4) In the semiconductor integrated circuit device adopting the double well structure, the breakdown voltage between the well region in the well isolation region and the substrate can be improved.

(5) In the semiconductor integrated circuit device adopting the double well structure, the number of manufacturing process steps can be reduced.

(6) MISFET adopting SOI structure
In a semiconductor integrated circuit device having:
The breakdown voltage of the T gate insulating film can be improved.

(7) The effect (6) can be achieved, and the controllability of the film thickness of the gate insulating film of the MISFET can be improved.

(8) The effect (6) can be achieved, and the number of steps in the manufacturing process of the semiconductor integrated circuit device can be reduced.

(9) The object (6) can be achieved, and the surface of the semiconductor integrated circuit device can be flattened.

(10) MISFE adopting SOI structure
In a semiconductor integrated circuit device having an SRAM having a memory cell of T, standby current failure can be prevented.

(11) In the semiconductor integrated circuit device in which the electrode is connected to the source region or the drain region of the MISFET, it is possible to prevent the occurrence of crystal defects in the connection region.

(12) In the semiconductor integrated circuit device in which the electrodes are connected to the source region or the drain region of the MISFET, the number of manufacturing process steps can be reduced.

(13) MISFET for driving memory cell
In the semiconductor integrated circuit device having the SRAM in which the load element is connected to the drain region of, the power consumption can be reduced.

(14) MISFET for driving memory cell
In the semiconductor integrated circuit device having the SRAM in which the load element is connected to the drain region of the memory cell, the information retention characteristic of the memory cell can be improved.

(15) In the semiconductor integrated circuit device in which the sidewall spacer is formed on the sidewall of the gate electrode of the MISFET and the source region and the drain region are formed using the sidewall spacer as a mask.
It is possible to prevent the occurrence of crystal defects in the source region and the drain region of the ISFET.

[Brief description of drawings]

FIG. 1 is a chip layout diagram of an SRAM according to a first embodiment of the present invention.

FIG. 2A is an enlarged block diagram of a main part of the SRAM, and FIG. 2B is a block circuit diagram showing a power supply system.

FIG. 3 is an enlarged block diagram of a main part of the SRAM.

FIG. 4 is an enlarged block diagram of a main part of the SRAM.

FIG. 5 is a circuit diagram of a memory cell of the SRAM.

FIG. 6 is a sectional view of the memory cell.

FIG. 7 is a plan view of the memory cell.

FIG. 8 is a plan view of the memory cell shown in each step.

FIG. 9 is a plan view of a memory cell in each step.

FIG. 10 is a plan view showing a specific layer of the memory cell.

FIG. 11 is a plan view of the end portion of the array shown in each step.

FIG. 12 is a plan view of the end portion of the array shown in each step.

FIG. 13 is a plan view of the end portion of the array shown in each step.

FIG. 14 is a plan view of the end portion of the array shown in each step.

FIG. 15 is a cross-sectional view of the end portion of the array.

FIG. 16 is a sectional view of a peripheral circuit of the SRAM.

FIG. 17 is an enlarged cross-sectional view of a main part of the memory cell.

FIG. 18: Impurities of the SRAM substrate and well regions
Concentration distribution map.

FIG. 19 is a cross-sectional view of a memory cell in each process.

FIG. 20 is a cross-sectional view of a memory cell in each process.

FIG. 21 is a cross-sectional view of a memory cell in each process.

FIG. 22 is a cross-sectional view of a memory cell in each process.

FIG. 23 is a cross-sectional view of a memory cell in each process.

FIG. 24 is a cross-sectional view of a memory cell in each process.

FIG. 25 is a cross-sectional view of a memory cell in each process.

FIG. 26 is a cross-sectional view of the memory cell in each process.

FIG. 27 is a cross-sectional view of a memory cell in each process.

FIG. 28 is a cross-sectional view of a memory cell in each process.

FIG. 29 is a cross-sectional view of a memory cell in each process.

FIG. 30 is a cross-sectional view of a memory cell in each process.

FIG. 31 is a cross-sectional view of a memory cell in each process.

FIG. 32 is a cross-sectional view of the memory cell in each process.

FIG. 33 is a cross-sectional view of a memory cell in each process.

FIG. 34 is a sectional view of the end portion of the array shown in each step.

FIG. 35 is a sectional view of the end portion of the array shown in each step.

FIG. 36 is a sectional view of the end portion of the array shown in each step.

FIG. 37 is a sectional view of the end portion of the array shown in each step.

FIG. 38 is a cross-sectional view of the end portion of the array shown in each step.

FIG. 39 is a sectional view of the end portion of the array shown in each step.

FIG. 40 is a concept of an SRAM substrate according to a second embodiment of the present invention.
Sectional view.

FIG. 41 is a sectional view of a specific process of the substrate.

[Explanation of Codes] 1 ... Semiconductor substrate, 2, 2M, 3, 3M ... Well region, 2
i, 3i ... Well isolation region, 4 ... Element isolation insulating film, 5 ...
Channel stopper region, 6, 12, 24 ... Gate insulating film, 7 ... Gate electrode, 13 ... Gate electrode, word line or wiring 10, 11, 17, 18, 21N, 39, 40 ...
Semiconductor region, 23, 26, 29, 33 ... Conductive layer or wiring, 9, 16 ... Sidewall spacer, 22 ... Connection hole, 9T, 21, 24G, 27, 30 ... Interlayer insulating film, M
C ... Memory cell, Qt ... Transfer MISFET, Qd ... Driving MISFET, Qp ... Load MISFET, C ... Capacitance element, WL ... Word line, DL ... Data line, Gr ... Guard ring region.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Figure 5]

FIG. 17

FIG. 40

[Fig. 2]

FIG. 19

FIG. 41

[Figure 3]

[Figure 4]

[Figure 8]

[Figure 10]

FIG. 18

[Figure 6]

[Figure 7]

[Figure 9]

FIG. 20

FIG. 11

[Fig. 12]

FIG. 35

[Fig. 13]

FIG. 14

FIG. 15

FIG. 16

FIG. 21

FIG. 22

FIG. 23

FIG. 24

FIG. 25

FIG. 26

FIG. 27

FIG. 28

FIG. 29

FIG. 30

FIG. 31

FIG. 32

FIG. 33

FIG. 34

FIG. 36

FIG. 37

FIG. 38

FIG. 39

Front page continuation (72) Inventor Shuji Ikeda 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Musashi Factory, Hitachi, Ltd. (72) Inventor Rei Meguro 5-20 Sanmizuhoncho, Kodaira-shi, Tokyo No. 1 Incorporated company Hitachi Ltd. Musashi Factory (72) Inventor Soichiro Hashiba 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Musashi Factory (72) Inventor Seiichi Ariga Above Kodaira, Tokyo 5-20-1 Mizumotocho Hitsuru Cho El S. I Engineering Co., Ltd. (72) Inventor Yasuko Yoshida 5-20-1 Josuihoncho, Kodaira-shi, Tokyo Hitachi Ltd. Musashi Factory ( 72) Inventor Isamu Kuramoto 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside the Musashi Plant, Hitachi Ltd. (72) Takayuki Kanda 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Stock company Hitachi, Ltd. Musashi Plant (72) Inventor Hiroshi Matsuki 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Musashi Factory (72) Inventor Masato Takahashi 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Incorporated Hitachi Ltd. Musashi Factory (72) Inventor Keiichi Yoshizumi Kamimizumoto-cho, Kodaira-shi, Tokyo 5-20-1 Incorporated company Hitachi, Ltd. Musashi factory (72) Inventor Ryuichi Izawa 5-201-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Musashi factory (72) Inventor Yu Hoshino Tokyo 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi, Ltd. Musashi Factory (72) Inventor Eri Fujita 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitsuryu SLS Engineering Co., Ltd. Incorporated (72) Inventor, Ryo Saeki 5-20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Musashi Factory, Hitachi, Ltd. (72) Inventor, Kiyoshi Nagai 5-2-1, Kamimizuhonmachi, Kodaira, Tokyo Issue Company Hitachi Ltd. Musashi Factory (72) Inventor Norio Suzuki 5-20, Kamimizuhonmachi, Kodaira-shi, Tokyo No. 1 Co., Ltd. Hitachi, Musashi in the factory (72) inventor Kazushige Sato Hitachi City, Ibaraki Prefecture Kuji-cho, 4026 address, Inc. Date falling Works Hitachi within the Institute

Claims (12)

[Claims] 1. A first semiconductor region of a second conductivity type is formed in a first region of a main surface of a semiconductor substrate of a first conductivity type, and a first conductivity type is formed in a second region of the main surface of the semiconductor substrate. And a second semiconductor region having an impurity concentration higher than that of the semiconductor substrate is formed, and a third semiconductor region of the first conductivity type is formed on the main surface of the first semiconductor region. In a semiconductor integrated circuit device in which a first conductivity type channel MISFET is formed on each main surface of the third semiconductor region, the impurity concentration of the surface of the third semiconductor region is equal to the impurity concentration of the surface of the second semiconductor region. It is set equal or higher than that. 2. The semiconductor integrated circuit device according to claim 1, wherein a static random access memory is mounted, and the first conductive region is formed on the main surface of the third semiconductor region of the main surface of the first semiconductor region. The type channel MISFET constitutes a flip-flop circuit of the memory cell of the static random access memory, and the first conductivity type channel MISFET formed on the main surface of the second semiconductor region directly connects the memory cell of the static random access memory. Alternatively, it constitutes a peripheral circuit that is indirectly driven. 3. The third semiconductor region according to claim 1 or 2 is self-aligned with the first semiconductor region. 4. A first conductivity type semiconductor region is formed in a first area of a main surface of a first conductivity type semiconductor substrate, and is formed of a first conductivity type in a second area of the main surface of the semiconductor substrate. In the semiconductor integrated circuit device, a second semiconductor region having a higher impurity concentration than that of the semiconductor substrate is formed, and a third semiconductor region of the first conductivity type is formed on the main surface of the first semiconductor region. A fourth semiconductor region formed of the second conductivity type and having an impurity concentration higher than that of the first semiconductor region is formed in a region along the outer periphery of the third semiconductor region on the main surface of the first semiconductor region. Constitute. 5. A first conductivity type semiconductor region is formed in a first region of a main surface of a first conductivity type semiconductor substrate, and is formed of a first conductivity type in a second region of the main surface of the semiconductor substrate. And a second semiconductor region having an impurity concentration higher than that of the semiconductor substrate is formed, and a third semiconductor region of the first conductivity type is formed on the main surface of the first semiconductor region. The method includes the following steps (1) to (5). (1) A step of forming a first mask in which the first region is opened on the main surface of the semiconductor substrate, (2) Using the first mask, a second conductive type film is formed on the main surface of the semiconductor substrate. A step of introducing a first impurity and diffusing the first impurity to form the second conductive type first semiconductor region, (3) using the first mask, and forming a main surface of the first semiconductor region Introducing a second impurity of the first conductivity type, (4) removing the first mask and opening the second region on the main surface of the semiconductor substrate, or the second region and Forming a second mask having an opening in the first region, (5) using the second mask, introducing a third impurity of the first conductivity type into the main surface of the semiconductor substrate,
Diffusing each of the second impurities to form a second semiconductor region and a third semiconductor region.
Forming each of the semiconductor regions. 6. A first semiconductor region of a second conductivity type is formed in a first region of a main surface of a semiconductor substrate of a first conductivity type, and a first conductivity type is formed in a second region of the main surface of the semiconductor substrate. And a second semiconductor region having an impurity concentration higher than that of the semiconductor substrate is formed, and a third semiconductor region of the first conductivity type is formed on the main surface of the first semiconductor region. The method includes the following steps (1) to (4). (1) A step of forming a first mask in which the first region is opened on the main surface of the semiconductor substrate, (2) Using the first mask, a second conductive type film is formed on the main surface of the semiconductor substrate. Introducing a first impurity, and introducing a second impurity of the first conductivity type and having a slow diffusion rate with respect to the first impurity, (3) removing the first mask, Forming a second mask in which the second region is opened or a second mask in which the second region and the first region are opened on the main surface, (4) using the second mask, the semiconductor Introducing a third impurity of the first conductivity type into the main surface of the substrate,
Diffusing each of the first impurity and the second impurity to form each of the second semiconductor region, the first semiconductor region, and the third semiconductor region. 7. A semiconductor integrated circuit device having a MISFET in which a gate insulating film is provided on the surface of a channel forming region or a gate electrode and a gate electrode or a channel forming region crossing the channel forming region or the gate electrode is formed. In the forming method, the following steps (1) to (4)
It is equipped with. (1) A step of depositing a semiconductor layer or a gate electrode layer on the entire surface of the substrate, patterning the semiconductor layer or the gate electrode layer to form a channel formation region or a gate electrode, (2) the channel formation region or A part of the film thickness of the gate electrode is oxidized or nitrided from its surface to form an oxide film or a nitride film having a film thickness thicker than that of the native silicon oxide film, and the channel formation region or the gate electrode Relaxing the shape of the corners of the surface, (3) forming a gate insulating film on the surface of the channel forming region or the gate electrode, (4) on the upper and side surfaces of the surface of the channel forming region or the gate electrode Forming a gate electrode or a channel formation region that crosses the channel formation region or the gate electrode with the gate insulating film interposed. 8. The step (3) of forming a gate insulating film in the step (7) is performed after removing the oxide film or the nitride film on the surface of the channel formation region or the gate electrode in the step (2). This is a step of newly forming a gate insulating film on the surface of the channel formation region or the gate electrode. 9. The step (3) of forming a gate insulating film according to claim 7, wherein the gate insulating film is formed by an oxide film or a nitride film on the surface of the channel formation region or the gate electrode in step (2). Or a step of forming a gate insulating film with a composite film in which an insulating film is newly deposited on the surface of the oxide film or the nitride film. 10. A semiconductor integrated circuit device having a MISFET in which a gate insulating film is provided on the surface of a channel forming region or a gate electrode and a gate electrode or a channel forming region crossing the channel forming region or the gate electrode is formed. The forming method includes the following steps (1) to (4). (1) A step of depositing a semiconductor layer or a gate electrode layer on the entire surface of the substrate, patterning the semiconductor layer or the gate electrode layer to form a channel formation region or a gate electrode, (2) the channel formation region or A step of forming a sidewall spacer on the side surface of the gate electrode, (3) a part of the film thickness of the channel formation region or the gate electrode is oxidized or nitrided from the surface thereof, and is thicker than the film thickness of the natural silicon oxide film. Forming an oxide film or a nitride film having a film thickness and relaxing the shape of the corner portion of the surface of the channel forming region or the gate electrode, (4) forming a gate insulating film on the surface of the channel forming region or the gate electrode A step of forming (5) the channel formation region or the surface of the gate electrode above and side surfaces of the gate insulating film with the gate insulating film interposed. Forming a gate electrode or a channel formation region across the gate electrode. 11. A semiconductor integrated circuit device according to claim 7, wherein a static random access memory is mounted, and the MISFET is a flip-flop circuit of a memory cell of the static random access memory. Configure a load MISFET. 12. A method of manufacturing a semiconductor integrated circuit device having a MISFET, comprising the following steps (1) to (4). (1) A step of forming a gate electrode on the main surface of the semiconductor region of the first conductivity type with a gate insulating film interposed, (2) A sidewall spacer having an insulating property on a side wall of the gate electrode in the gate length direction. Forming step, (3) forming a mask covering at least the surface of the sidewall spacer, (4) other than the gate electrode, the sidewall spacer and the mask on the main surface of the first conductivity type semiconductor region A step of introducing a second conductivity type impurity into the region by ion implantation and forming a second conductivity type source region and a drain region with the second conductivity type impurity to form a MISFET.