JPH0529924A - 1/9 frequency divider circuit - Google Patents

Abstract

PURPOSE:To obtain an output signal having a duty ratio equal to that of an input signal by dividing the frequency of the input signal to 1/9. CONSTITUTION:D flip-flops 11, 12, 13 use respectively an input signal as their drive source and the D flip-flop 11, 12 form a shift register A. Similarly, D flip-flops 14, 15, 16 use an inverse of the input signal (a) and the D flip-flops 14, 15 form a shift register B. A noninverting output signal of the D flip-flop 12 is fed to a data input terminal of the D flip-flop 16, and a noninverting output signal of the D flip-flop 15 is fed to a data input terminal of the D flip-flop 13. Each inverting output signal of the D flip-flops 13, 16 is fed to an AND gate 18. An output signal of the AND gate 18 is fed to the shift registers A, B. The period of the output signal of the AND gate 18 is a multiple of 9/2 of the period of the input signal (a). A DFF 17 formed to divide an output signal frequency of the AND gate 18 into 1/2 is used to obtain an output signal (b) whose duty ratio is equal to that of the input signal (a) and subject to 1/9 frequency division.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a divide-by-9 circuit, and more particularly to a divide-by-9 circuit for dividing an input signal of a certain frequency having the same duty ratio and converting it into an output signal of a ninth frequency.

[0002]

2. Description of the Related Art Conventionally, this type of divide-by-9 circuit is constructed, for example, as shown in FIG. This 9 divider circuit
Four D-type flip-flops (hereinafter referred to as DFF)
30 to 33, AND gates 34 to 36, exclusive NOR gates 37 to 39, OR gates 40 and 41, and a NAND gate 42.

This circuit, except for the NAND gate 42 and AND gates 34 to 36, is a 4-bit synchronous down system in which the output signal of the DFF 30 is the most significant bit (MSB) and the output signal of the DFF 33 is the least significant bit (LSB). It has the same configuration as the counter. The NAND gate 42 is the DFF 30-.
Each inverted output signal (Q bar) of 33 is input, and "1" while the normal output signal (Q) of any DFF is at H level (high level), that is, when the counter value is not 0.
Is output. While the output signal of the NAND gate 42 is "1", the AND gate 34 outputs the output signal of the exclusive NOR gate 38, the AND gate 35 outputs the output signal of the exclusive NOR gate 39, and the AND gate 36 outputs the DFF.
By passing the inversion output signals of 33 respectively, DF
The F33 is made to operate as the lower bit of the synchronous down counter, the DFF32 is made to operate as its upper bit, and the DFF31 is made to operate as its higher bit.

On the contrary, if the output signal of the NAND gate 42 is "0", the three AND gates 34 to 36 are closed and output "0". In addition, the input signal a is DFF30-
It is adapted to be input to each clock input terminal 33.

Next, the operation of the conventional divide-by-9 circuit will be described with reference to FIGS.

First, it is assumed that the normal output signal of the DFF 30 is "1" and the normal output signals of the DFFs 31 to 33 are "0" in the initial state (counter value 8). At this time, the output signal of the NAND gate 42 becomes "1". Therefore, the AND gate 34 passes the output signal of the exclusive NOR gate 38, the AND gate 35 passes the output signal of the exclusive NOR gate 39, and the AND gate 36 passes the inverted output signal of the DFF 33. In this state, the entire circuit operates in the same way as the synchronous down counter, and the first input signal a
At the rising edge of, the normal output signals of the DFFs 31, 32, and 33 become "1", and the normal output signal of the DFF 30 becomes "0" (counter value 7). After that, the counter value is decremented by one each time the input signal a rises until the counter value becomes “0”.

At the rising edge of the eighth input signal, the DFF
All the normal output signals of 30 to 33 are "0" (counter value 0). As a result, the output signal of the NAND gate 42 becomes "0", so that the AND gates 34 to 36 close the gates and output "0" as the output signal. DFF3
Since the normal output signals of 1 to 33 are "0", the output signal of the OR gate 40 is "0", and the output signal of the exclusive NOR gate 37 is "1".

These data are taken into the DFFs 30 to 33 at the rising edge of the ninth input signal a, and the DFF 3
The normal output signal of 0 becomes "1", and the normal output signals of DFFs 31 to 33 become "0" (counter value 8). This is the same as the initial state. Therefore, thereafter, the above procedure is repeated every time the nine input signals a rise.

In the above operation, the non-inverted output signal of the DFF 30 always operates at the H level only for the counter value 8, the L level for the counter values 7 to 0, and the cycle for 9 input signal cycles. . Therefore, the non-inverted output signal (output signal b) of the DFF 30 becomes a signal obtained by dividing the input signal a by 9.

[0010]

As described above, the conventional divide-by-9 circuit can output the output signal b as the divide-by-9 signal of the input signal a, but the duty ratio of the input signal a is 1: 1. Although it is 1, there is a problem that the duty ratio of the output signal b becomes 1: 8, as is clear from (j) of FIG.

The present invention has been made in view of the above problems, and an object thereof is to divide an input signal into a frequency of 1/9 and output an output signal having a duty ratio equal to that of the input signal. It is to provide a frequency dividing circuit capable of dividing by 9.

[0012]

The circuit for dividing by 9 of the present invention is
An inverter that inverts and outputs an input signal, a first D flip-flop that receives the output signal of the inverter as a clock input, and a non-inverted output signal of the first D flip-flop as a data input, and the output of the inverter A second D flip-flop having a signal as a clock input, a third D flip-flop having the non-inverted output signal of the second D flip-flop as a data input and the input signal as a clock input, and the input signal Of the fourth D flip-flop, the fifth D flip-flop of which the normal output signal of the fourth D flip-flop is the data input, and the input signal is the clock input, and the fifth D flip-flop A sixth D flip using the normal output signal of the D flip flop as a data input and the output signal of the inverter as a clock input And the logical product signal of the inverted output signal of the third D flip-flop and the inverted output signal of the sixth D flip-flop to each data input of the first D flip-flop and the fourth D flip-flop. AND gates respectively output to the terminals, and an output signal of the AND gate as a clock input, and its own inverted output signal as a data input.
And a seventh D flip-flop for outputting a frequency-divided output signal.

In the divide-by-9 circuit of the present invention, a buffer having a delay time equal to that of the inverter is further provided, and an output signal of the buffer is supplied to the third D flip-flop.
A mode in which the clock signals are supplied to the clock input terminals of the fourth D flip-flop and the fifth flip-flop,
Further, instead of the AND gate, the inverted output signals of the third D flip-flop and the sixth D flip-flop are input, and the output signal is supplied to each clock input terminal of the seventh D flip-flop. A configuration using a NOR gate may be used.

With such a configuration, the divide-by-9 circuit of the present invention can divide the input signal into a frequency of 1/9 and make the duty ratio of this output signal equal to that of the input signal.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a divide-by-9 circuit according to an embodiment of the present invention.

The divide-by-9 circuit includes an inverter 20 that inverts and outputs an input signal a, and a buffer 1 that receives the input signal a and obtains an output signal with a delay time equal to that of the inverter 20.
9 and a first D flip-flop 14 (hereinafter referred to as DFF 14) that receives the output signal of the inverter 20 as a clock input, the non-inverted output signal of the DFF 14 as a data input, and the output signal of the inverter 20 as a clock input. And a third D flip-flop 13 (hereinafter referred to as the DFF 15) that receives the non-inverted output signal of the DFF 15 as a data input and the output signal of the buffer 19 as a clock input. , DFF13) and a fourth D flip-flop 11 (hereinafter referred to as DFF1) which receives the output signal of the buffer 19 as a clock input.
It is called 1. ) And a non-inverted output signal of the DFF 11 as a data input and an output signal of the buffer 19 as a clock input (hereinafter referred to as DFF 1).
2. ) And a normal output signal Q of the DFF 12 as a data input and an output signal of the inverter 20 as a clock input.
It is called F16. ) And an inverted output signal of the DFF 13 and an inverted output signal of the DFF 16 as inputs, and an AND gate 18 that outputs the AND signal to the data input terminals of the DFF 11 and the DFF 11, respectively, and an output signal of the AND gate 18 as a clock input. , A seventh D flip-flop 17 having its own inverted output signal as a data input
(Hereinafter, referred to as DFF17). Here, the DFF 11 and DFF 12 form a shift register A, and the DFF 14 and DFF 15 form a shift register B.

Next, the operation of the divide-by-9 circuit of this embodiment will be described with reference to FIG.
This will be described with reference to the timing charts of (a) and (b).

First, as an initial state, the DFFs 11 to 17 are
It is assumed that all the normal output signals of are all "0". Therefore, since the inverted output signals of the DFF 13 and DFF 16 are "1", the output signal of the AND gate 18 is "1".

The initial state is D at the first rise of the input signal a, that is, the rise of the output signal of the buffer 19.
The normal output signal is taken into the FF11 and becomes "1". Further, since the normal output signal of the DFF 11 and the normal output signal of the DFF 15 in the initial state are “0”, the DF
The normal output signal of F12 remains "0" and the inverted output signal of DFF13 remains "1". Therefore, the output signal of the AND gate 18 remains "1".

At the next fall of the input signal, that is, the rise of the output signal of the inverter 20, the output signal of the AND gate 18 is taken into the DFF 14, and its non-inverted output signal becomes "1". Since the normal output signal of the DFF 14 and the normal output signal of the DFF 12 are “0” at the previous time point, the normal output signal of the DFF 15 is “0”, and the inverted output signal of the DFF 16 is also “1”. Therefore, the output signal of the AND gate 18 remains "1".

At the rising edge of the second input signal, the output signal of the AND gate 18 and the normal output signal of the DFF 15 did not change, so the normal output signal of the DFF 11 and the inverted output signal of the DFF 13 did not change, but the DFF 12 did not change.
Since the normal output signal of the DFF 11 has been previously set to "1", the normal output signal of "1" transits to "1". The output signal of the AND gate 18 remains "1" because there is no change in the inverted output signal of the DFF 13.

Since the output signal of the AND gate 18 does not change at the fall of the second input signal, the DFF
The normal output signal of the DFF 15 does not change, but the normal output signal of the DFF 15 transits to "1" because the normal output signal of the previous DFF 14 is "1". Further, since the non-inverted output signal of the DFF12 also changes to "1", the DFF16
The inverted output signal of is 0. Therefore AND gate 1
The output signal of 8 transits to "0".

At the rising edge of the third input signal, the output signal of the AND gate 18 becomes "0", so DFF1
The normal output signal of 1 also becomes "0". The normal output signal of the DFF 12 is held at "1" because the normal output signal of the DFF 11 at the previous time point has not changed. The inverted output signal of the DFF 13 transitions to "0" in response to the normal output signal of the DFF 15 becoming "1". Therefore, the output signal of the AND gate 18 also remains "0".

Since the output signal of the AND gate 18 is "0" at the falling edge of the third input signal, the non-inverted output signal of the DFF 14 transits to "0". DFF14 at the previous time
Since there is no change in the normal output signal of DFF12 and the normal output signal of DFF12, the normal output signal of DFF15 and DFF1.
The inverted output signal of 6 does not change either. Therefore AND gate 1
The output signal of 8 does not change either.

At the rising edge of the fourth input signal, since the non-inverted output signal of the DFF 11 is "0", D
The normal output signal of the FF12 also transits to "0". DFF1
The normal output signal of 1 and the inverted output signal of the DFF 13 are
Since neither the output signal of the AND gate 18 nor the normal output signal of the DFF 15 has changed, there is no change. Therefore, there is no change in the output signal of the AND gate 18.

Since the output signal of the AND gate 18 does not change at the fourth fall of the input signal, the normal output signal of the DFF 14 remains "0". But DFF15
Since the normal output signal of the DFF 14 is "0" before, the normal output signal of "0" becomes "0". Also DFF12
In response to the normal output signal of DFF becoming "0", DFF
The inverted output signal of 16 also changes to "1". The inverted output signal of the DFF 16 becomes "1", but the output signal of the AND gate 18 remains "0" because the inverted output signal of the DFF 13 is still "0".

At the rising edge of the fifth input signal, the output signal of the AND gate 18 and the normal output signal of the DFF 11 remain "0", so that the normal output signal of the DFF 11 and the normal output signal of the DFF 12 are also "0". It remains.
The inverted output signal of the DFF 13 transits to "1" because the non-inverted output signal of the DFF 15 becomes "0". In response to this, the output signal of the AND gate 18 transits to "1". This is also applied to the clock input terminal of the DFF 17, and as a result, the normal output signal transits to "1".

At the falling edge of the fifth input signal, the output signal of the AND gate 18 is "1", so D
The normal output signal of the FF14 also becomes "1". The normal output signal of the DFF 15 and the inverted output signal of the DFF 16 are
Since there is no change in the normal output signal of the FF 14 and the normal output signal of the DFF 12, no state transition occurs. Therefore, there is no change in the output signal of the AND gate 18.

At the rising edge of the sixth input signal, since the output signal of the AND gate 18 is "1", the non-inverted output signal of the DFF 11 transits to "1". However, with respect to the normal output signal of the DFF 12 and the inverted output signal of the DFF 13, since the values of the normal output signal of the DFF 11 and the normal output signal of the DFF 15 at the previous time have not changed, the values of “0” and “1” are respectively set. There is. Therefore AND gate 18
The output signal of is also "1".

At the sixth fall of the input signal, the output signal of the AND gate 18 and the normal output signal of the DFF 12 did not change, so the normal output signal of the DFF 14 and the inverted output signal of the DFF 16 did not change. DFF15
Since the normal output signal of the DFF 14 is "1" before, the normal output signal of "1" transits to "1". The output signal of the AND gate 18 remains "1" because there is no change in the inverted output signal of the DFF 16.

At the rising edge of the seventh input signal, the output signal of the AND gate 18 is still "1".
Although the normal output signal of F11 does not change, the normal output signal of DFF12 transits to "1" because the normal output signal of DFF11 was previously "1". Also, DFF15
Since the non-inverted output signal of is also changed to "1", the DFF13
The inverted output signal of is 0. Therefore, the output signal of the AND gate 18 transits to "0".

At the fall of the seventh input signal, the output signal of the AND gate 18 becomes "0", so that the DFF
The normal output signal of 14 also becomes "0". The normal output signal of the DFF 15 is held at "1" because the normal output signal of the DFF 14 at the previous time point has not changed. The inverted output signal of the DFF 16 transits to "0" in response to the normal output signal of the DFF 12 becoming "1". Therefore, the output signal of the AND gate 18 also remains "0".

At the rising edge of the eighth input signal, since the output signal of the AND gate 18 is "0", the normal output signal of the DFF 11 transits to "0". DFF1 at the previous time
Since the normal output signal of 1 and the normal output signal of DFF 15 do not change, the normal output signal of DFF 12 and the DFF 15 do not change.
The inverted output signal of 13 does not change either. Therefore, the output signal of the AND gate 18 also does not change.

Since the non-inverted output signal of the DFF 14 is "0" before the eighth fall of the input signal,
The normal output signal of the DFF 15 also transits to "0". DFF
The normal output signal of 14 and the inverted output signal of DFF 16 do not change because neither the output signal of AND gate 18 nor the normal output signal of DFF 12 has changed. Therefore,
There is no change in the output signal of the AND gate 18.

At the rising edge of the ninth input signal, the output signal of the AND gate 18 does not change, so that the normal output signal of the DFF 11 remains "0", but the normal output signal of the DFF 12 outputs the normal output of the DFF 11 before. Since the signal is "0", it becomes "0". Further, in response to the fact that the normal output signal of the DFF 15 also becomes "0", the inverted output signal of the DFF 13 transits to "1". The inverted output signal of the DFF 13 becomes "1", but the inverted output signal of the DFF 16 is still "0", so the output signal of the AND gate 18 remains "0".

At the falling edge of the ninth input signal, the output signal of the AND gate 18 and the normal output signal of the DFF 14 remain "0", so the normal output signal of the DFF 14 and the normal output signal of the DFF 15 also become "0". “It remains.
The inverted output signal of the DFF 16 transits to "1" because the non-inverted output signal of the DFF 12 becomes "0". In response to this, the output signal of the AND gate 18 transits to "1". This is also supplied to the clock input terminal of the DFF 17, and as a result, the normal output signal transits to "0".

By the fall of the ninth input signal, all the normal output signals of the DFFs 11 to 17 become "0", which is the same as the initial state. After that, 9 pairs of input signals a
The above operation is repeated at every rising and falling of the input signal a, and the output signal of the AND gate 18 rises at every nine transitions of the input signal a. Therefore, DFF17
From the non-inverted output terminal (Q), a frequency-divided output signal b having a duty ratio of 1: 1 is output.

In the above embodiment, the buffer 19
Is provided to obtain the same delay time as that of the inverter 20 and reduce the influence of the skew between the inverted output signal of the DFF 13 due to the rising of the input signal a and the skew of the inverted output signal of the DFF 16 due to the falling of the input signal a. If the frequency is low or the delay time due to the inverter 20 is sufficiently small, it is not necessary to provide it.

Further, the AND gate 18 may be replaced with another logic element having an equivalent logical configuration, for example, a NOR gate having the inverted output signal of the DFF 13 and the inverted output signal of the DFF 16 as inputs.

[0041]

As described above, according to the ninth frequency division circuit of the first to third aspects, the inverter for inverting the input signal and outputting the inverted signal, and the first D for inputting the output signal of the inverter as the clock input. Flip-flop and this first D
A second D having the normal output signal of the flip-flop as a data input and the output signal of the inverter as a clock input.
A flip-flop, a third D flip-flop having the non-inverted output signal of the second D flip-flop as a data input and having the input signal as a clock input, and a fourth D flip-flop having the input signal as a clock input. And
A fifth D having the normal output signal of the fourth D flip-flop as a data input and the input signal as a clock input
A flip-flop and a sixth D flip-flop, which receives the non-inverted output signal of the fifth D flip-flop as a data input and uses the output signal of the inverter as a clock input, and an inverted output signal of the third D flip-flop. And a logical product signal of the inverted output signals of the sixth D flip-flop and the fourth D flip-flop and the fourth D flip-flop.
AND gate which outputs to each data input terminal of the D flip-flop and the output signal of this AND gate is used as a clock input, and its own inverted output signal is used as a data input to output an output signal divided by 9 with respect to the input signal. Since the seventh D flip-flop is provided, it is possible to divide the input signal into a frequency of 1/9 and generate an output signal having a duty ratio equal to that of the input signal. There is.

[0042]

[Brief description of drawings]

FIG. 1 is a configuration diagram of a divide-by-9 circuit according to an embodiment of the present invention.

2 is a time chart showing the operation of the divide-by-9 circuit of FIG. 1. FIG.

FIG. 3 is a configuration diagram of a conventional divide-by-9 circuit.

FIG. 4 is a time chart showing the operation of a conventional circuit.

[Explanation of symbols]

11-17 D-type flip-flop 18 And Gate 19 buffers 20 inverter

Claims (3)

[Claims] 1. An inverter that inverts and outputs an input signal, a first D flip-flop that receives the output signal of this inverter as a clock input, and a normal output signal of this first D flip-flop as a data input. A second D flip-flop having the output signal of the inverter as a clock input, and a third D flip-flop having the non-inverted output signal of the second D flip-flop as a data input and the input signal as a clock input
A flip-flop; a fourth D flip-flop which receives the input signal as a clock input; and a fifth D flip-flop which outputs the normal output signal of the fourth D flip-flop as a data input and the input signal as a clock input.
A flip-flop, a sixth D flip-flop which receives the non-inverted output signal of the fifth D flip-flop as a data input, and an output signal of the inverter as a clock input, and an inverted output signal of the third D flip-flop. And an AND signal of the inverted output signals of the sixth D flip-flop and the first D flip-flop and the fourth D flip-flop.
An AND gate for outputting to each data input terminal of the flip-flop, and an output signal of the AND gate as a clock input, and an inverted output signal of its own as a data input for outputting an output signal of frequency division 9 with respect to the input signal And a D flip-flop of 1. 2. A buffer having a delay time equal to that of the inverter is provided, and an output signal of the buffer is provided to each clock input terminal of the third D flip-flop, the fourth D flip-flop and the fifth D flip-flop. 2. The divide-by-9 circuit according to claim 1, further comprising: 3. The third gate instead of the AND gate
2. A NOR gate for receiving the inverted output signals of the D flip-flop and the sixth D flip-flop respectively and supplying the output signal to the clock input terminal of the seventh D flip-flop is used. Alternatively, the 9-divider circuit described in 2.