JPH05299011A - Field emission component and its manufacture - Google Patents

Abstract

PURPOSE:To efficiently manufacture a field emission (FEC) which has a resistance layer independent for every emitter. CONSTITUTION:(a) A cathode conductor 2, an insulation layer 3 and a gate 4 are laminated on an insulating substrate 1 to form a cavity 5 in the insulation layer 3 and the gate 4. (b) Si is evaporated to the insulating substrate 1 from a vertical direction to from a Si layer on the gate 4 and an independent resistance layer 7 on the cathode conductor 2 in the cavity 5. (c) The Si layer 6 is only oxidized with anode oxidation to form a peeled layer 8. Mo is evaporated to the insulating substrate 1 from a vertical direction to form an emitter 9 on the resistance layer 7. (d) The peeled layer 8 and an unnecessary layer 10 on the peeled layer 8 are removed to obtain a field emission component(FEC) which has the resistance layer 7 independent for every emitter 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field emission device (Field
Emission Cathodes, hereinafter referred to as FEC. ) And the manufacturing method thereof. The FEC of the present invention is useful as an electron source for various electron beam application devices such as fluorescent display devices, CRTs, electron microscopes, and electron beam exposure devices.

[0002]

2. Description of the Related Art FIG. 2 shows an FEC disclosed in Japanese Patent Laid-Open No. 1-154426. A cathode conductor 101 is formed on the substrate 100, and a resistance layer 102 is formed thereon. An insulating layer 103 and a gate 104 are sequentially stacked on the resistance layer 102. Insulating layer 103 and gate 1
A hole is formed in 04, and a cone-shaped emitter 105 is formed on the resistance layer 102 in the hole.

In the above structure, the resistance layer 102 is commonly provided for the many emitters 105 formed and is continuously formed on the cathode conductor 101. The resistance layer 102 is made of In ₂ O ₃ , Fe ₂
O ₃ , ZnO, Ni—Cr alloy, or Si doped with impurities and having a resistivity of 1 × 10 ² Ω · cm to 1 × 1
It is 0 ⁶ Ω · cm.

FIG. 3 shows the manufacturing process of the FEC. First, the cathode conductor 101, the resistance layer 102, the insulating layer 103, and the gate 104 are sequentially stacked on the substrate 100. Next, as shown in FIG. 4A, holes 106 are formed in the gate 104 and the insulating layer 103 by etching.

As shown in FIG. 3B, the gate 10 is moved from a position diagonally above the substrate 100 at a predetermined angle θ.
4. Ni or Al is obliquely vapor-deposited on the surface of No. 4, and the peeling layer 107
To form. Ni or Al is vapor-deposited only on the surface of the gate 104 and does not enter the hole 106 of the insulating layer 103.

Then, as shown in FIG. 3C, an emitter material is vapor-deposited from above to form a cone-shaped emitter 105 in the hole 106, and thereafter, a peeling layer 107 is formed as shown in FIG. 3D. At the same time, the emitter material on the peeling layer 107 is removed.

[0007]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
According to the above, since the resistance layer 102 is common, the respective emitters 105 are not electrically independent, and when a certain emitter comes into contact with the gate and breaks, damage is also applied to the resistance layer 102,
Sometimes all emitters would stop working.

According to the conventional manufacturing method of the FEC described above, N is formed in order to form the release layer 107 on the gate 104.
Diagonal vapor deposition of i or Al was performed. According to this method, when the substrate is large, the distance between the vapor deposition source and each part of the substrate is different, so that the thickness of the peeling layer formed varies depending on the position on the substrate. Such a variation in the thickness of the peeling layer leads to a variation in the opening diameter, which causes a variation in the height of the emitter formed in the hole. Further, there is a problem that such a manufacturing method by the oblique vapor deposition method is very complicated and has no mass productivity.

It is an object of the present invention to provide an FEC having an independent resistance layer for each emitter, and a method capable of efficiently manufacturing such an FEC without using an oblique evaporation method.

[0010]

A field emission device according to the present invention comprises a cathode conductor formed on an insulating substrate, an insulating layer formed on the cathode conductor and having a large number of holes.
A resistance layer provided independently of each other on the cathode conductor in each hole, a cone-shaped emitter formed on each resistance layer, and a gate formed on the insulating layer. There is.

Further, according to the present invention, in the above field emission device, P or B is doped to 1 × 10 ² to 1 × 10 ^7.
The resistance layer may be formed of Si having a resistivity of Ω · cm.

The method of manufacturing a field emission device according to the present invention is
A step of forming a cathode conductor having a predetermined pattern on an insulating substrate, a step of sequentially laminating an insulating layer and a metal thin film on the cathode conductor, and a step of etching the metal thin film and the insulating layer to form a gate and a large number of holes. A step of forming a Si layer on the gate and the cathode conductor in each of the holes by positive vapor deposition, and a step of oxidizing the Si thin film of the gate by an anodic oxidation method to form a SiO ₂ peeling layer. a step of forming an emitter cone shape on each Si thin film of the insulating substrate within the respective holes by a positive depositing an emitter material from above, the emitter material on the SiO ₂ release layer S
It has a step of removing it together with the iO ₂ peeling layer.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 1A, N is formed on the insulating substrate 1 such as glass.
A metal thin film of b, Mo, Al or the like is solidly formed and processed into a desired pattern by a photolithography method to obtain a cathode conductor 2.

An insulating layer 3 made of SiO ₂ is formed on the insulating substrate 1 so as to cover the cathode conductor 2. The insulating layer 3 is formed by a sputtering method or a CVD method and has a film thickness of about 1.0 μm.

On the surface of the insulating layer 3, a gate material, Nb or Mo, is deposited by sputtering to a thickness of about 0.4 μm to form a gate layer.

Reactive ion etching (RIE)
By the method, a large number of holes 4a having a diameter of about 1.0 μm are formed in the gate layer to form the gate 4 as shown in FIG.

The insulating layer 3 is etched from the hole 4a of the gate 4 until the cathode conductor 2 is exposed, and a hole 5 is formed. For etching, use buffered hydrofluoric acid (B
Wet etching using HF) or CH
Dry etching performed by the RIE method using a gas such as F ₃ may be used. After this step, if the resist is peeled off, as shown in FIG.
The structure shown in (a) is obtained.

As shown in FIG. 1 (b), Si doped with P or B is positively vapor-deposited on the insulating substrate 1 from above by an electro-beam vapor deposition (EB vapor deposition) method. Here, the normal vapor deposition means that the vapor deposition source is arranged right above the insulating substrate 1 and the gate 4
It means that Si is vapor-deposited perpendicularly to. According to this normal vapor deposition method, unlike the conventional oblique vapor deposition, even if the insulating substrate 1 is relatively large, the distance between the vapor deposition source and each part of the insulating substrate 1 does not greatly vary.

As shown in FIG. 1B, a Si layer 6 and a resistance layer 7 made of Si are formed on the upper surface of the gate 4 and the cathode electrode 2 in the hole 5 by the normal vapor deposition of Si. .. The thickness has a resistivity of 1 × 10 ² Ω · cm to 1 × 10
Set the dimensions to be ⁷ Ω · cm.

Using the anodic oxidation method, only the Si layer on the gate 4 is oxidized to SiO ₂ and the peeling layer 8 is formed. That is, a solution obtained by adding ethylene glycol to a 0.04N KNO ₃ solution was used, and the gate 4 of the insulating substrate 1 was used as an anode, and a Pt or SUS passivation electrode was used as a cathode.
Anodization is performed at a current density of ˜25 mA / cm ² .

As shown in FIG. 1C, the Si of the gate 4 is
Layer 6 is oxidized to SiO ₂ to form release layer 8. In this case, only the Si layer 6 on the gate 4 is energized, and the resistance layer 7 on the cathode electrode 2 is not energized. Therefore, the Si resistance layer 7 does not change.

Next, as shown in FIG. 1 (c), Mo, which is an emitter material, is vapor-deposited directly above the holes 5. Hole 5
A cone-shaped emitter 9 is formed on the internal resistance layer 7, and a vapor deposition layer 10 of Mo is formed on the peeling layer 8.

Next, the peeling layer 8 is removed using buffered hydrofluoric acid (BHF), and the unnecessary Mo vapor deposition layer 10 is removed. At this time, BHF also enters the holes 5 and etches the insulating layer 3 again, so that the holes 5 are further widened and the structure shown in FIG.
A Spindt-type FEC having a cross-sectional shape as shown in (d) is obtained.

[0024]

According to the field emission device of the present invention, since each emitter has an independent resistance layer, even if an overcurrent flows due to a short circuit, only the shorted part is destroyed, and The damage does not spread to the emitter of the. Therefore, a field emission device having a long life can be obtained.

Further, according to the method for manufacturing a field emission device of the present invention, since the peeling layer can be formed by normal vapor deposition, the film thickness can be made uniform and the hole diameter of the gate opening can be made uniform. become. Therefore, there is an effect that many emitters can be formed at a uniform height.

Since the normal vapor deposition method is applied as described above, a uniform field emission device can be formed even if the substrate area is large.

Further, since the resistance layer and the peeling layer can be formed at the same time, the manufacturing process is simplified.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of an example.

FIG. 2 is a sectional view of a conventional FEC.

FIG. 3 is a manufacturing process diagram of a conventional FEC.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Cathode conductor 3 Insulating layer 4 Gate 5 Voids 7 Resistive layer 8 Release layer 9 Emitter

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Masateru Taniguchi 629 Oshiba, Mobara-shi, Chiba Futaba Electronics Co., Ltd. (72) Inventor Norio Nishimura 629 Oshiba, Mobara-shi, Chiba Futaba Electronics Co., Ltd. (72) Inventor Hisataka Ochiai 629 Oshiba, Mobara-shi, Chiba Futaba Electronics Co., Ltd. (72) Inventor Manabu Yamaguchi 629 Oshiba, Mobara-shi, Chiba Futaba Electronics Co., Ltd.

Claims (3)

[Claims] 1. A cathode conductor formed on an insulating substrate, an insulating layer formed on the cathode conductor and having a large number of holes, and independently provided on the cathode conductor in each of the holes. A field emission device having a resistive layer formed thereon, a cone-shaped emitter formed on each resistive layer, and a gate formed on the insulating layer. 2. The resistance layer is 1 × 10 ² to 1 × 10 ^7.
The field emission device according to claim 1, which is P or B-doped Si having a resistivity of Ω · cm. 3. A step of forming a cathode conductor having a predetermined pattern on an insulating substrate, a step of sequentially stacking an insulating layer and a metal thin film on the cathode conductor, and etching the metal thin film and the insulating layer to form gates and a large number of gates. forming a vacancy, a step of forming a Si layer by the positive deposition on the cathode conductor of said each of the holes and the gate, SiO ₂ and the Si thin film on the gate oxidized by anodic oxidation Forming a peeling layer, forming a cone-shaped emitter on each Si thin film in each of the holes by directly vapor-depositing the emitter material on the insulating substrate, and forming a cone-shaped emitter on the SiO ₂ peeling layer. A method for manufacturing a field emission device, comprising a step of removing an emitter material together with a SiO ₂ peeling layer.