JPH0528780A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To provide a nonvolatile semiconductor memory enabling of smooth high-speed reading by negligibly shortening the dead time occurring at a switching time of the word line. CONSTITUTION:Column reading for the data of a memory cell selected with one word line WL stored in a sense amplifier circuit 3 having a latching function provided with each bit line BLj is carried out. During this time, between the bit line BLj and the sense amplifier circuit 3 is cut-off by a bit line transfer gate Qj2 and a timing control is carried out such that reading of the bit line BLj of the data of the memory cell selected by the next word line WL is simultaneously carried out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device capable of high-speed reading.

[0002]

2. Description of the Related Art A NAND cell type EEPROM is known as a non-volatile semiconductor memory device (EEPROM) which is electrically rewritable and can be highly integrated.
One memory cell has a FETMOS structure in which a floating gate and a control gate are laminated on a substrate via an insulating film, and a plurality of memory cells that are adjacent to each other are connected in series so that their sources and drains are shared. To form a NAND cell.

The drain on one end side of the NAND cell is connected to the bit line via the select gate, and the source on the other end side is also connected to the common source line via the select gate. A plurality of such memory cells are arranged in a matrix to form an EEPROM.
M is constructed. The memory cell array is usually formed in a p-type well formed in an n-type semiconductor substrate.

The operation of this NAND cell type EEPROM is as follows. Data writing is performed in order from the memory cell farther from the bit line. Explaining the case of the n-channel, a boosted write potential Vpp (= about 20 V) is applied to the control gate of the selected memory cell, and the control gate and the select gate of the non-selected memory cell on the bit line side are applied. Is applied with an intermediate potential VH (= about 10V), and 0V (for example, "1") is applied to the bit line according to the data.
Alternatively, an intermediate potential (for example, "0") is applied. At this time, the potential of the bit line is transferred to the non-selected memory cell and transmitted to the drain of the selected memory cell. When the data is "1", a high electric field is applied between the floating gate and the drain of the selected memory cell, electrons are tunnel-injected from the drain to the floating gate, and the threshold value moves in the positive direction. When the data is "0", there is no threshold change.

Data erasing is simultaneously performed on all the memory cells in the NAND cell. That is, all control gates and select gates are set to 0V, and the boosted erase potential VppE (= 20V) is applied to the p-type well and the n-type substrate. As a result, in all the memory cells, electrons in the floating gate are emitted to the well, and the threshold value moves in the negative direction.

In data reading, whether the control gate of the selected memory cell is set to 0V and the control gates and selection gates of the other memory cells are set to the power supply potential Vcc (= 5V), and whether or not a current flows in the selected memory cell. Is detected.

Such a conventional NAND cell type EEPRO
In M, since multiple memory cells are connected in cascade,
There was a problem that the cell current during reading was small, and random reading took time.

For example, when a NAND cell is constructed by 8-bit cascade connection, the cell current at the time of reading becomes 1 μA at worst. The worst condition at the time of reading is a memory cell in which 7 bits out of 8 bits of the NAND cell are logical "0" (threshold voltage is 0.5 V or more and 3.5 V or less), and 1 bit to be read is a logical "1". Memory cell (threshold voltage is -0.5V or less)
Is the case. At the 4M bit level, the capacitance per bit line is about 0.5pF, so the time required to discharge the bit line from the precharge potential of 5V to 0V is 5V × 0.5 [pF] / 1. [ΜA] = 2.5 [μsec]. Further, if a polycrystalline silicon film is used for the word lines, it takes a long time to select the word lines.

For example, if the sheet resistance of the polycrystalline silicon film is 50 Ω / □, the width of the word line is 0.7 μm and the length is 3.5 mm, so the resistance of one word line is 250.
It becomes kΩ. Since the capacity of one word line is 4 pF, the time constant of the word line is a lumped constant of 1 μsec. Therefore, in the conventional NAND cell type EEPROM, it took at least 3.5 μsec for random reading.

Even if the word line selection time is shortened from the current 1 μsec to 100 nsec by using silicide for the word line, the read time due to a small cell current does not change, and it is estimated that at least 2.5 μsec is required.

On the other hand, a conventional NAND cell type EEPROM
Then, each bit line has a sense amplifier circuit that also serves as a latch circuit. When data is taken into this sense amplifier / latch circuit, continuous column reading is possible by switching the column address. The time required to read this column is as short as 100 nsec. Therefore, in the conventional NAND cell type EEPROM, there is a problem that random reading takes 35 times as long as column reading.

Further, recently, the use of the EEPROM has been expanding, for example, as a replacement for a floppy disk or as a storage medium for a film of a solid-state electronic camera. In such an application, in the reading, random reading in 1-bit units is not performed, and 1 block,
Continuous reading is performed in units of one sector.

For example, when 4 kbit memory cells are selected per word line and one block is composed of 8 word lines, that is, 32 kbit memory cells,
In the conventional NAND type EEPROM, there is a dead time of 3.5 .mu.sec each time the word line is switched, so that there is a problem that smooth continuous reading is hindered.

The same applies to the NAND cell type EEPRO.
Not only for M, but also for higher integration, increase in word line resistance and increase in bit line capacitance and a decrease in cell current causes a problem in other EEPROMs and the like.

[0015]

As described above, the conventional E
In the EPROM, there is a problem that useless time is involved in switching the word lines and the high speed of random reading and block reading is particularly impaired.

The present invention has been made in view of the above circumstances, and provides a non-volatile semiconductor memory device capable of performing smooth high-speed reading by reducing the dead time generated when switching the word lines to a negligible amount. The purpose is to do.

[0017]

In the nonvolatile semiconductor memory device according to the present invention, data of a memory cell selected by a certain word line stored in a sense amplifier circuit having a latch function provided in each bit line. Timing control for blocking the bit line and the sense amplifier circuit by the bit line transfer gate during the column read and simultaneously reading the data of the memory cell selected by the next word line to the bit line. Means are provided.

[0018]

According to the present invention, the time required for word line selection and reading of memory cell data to the bit line, which occurs at the time of switching the word line, is taken in within the column reading time, so that there is a dead time externally. As a result, smooth high-speed reading can be achieved.

For example, when 4 kbit memory cells are connected to each word line and one block is composed of 8 word lines, that is, 32 kbit memory cells, the word lines are switched in the conventional NAND type EEPROM. Since a dead time of 3.5 μsec is entered each time, the read time for one block is (3.5 [μsec] +100 [nsec] × 4095) × 8 = 3304 [μsec].

On the other hand, in the present invention, the dead time generated at the time of switching the word line is not necessary, and instead of this, for example, a dummy cycle having a column read time of 100 [nsec] may be inserted to read one block. The time is 3.5 [μsec] +100 [nsec] × 4095 + (100 [nsec] +100 [nsec] × 4095) × 7 = 3280.9 [μsec]. Therefore, according to the present invention, high-speed continuous reading is possible.

[0021]

Embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 1 shows a block configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention, FIG. 2 shows its memory cell array configuration, and FIG. 3 shows the configuration of a sense amplifier circuit section.

In FIG. 1, 1 is a memory cell array in which nonvolatile memory cells are arranged, 2 is a row decoder for selecting a word line, 3 is a sense amplifier circuit having a data latch function, 4 is a column decoder for selecting a bit line, 5,
Reference numeral 6 denotes a row address buffer and a column address buffer for respectively fetching external addresses, 7 denotes an I / O sense amplifier circuit connected to the sense amplifier circuit 3 via the data input / output lines IO and / IO, and 8 denotes a data output buffer. ,
9 is a data input buffer, 10 is chip enable /
It is a logic control circuit that generates a timing control clock for an internal circuit by external control signals such as CE, output enable / OE, and write enable / WE.

As shown in FIG. 2, the memory cell array 1 includes a plurality of word lines WLi (i = 0 ,, 1, ..., M).
And a plurality of bit lines BLj (j = 0,
1, ..., N) are arranged, and the non-volatile memory cells MCij selected by the word line WLi and transmitting / receiving data to / from the bit line BLj are arranged at the respective intersections. There is. The memory cell MCij is, for example, F
It is an EEPROM cell having an ETMOS structure. Each bit line BLj is provided with a PMOS transistor Qj1 for precharging it to the read potential VR at the time of reading.

As shown in FIG. 3, each bit line BLj is connected to a bit line sense amplifier SAj via a bit line transfer gate Qj2 composed of an NMOS transistor. The sense amplifier SAj is connected to the data input / output lines IO, / IO via column selection gates Qj3, Qj4 which are NMOS transistors controlled by the column selection line CSLj selected by the column decoder 4. 4 to 6 are timing charts showing the read operation of the nonvolatile semiconductor memory device of this embodiment.

When the chip enable / CE changes from "H" level to "L" level and the row address and column address of the chip external input are taken into the chip, the read operation starts (time t0).

First, the control signal PREB for precharging the bit line BLj changes from Vcc to Vss (time t1),
This turns on the PMOS transistor Qj1,
Bit line BLj is precharged to VR. After precharging, the control signal PREB is changed from Vss to Vcc again, the PMOS transistor Qj1 is turned off, and the bit line BLj becomes floating at the VR potential.

Next, the word line WL0 selected by the row address changes from Vss to the "H" level potential VH (time t2), and the data of the memory cell memory cell MC0j selected by this word line WL0 is transferred to the bit line respectively. B
Read to Lj. In this case, the threshold voltage of the transistor of the memory cell is 5V or more (for example, 6
V), if the logic "1" is set to less than 5V (for example, 4V), the bit line from which the memory cell data of the logic "0" is read maintains the VR potential, while the logic "1" is maintained. The bit line from which the memory cell data is being read is discharged from the VR potential.

When the potential of the bit line from which the memory cell data of logic "1" is read becomes lower than the circuit threshold value of the sense amplifier SAj (time t3), the control signal TG of the bit line transfer gate is generated. Changes from Vss to Vcc, and the bit line data is transmitted to the sense amplifier SAj.

After that, the word line WL0 and bit line transfer gate control signal TG returns from Vcc to Vss (time t5). This timing t5 may be during the sense operation of the sense amplifier SAj to which the information of the bit line is transmitted,
It may be after the sense operation is completed. Also, the word line WL
Either 0 or the bit line transfer gate control signal TG may be preceded to return Vcc to Vss.

When the column selection line CSL0 selected by the column address changes from Vss to Vcc (time t4),
The data read and latched by the sense amplifier SA0 is transmitted to the input / output lines I0, / I0 and output via the input / output line sense amplifier circuit 7 and the data output buffer 8. When the column address changes, the column address transition detection circuit detects it, the next column selection line CSL1 is selected (time t7), and the read data is output to the sense amplifier SA1.

In this way, the sense amplifiers SA0 to S
The data stored in An is read out. If the row address changes while the column read operation continues, the row address transition detection circuit detects it and the bit line precharge signal PREB changes to Vcc. To Vss, the bit line BLj is charged to VR again (time t
6). After charging the bit line, the control signal PREB changes from Vcc to Vss again, the bit line BLj becomes floating at the VR potential, and the next word line WL1 selected by the row address changes from Vss to VH (time t8). ,
The data in the memory cell MC1j is read onto the bit line BLj.

When the memory cell data is read to the bit line by switching the word line, since the bit line transfer gate Qj2 is already turned off at the time t5, the sense amplifier SAj transfers to the input / output lines IO and / IO. It will be done without any problems in the form of simultaneous data transfer.

The column select line CSLn is selected by the nth column address (time t9), and the sense amplifier S
After the stored data of An is output, the sense amplifier reset signal RESETB changes from Vcc to Vss (time t1
0). As a result, the sense amplifier SA in which the data of the memory cell MC0j selected by the word line WL0 is stored.
All j are reset.

Next, the sense amplifier / reset signal RESE
When TB returns from Vss to Vcc and the bit line transfer gate control signal TG changes from Vss to Vss (time t11),
The bit line BLj from which the data of the memory cell MC1j selected by the word line WL1 is read is the sense amplifier SAj.
And the bit line data is transmitted to the sense amplifier SAj.

After that, as in the case of the previous column reading, the column selection line CSLj is sequentially selected (time t12, t14,
...), the storage data of the sense amplifier SAj is sequentially read. Meanwhile, the word line WL1 and the bit line transfer gate control signal TG are returned to Vss (time t13), and when the row address is further changed, the next word line WL2 is selected (time t15). Be done.

At the timing when the next row address is taken in while the data stored in the sense amplifier SAj is sequentially read, a change in the row address is detected, the bit line is precharged, and the word line is selected. The process until the data of the memory cell is read to the bit line and the potential of the bit line of logic "1" becomes lower than the circuit threshold value of the sense amplifier is completed until the column select line CSLn is selected. It is performed at such timing.

When the last row address is fetched, the data of the memory cell MCmj selected by the word line WLm is read, and the chip enable CE returns from "L" level to "H" level (time t16), a read operation is performed. Ends.

FIG. 7 shows the structure of a memory cell array of an embodiment in which the present invention is more specifically applied to a NAND cell type EEPROM, and FIG. 8 shows the structure of a sense amplifier circuit section.

The memory cell array, as shown in FIG.
Adjacent seven memory cells are connected in series so that the source and drain are shared by adjacent memory cells to form a NAND cell. The drain at one end of the NAND cell is connected to the bit line BL via the select gate, and the source at the other end is also connected to the common source line via the select gate. As shown in FIG. 8, the bit line sense amplifier circuit SAj is composed of two clock synchronous type CMOS inverters IN.
It is constructed by using V1 and INV2.

The bit line sense amplifier circuit is not limited to one bit line, but may be a so-called shared sense amplifier system in which one bit line is provided for a plurality of bit lines as shown in FIG. 9, for example. 10 to 12 show N of this embodiment.
FIG. 6 is a timing diagram showing a read operation of an AND cell type EEPROM.

When the chip enable / CE changes from the "H" level to the "L" level and the row address and the column address of the chip external input are taken in the chip, the read operation starts. The control signal PREB for precharging the bit line changes from Vcc to Vss, the PMOS transistor Qj1 is turned on, and the bit line BLj is precharged. After the bit line precharge, the control signal PREB is changed from Vcc to Vss again, and the bit line BLj is brought into the floating state of the potential VR. The word line WL00 selected by the row address keeps Vss, and the same NAN
The other word lines WL01 to WL07 in the D cell and the drain side and source side select gate lines SGD0, SGS0 are V
When ss changes to Vcc, the data of the memory cells MC000 to MCn00 along the selected word line WL00 is read to the bit line BLj.

The threshold voltage of the memory cell is, for example, 0.5V to 3.5V at logic "0" and -0.5V at logic "1".
If set as follows, the bit line from which the memory cell data of logic "0" is read maintains VR and the bit line of logic "1" is maintained.
The bit line from which the memory cell data is being read is discharged. When the potential of the bit line from which the memory cell data of logic "1" is read becomes lower than the circuit threshold of the sense amplifier SAj, the control signal TG of the bit line transfer gate changes from Vss to Vcc, and the bit The line data is transmitted to the sense amplifier SAj.

After that, the word lines WL01 to WL07, the select gate lines SGD0 and SGS0, and the bit line transfer gate control signal TG return from Vcc to Vss, but the timing is the sense amplifier S to which the information of the bit line is transmitted.
Aj may be during the sensing operation or after the sensing operation is completed. Further, one of the word line and select gate line and the bit line transfer gate control signal TG may be preceded to return Vcc to Vss.

Next, the column select line CSL0 selected by the column address changes from Vss to Vcc, and the data read to the sense amplifier SA0 is changed to the input / output line I0,
It is transmitted to the / I0 line and output via the input / output line sense amplifier circuit and the data output buffer.

When the column address changes, the column address transition detection circuit detects it and detects the next column selection line C.
SL1 is selected and the data latched by the sense amplifier SA1 is output.

In this way, the data stored in the sense amplifier circuits SA0 to SAn are sequentially read out. At the same time, if the row address changes, the row address transition detection circuit detects it and the bit line precharge. The signal PREB changes from Vcc to Vss, and the bit line BL
Charge j again to VR. After charging, control signal PREB
Changes from Vcc to Vss again, and the bit line BLj is precharged. Then, the next word line WL01 selected by the row address maintains Vss, the remaining word lines and select gate lines in the same NAND cell are changed from Vss to Vcc, and the data of the memory cells along the word line WL01 are changed to the bit line BLj. It is read.

After the column selection line CSLn is selected by the nth column address and the stored data of the sense amplifier SAn is output, the sense amplifier reset signal R is output.
ESETB changes from Vcc to Vss, and the sense amplifier SAj in which the memory cell data is stored is reset. The sense amplifier reset signal RESETB returns from Vss to Vcc, and the bit line transfer gate control signal T
When G changes from Vss to Vcc, the bit line BLj from which the data of the memory cell along the selected word line WL01 is read is connected to the sense amplifier SAj, and the data read to the bit line is transmitted to the sense amplifier.

After that, the column select line CSLj is sequentially selected, and the stored data of the sense amplifier SAj is sequentially read. While this column reading is being performed, the row address changes and the same process is repeated.

When the last row address is fetched, the data in the memory cell selected by word line WL07 is read, and chip enable / CE returns from "L" level to "H" level, the read operation is completed.

As described above, according to the present invention, the bit line transfer gate is provided between the bit line and the sense amplifier circuit while the data latched by the bit line sense amplifier circuit is being read out to the input / output line. The memory cell data is read out to the bit line by the selected word line and the operation is repeated.

In the present invention, in addition to the continuous read described above, normal random read, page mode, static column mode, and other random read with respect to page (word line direction) are also possible. Therefore, the control signal / SCAN input from the outside of the chip may be used to switch between the continuous read mode and the normal read mode. The external control signal / SCAN enters the logic control circuit 10 as shown in FIG. 1, whereby the continuous read mode and the normal read mode are switched.

FIG. 13 shows such a switching control signal / S.
It is a timing diagram which shows the read-out operation of the Example which used CAN. Control signal / SCAN goes from "H" level to "L"
When the chip enable / CE changes from “H” level to “L” level, the continuous read mode is set,
Random row addresses j7, k5, ..., S3 are taken in, and the column addresses are 0 to n for each row address.
Is continuously taken up to. When row addresses are randomly input as shown in FIG. 13 (a), the reading order of the memory cells is as shown in FIG. 13 (b).

In addition, when inputting the column address, FIG.
As shown in 3 (c), one dummy cycle may be input between the nth and 0th dummy cycles. During this dummy cycle, the sense amplifier circuit storing the previous data is reset, and the data of the next memory cell read to the bit line is transferred to the sense amplifier. FIG. 14 shows an embodiment in which a column address counter 11 is provided and a switching control signal / SCAN is input to it.

In the continuous read mode, the control signal / SCAN is used instead of the externally input column address as shown in FIG.
The column address counter 11 sequentially generates internal column addresses by toggling as shown in FIG. Also in this case, as shown in FIG. 15 (b), a system may be used in which / SCAN is input as a 1-pulse dummy cycle between the nth and 0th column addresses.

FIG. 16 shows an embodiment in which a row address / latch circuit 12 for storing a plurality of sets of row addresses is further provided. The row address / latch circuit 12 is controlled by the output of the column address counter 11 and takes in the row address latched at a specific column address.

That is, as shown in FIG. 19A, when a specific internal column address, that is, the l-th column address in the figure is output, the row address stored in the row address latch circuit 12 is output. . FIG. 17 shows a case where a specific column address is externally input, and the present invention is also effective in this case.

Further, as shown in FIG. 18, a shift register circuit 13 having the same number of bits as the number of memory cells cascade-connected in the NAND series may be provided. In this case, for example, when the NAND cell string of the word lines WL00 to WL07 is selected, one block (n + 1) × 8 is selected as shown in FIG. 19 (b).
Bit data is continuously read.

Since a shift register is used,
Even if the first word line specified by the input row address is WL01, after selecting word line WL07, it is possible to return to word line WL00 and continuously read the data for all word lines in the specified NAND string. Is.

Further, as shown in FIG. 20, the row address counter 14 is also provided inside the chip, and the data of the memory cells for the word line corresponding to the maximum number of bits of the row address counter 14 or all the word lines is continuously read. The present invention is effective even when the data is read out.

Further, the switching of the continuous read mode controls the data inputted from the write enable / WE and the data input Din as a command as shown in FIG. 21, without using the control signal / SCAN for the continuous read. It can also be configured as follows. Such a command method is particularly effective in the case of a multi-bit configuration of at least 2 bits or more.

Although the specific structure of the timing control circuit for continuous reading has not been shown above, it will be as shown in FIG. 22. When the chip enable / CE is at "L" level, the row address Row A outside the chip is
When dd. changes, this is taken into the chip by the row address buffer, and the rowless transition detection circuit 21
Therefore, a row address detection pulse is generated. Receiving this pulse, the bit line precharge circuit 22 operates to precharge the bit line BL. After charging, the bit line BL becomes a floating state, and the row decoder / word line driver 23 selects the word line WL.

When the memory cell data is transmitted to the bit line sense amplifier BL.S / A via the bit line BL,
The word line WL is reset, and the bit line transfer gate TG is rendered non-conductive by the output of the transfer gate driver 24.

Next, the column select line CSL0 is selected,
The data read to the bit line sense amplifier BL.S / A0 is transmitted to the input / output lines I / O and I / OB, and is transmitted through the input / output line sense amplifier I / O.S / A and the data output buffer. Is output.

Next, when the column address Col. Add. Changes, the column address transition detection circuit 25 detects this and generates a pulse, and the column decoder / column select line driver 26 controlled by this detects the next column. Select line CSL1 is selected and bit line sense amplifier BL
・ The data read to S / A1 is output.

Thus, the bit line sense amplifier BL.
The data stored in BL.S / An is read from S / A0, but at the same time, the next row address Row
When Add. Changes, the row address transition detection circuit 21 detects this and generates a pulse. In response to this pulse, the bit line precharge circuit 22 operates and the bit line BL is precharged again. After charging, bit line BL
Becomes a floating state, and the word line WL is selected by the row decoder / word line driver 23. After that, the column select line CSL is selected by the nth column address.
After n is selected and the data of the bit line sense amplifier BL.S / An is read, the bit line sense amplifier reset signal RESE obtained from the reset signal driver 27.
Bit line sense amplifier BL.S / A0 to S / depending on TB
An is reset.

Bit line sense amplifier reset signal RES
When ETB is restored and the bit line transfer gate is turned on by the driver 24 described below, the bit line BL reading the memory cell data is connected to the bit line sense amplifier.

Then, the column select lines CSL0 to CSLn are selected.
Are sequentially selected, and the bit line sense amplifier BL · S / A0
Data of .about.S / An are sequentially read. During this column reading, the next row address RowAdd. Changes, and the same process as above is repeated.

[0069]

As described above, in the non-volatile semiconductor memory device according to the present invention, in the continuous read operation, the dead time required at the time of switching the word lines is eliminated, and one block of the NAND string designated by the address or all the words are read. The data of the memory cells regarding the line can be smoothly and continuously read.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a memory cell array of the same embodiment.

FIG. 3 is a diagram showing a configuration of a sense amplifier unit of the same embodiment.

FIG. 4 is a timing chart showing a continuous read operation of the same embodiment.

FIG. 5 is a timing chart showing a continuous read operation of the same embodiment.

FIG. 6 is a timing chart showing a continuous read operation according to the embodiment.

FIG. 7 is a diagram showing a memory cell array configuration of an embodiment applied to a NAND cell type EEPROM.

FIG. 8 is a diagram showing a specific configuration example of a sense amplifier of the same embodiment.

FIG. 9 is a diagram showing a shared sense amplifier system.

FIG. 10 is a timing chart for explaining a continuous read operation of the embodiment.

FIG. 11 is a timing chart for explaining a continuous read operation of the embodiment.

FIG. 12 is a timing chart for explaining a continuous read operation of the embodiment.

FIG. 13 is an input timing chart of the embodiment using the continuous read control signal / SCAN.

FIG. 14 is a diagram showing a configuration of an embodiment incorporating a column address counter.

FIG. 15 is a timing chart for explaining the operation of the embodiment.

FIG. 16 is a diagram showing the configuration of an embodiment incorporating a row address latch circuit.

17 is a diagram showing a configuration of an embodiment in which a column address is externally input in FIG.

FIG. 18 is a diagram showing the configuration of an embodiment incorporating a row address shift register.

FIG. 19 is a diagram for explaining the continuous read operation of the embodiments of FIGS. 16 and 18;

FIG. 20 is a diagram showing the configuration of an embodiment incorporating a row address counter.

FIG. 21 is a diagram for explaining another read mode switching method.

FIG. 22 is a diagram showing a configuration example of a timing control circuit according to the present invention.

[Explanation of symbols]

1 ... memory cell array, 2 ... Row decoder, 3 ... Sense amplifier / data latch, 4 ... column decoder, 5 ... Row address buffer, 6 ... column address buffer, 7 ... I / O sense amplifier, 8 ... Data output buffer, 9 ... Data input buffer, 10 ... Logic control circuit, 11 ... column address counter, 12 ... Row address latch, 13 ... Shift register.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masaki Tomoki             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Inside the Toshiba Research Institute (72) Inventor Fujio Masuoka             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Inside the Toshiba Research Institute

Claims (9)

[Claims] 1. A memory cell array in which a plurality of word lines and a plurality of bit lines intersect each other, and a rewritable nonvolatile memory cell is arranged at each intersection of the word lines and the bit lines, and the memory. A unit for selecting a word line of the cell array; a unit for selecting a bit line of the memory cell array; a sense amplifier circuit having a latch function connected to a bit line of the memory cell array via a bit line transfer gate; A data input / output buffer to which an amplifier circuit is connected via a data input / output line, and data of a memory cell selected by a word line is latched by the sense amplifier circuit, and the data is read out to the data input / output line. The bit line transfer gate is turned off while the memory selected by the next word line The nonvolatile semiconductor memory device, wherein a data cell with a means for performing the reading timing controlled by the bit line. 2. The sense amplifier / data latch circuit comprises:
2. The nonvolatile semiconductor memory device according to claim 1, wherein at least two bit lines which are switch-connected by a transfer gate are shared. 3. The memory cell is an electrically rewritable E
The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is an EPROM cell. 4. The memory cell has a FETMOS structure, and a plurality of memory cells adjacent to each other are connected in series so as to share a source and a drain.
2. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device constitutes a ROM. 5. The means for performing the word line selection is a row address buffer and a row decoder, and the means for performing the bit line selection is a column address buffer and a column decoder. The nonvolatile semiconductor memory device described. 6. A memory cell array in which a plurality of word lines and a plurality of bit lines intersecting each other are arranged, and a rewritable nonvolatile memory cell is arranged at each intersection of the word lines and the bit lines, and the memory. A row decoder for selecting a word line of the cell array, a column decoder for selecting a bit line of the memory cell array, a sense amplifier circuit having a latch function connected to a bit line of the memory cell array via a bit line transfer gate, A data input / output buffer to which the sense amplifier circuit is connected via a data input / output line, and data of a memory cell selected by a certain word line is latched by the sense amplifier circuit, and the data is transferred to the data input / output line. While being read, turn off the bit line transfer gate and switch to the next word line. Means for controlling the timing of reading the data of the selected memory cell to the bit line, and the data read from the memory cell selected by the row address and latched in the sense amplifier circuit sequentially by the column decoder. A non-volatile semiconductor memory device, comprising: a continuous read control terminal for reading to a data input / output line. 7. A memory cell array in which a plurality of word lines and a plurality of bit lines intersecting each other are arranged, and a rewritable nonvolatile memory cell is arranged at each intersection of the word lines and the bit lines, and the memory. A row decoder for selecting a word line of the cell array, a column decoder for selecting a bit line of the memory cell array, a sense amplifier circuit having a latch function connected to a bit line of the memory cell array via a bit line transfer gate, A data input / output buffer to which the sense amplifier circuit is connected via a data input / output line, and data of a memory cell selected by a certain word line is latched by the sense amplifier circuit, and the data is transferred to the data input / output line. While being read, turn off the bit line transfer gate and switch to the next word line. Means for controlling the timing of reading the data of the selected memory cell to the bit line, and the data selected by the row address and latched in the sense amplifier circuit are sequentially read to the data input / output line by the column decoder. A non-volatile semiconductor memory device comprising: a column address counter. 8. A memory cell array in which a plurality of word lines and a plurality of bit lines intersecting each other are arranged, and a rewritable nonvolatile memory cell is arranged at each intersection of the word lines and the bit lines, and the memory. A row decoder for selecting a word line of the cell array, a column decoder for selecting a bit line of the memory cell array, a sense amplifier circuit having a latch function connected to a bit line of the memory cell array via a bit line transfer gate, A data input / output buffer to which the sense amplifier circuit is connected via a data input / output line, and data of a memory cell selected by a certain word line is latched by the sense amplifier circuit, and the data is transferred to the data input / output line. While being read, turn off the bit line transfer gate and switch to the next word line. A nonvolatile memory comprising means for controlling timing for reading data of a selected memory cell to the bit line, and a row address latch circuit for fetching and latching a plurality of sets of external row addresses. Semiconductor memory device. 9. A memory cell array comprising a plurality of word lines and a plurality of bit lines intersecting each other, and a rewritable nonvolatile memory cell arranged at each intersection of the word lines and the bit lines, and the memory. A row decoder for selecting a word line of the cell array, a column decoder for selecting a bit line of the memory cell array, a sense amplifier circuit having a latch function connected to a bit line of the memory cell array via a bit line transfer gate, A data input / output buffer to which the sense amplifier circuit is connected via a data input / output line, and data of a memory cell selected by a certain word line is latched by the sense amplifier circuit, and the data is transferred to the data input / output line. While being read, turn off the bit line transfer gate and switch to the next word line. And a row address counter or a shift register for designating one block of row addresses for continuous reading, and means for controlling timing of reading data of the selected memory cell to the bit line. Nonvolatile semiconductor memory device.