JPH05275838A - Module for electronic device - Google Patents
Module for electronic deviceInfo
- Publication number
- JPH05275838A JPH05275838A JP4012643A JP1264392A JPH05275838A JP H05275838 A JPH05275838 A JP H05275838A JP 4012643 A JP4012643 A JP 4012643A JP 1264392 A JP1264392 A JP 1264392A JP H05275838 A JPH05275838 A JP H05275838A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- circuit board
- board
- electronic device
- bare chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は電子装置用モジュールに
関し、特に外部回路との接続部を備えた電子装置用モジ
ュールに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device module, and more particularly to an electronic device module having a connection portion with an external circuit.
【０００２】[0002]
【従来の技術】従来、この種の電子装置用モジュール
は、例えばＩＣメモリーカードの様に、ケーシングされ
たＬＳＩ及び外部接続用コネクタ等をプリント板の上及
び端に実装し、この上にカバー等を取り付けた構造の製
品が実用化されている。2. Description of the Related Art Conventionally, a module for an electronic device of this kind has a packaged LSI and an external connection connector mounted on the top and the end of a printed board, such as an IC memory card, and a cover and the like mounted thereon. A product with a structure attached is put into practical use.
【０００３】一方、成形射出されたプラスチック筺体に
回路パターンを形成し、その上に部品を実装する技術は
ＭＩＰとして知られており、例えばエレクトロ パッケ
ージング ニーズ メット バイ スリー ディメンジ
ョナル モールデド インタコネクション パッケージ
ング（Ｅｌｅｃｔｒｏ Ｐａｃｋａｇｉｎｇ Ｎｅｅｄ
ｓ Ｍｅｔ ｂｙ Ｔｈｒｅｅ Ｄｉｍｅｎｔｉｏｎａ
ｌ Ｍｏｌｄｅｄ Ｉｎｔｅｒｃｏｎｎｅｃｔｉｏｎ
Ｐａｃｋａｇｉｎｇ）ヒューチャー トランスポーテー
ション テクノロジー コンファレンス アンド エク
スポジションシアトル，ワシントン（Ｆｕｔｕｒｅ Ｔ
ｒａｎｓｐｏｒｔａｔｉｏｎ Ｔｅｃｈｎｏｌｏｇｙ
Ｃｏｎｆｅｒｅｎｃｅ ａｎｄ Ｅｘｐｏｓｉｔｉｏｎ
Ｓｅａｔｔｌｅ，Ｗａｓｈｉｎｇｔｏｎ）（Ａｕｇｕ
ｓｔ １０−１３，１９８７）で紹介されている様に、
モールド整形された筺体に３次元実装する方法でＳＭＴ
（Ｓｕｒｆａｃｅ Ｍｏｕｎｔ Ｔｅｃｈｎｏｌｏｇ
ｙ）を実現している。On the other hand, a technique for forming a circuit pattern on a molded and injected plastic housing and mounting components on it is known as MIP. (Electro Packing Need
s Met by Three Dimensiona
l Molded Interconnection
Packing) Future Transportation Technology Conference and Exposition Seattle, Washington (Future T)
transportation technology
Conference and Expoition
Seattle, Washington) (Augu
st 10-13, 1987),
SMT by the method of three-dimensional mounting on the molded housing
(Surface Mount Technology)
y) is realized.
【０００４】類似分野として混成ＩＣがある。これはセ
ラミック基板上にパターンを形成し、その上にケーシン
グされたＬＳＩやベアチップ、コンデンサ、抵抗等を搭
載し樹脂コートしている。A hybrid IC is a similar field. In this, a pattern is formed on a ceramic substrate, and an LSI, a bare chip, a capacitor, a resistor, etc., which are casing thereon, are mounted and resin-coated.
【０００５】[0005]
【発明が解決しようとする課題】この従来の電子装置用
モジュールは、ＩＣメモリカード等のように、たえず外
部環境に搭載部品がさらされているか、カバー等により
さらされにくい構造となっているが、長年の間には搭載
部品に外部環境の影響を受けることが考えられ、高密度
実装の為ＬＳＩ等のベアチップを搭載することは非常に
困難であった。This conventional electronic device module has a structure such as an IC memory card or the like in which mounted components are constantly exposed to the external environment or a cover or the like that makes it difficult to expose. However, it has been considered that mounted components are affected by the external environment for many years, and it has been very difficult to mount a bare chip such as an LSI because of high-density mounting.
【０００６】また、混成ＩＣでは、ベアチップの搭載は
行われているが、セラミック板に凹凸をつける等の加工
が困難であり、３次元実装を行うのは難しく、薄くする
のに限界があるという問題点があった。Further, in the hybrid IC, although a bare chip is mounted, it is difficult to process the ceramic plate such as making it uneven, and it is difficult to carry out three-dimensional mounting, and there is a limit to thinning. There was a problem.
【０００７】[0007]
【課題を解決するための手段】本発明の電子装置用モジ
ュールは、絶縁材料による平板状の基板に、この基板の
少なくとも１つの辺に沿って形成された外部回路との接
続用のコネクタ部、少なくとも片面に形成されたパター
ン配線、及び回路部品を挿入固定するための複数の凹部
を設けた回路板と、この回路板の各凹部にそれぞれ前記
パターン配線と接続して挿入固定されたＬＳＩのベアチ
ップを含む複数の回路部品と、前記回路板のコネクタ部
以外の部分及び前記複数の回路部品全てを内部に封入す
る外装樹脂部とを有している。According to another aspect of the present invention, there is provided a module for an electronic device, in which a flat plate-shaped substrate made of an insulating material is formed on at least one side of the substrate for connection with an external circuit. A circuit board having at least one pattern wiring formed on one side and a plurality of recesses for inserting and fixing circuit components, and an LSI bare chip fixedly inserted into each recess of the circuit board by connecting to the pattern wiring. A plurality of circuit components including the above, and a portion other than the connector portion of the circuit board and an exterior resin portion that encloses all of the plurality of circuit components therein.
【０００８】また、凹部の底面にパターン配線と接続す
るはんだバンプが形成され、このはんだバンプに回路部
品の電極を接続する構造を有している。Further, a solder bump is formed on the bottom surface of the recess for connecting to the pattern wiring, and the electrode of the circuit component is connected to the solder bump.
【０００９】また、回路部品を接続，挿入固定した回路
板を複数枚積層し、これらを外装樹脂により一体封入形
成した構造を有している。Further, it has a structure in which a plurality of circuit boards to which circuit parts are connected, inserted and fixed are laminated, and these are integrally encapsulated by an exterior resin.
【００１０】[0010]
【実施例】次に本発明の実施例について図面を参照して
説明する。Embodiments of the present invention will now be described with reference to the drawings.
【００１１】図１（ａ），（ｂ）は本発明の第１の実施
例の外観斜視図及び断面図である。1A and 1B are an external perspective view and a sectional view of a first embodiment of the present invention.
【００１２】回路板１は、絶縁材料による平板上の基板
１１に、この基板１１の一辺に沿って形成され外部回路
と接続するための複数の接続端子部１３を含むコネクタ
部１２と、両面に形成されスルーホール１５を介して互
いに接続するパターン配線１４と、回路部品を挿入固定
するための複数の凹部１６とを設けた構造となってい
る。The circuit board 1 has a flat plate substrate 11 made of an insulating material, a connector portion 12 formed along one side of the substrate 11 and having a plurality of connection terminal portions 13 for connecting to an external circuit, and both surfaces thereof. The structure is such that the pattern wirings 14 formed and connected to each other through the through holes 15 and the plurality of recesses 16 for inserting and fixing circuit components are provided.
【００１３】この回路板１の各凹部１６には、ＬＳＩの
ベアチップ３、抵抗等の受動素子４等が挿入固定され、
これらベアチップ３，受動素子４等の電極はボンディン
グ線５やはんだ６によりパターン配線１４に接続されて
いる。The bare chip 3 of the LSI, the passive element 4 such as a resistor, etc. are inserted and fixed in each recess 16 of the circuit board 1,
The electrodes of the bare chip 3, the passive element 4 and the like are connected to the pattern wiring 14 by the bonding wire 5 and the solder 6.
【００１４】そして、回路板１のコネクタ部１２以外の
部分及びベアチップ３，受動部品４等を含む全ての回路
部品を内部に封入するように外装樹脂部２が形成されて
いる。The exterior resin portion 2 is formed so as to encapsulate all the circuit components including the bare chip 3, the passive component 4 and the like other than the connector portion 12 of the circuit board 1 therein.
【００１５】図２（ａ）〜（ｃ）にこの実施例の回路板
１及びベアチップ３，受動素子４の分解斜視図、並びに
ベアチップ３，受動素子４の接続固定状態の詳細を表示
する断面図を示す。2 (a) to 2 (c) are exploded perspective views of the circuit board 1 and the bare chip 3 and the passive element 4 of this embodiment, and a sectional view showing details of the connection / fixing state of the bare chip 3 and the passive element 4. Indicates.
【００１６】回路板１は、まず、モールド成形により、
ＬＳＩのベアチップ３や受動素子４等を挿入固定する凹
部１６を、また裏面のパターン配線と接続するためのス
ルーホール１５用の穴を同時に成形する。次に、めっき
等により外部回路接続用のコネクタ部１２の接続端子部
１３、回路を構成するためのパターン配線１４、スルー
ホール１５，パッド１７等を同時に形成する。The circuit board 1 is first molded by molding.
A recess 16 for inserting and fixing the bare chip 3 of the LSI, the passive element 4 and the like, and a hole for a through hole 15 for connecting to the pattern wiring on the back surface are simultaneously formed. Next, the connection terminal portion 13 of the connector portion 12 for external circuit connection, the pattern wiring 14 for forming a circuit, the through hole 15, the pad 17 and the like are simultaneously formed by plating or the like.
【００１７】こうして図２に示す回路板１が完成する。
そして、凹部１６にベアチップ３，受動素子４等が挿入
固定され、ボンディング線５や、はんだ６によりこれら
の電極とパターン配線１４とが接続される。はんだ付け
はリフローによる表面実装技術（ＳＭＴ）を使用すると
よい。Thus, the circuit board 1 shown in FIG. 2 is completed.
Then, the bare chip 3, the passive element 4 and the like are inserted and fixed in the concave portion 16, and these electrodes and the pattern wiring 14 are connected by the bonding wire 5 and the solder 6. Surface mounting technology (SMT) by reflow may be used for soldering.
【００１８】この後、インサートモールドにより外装樹
脂部２が形成される。After that, the exterior resin portion 2 is formed by insert molding.
【００１９】このような構造とすることにより、ベアチ
ップ３を含む回路部品を外部環境から遮断することがで
きるので、長期間信頼性を保証することができる。ま
た、回路部品は回路板１の凹部１６に挿入固定されてい
るので、全体の厚さを薄くすることができる。With such a structure, the circuit components including the bare chip 3 can be shielded from the external environment, so that long-term reliability can be guaranteed. Moreover, since the circuit component is inserted and fixed in the recess 16 of the circuit board 1, the overall thickness can be reduced.
【００２０】なお、回路部品とパターン配線１４との接
続は、図３に示すように、凹部１６の底面にパターン配
線１４と接続するバンプ１８を設け、このバンプ１によ
り行うことができる。The circuit component and the pattern wiring 14 can be connected by the bump 1 provided on the bottom surface of the recess 16 and connected to the pattern wiring 14 as shown in FIG.
【００２１】図４は本発明の第２の実施例を示す断面図
である。FIG. 4 is a sectional view showing a second embodiment of the present invention.
【００２２】この実施例は、３枚の回路板１ａ，１ｂ，
１ｃを積層してインサートモールドにより一体化形成し
たものである。このように立体化構造にしても、一枚一
枚の回路板が薄くできるので、この場合も全体の厚さを
薄くすることができる。なお、各回路板のパターン配線
間の接続はスルーホールにピン７を注入する等の方法で
行うことができる。また当然、はんだ付けでもよい。In this embodiment, three circuit boards 1a, 1b,
1c is laminated and integrally formed by insert molding. Even with such a three-dimensional structure, each circuit board can be made thin, and in this case as well, the overall thickness can be made thin. The connection between the pattern wirings of each circuit board can be made by a method of injecting the pin 7 into the through hole. Of course, soldering may be used.
【００２３】図５は本発明の第３の実施例を示す断面図
である。FIG. 5 is a sectional view showing a third embodiment of the present invention.
【００２４】この実施例は、コレクタ部１２に接続端子
部１３と接続するばね接触子８１をもつ電気コネクタ８
が接続されており、より高密度で外部回路との入出力が
可能になる。In this embodiment, an electrical connector 8 having a spring contactor 81 for connecting the collector portion 12 to the connection terminal portion 13 is provided.
Are connected, and input / output with an external circuit can be performed with higher density.
【００２５】図６は本発明の第４の実施例を示す断面図
である。FIG. 6 is a sectional view showing a fourth embodiment of the present invention.
【００２６】この実施例は、ベアチップ３が回路板１ｄ
の両面に実装できるように、両面に凹部１６を有してい
る。In this embodiment, the bare chip 3 is the circuit board 1d.
The concave portions 16 are provided on both sides so that the concave portions 16 can be mounted on both sides.
【００２７】図７は本発明の第５の実施例を示す断面図
である。FIG. 7 is a sectional view showing the fifth embodiment of the present invention.
【００２８】この実施例は、片面にＡｌなどで形成され
たヒートシンク９を取り付けたもので、インサートモー
ルドを行う段階で同時に取付けることにより後付けの手
間をなくすことができる。In this embodiment, a heat sink 9 made of Al or the like is attached to one surface, and by simultaneously attaching the heat sink 9 at the stage of performing insert molding, it is possible to eliminate the trouble of retrofitting.
【００２９】[0029]
【発明の効果】以上説明したように本発明は、絶縁材料
による平板状の基板に、この基板の一辺に沿って形成さ
れた外部回路との接続用のコネクタ部と、片面又は両面
に形成されたパターン配線と、回路部品を挿入固定する
ための複数の凹部とを設けた回路板を形成し、この回路
板の凹部にベアチップ，受動素子等を挿入固定して電気
的接続を行い、コネクタ部以外を全て外装樹脂部で封入
する構造とすることにより、ベアチップを含む回路部品
等を外部環境から遮断できるので長期間信頼性を保証す
ることができ、また回路部品を凹部に挿入固定できるの
で全体の厚さを薄くすることができる効果がある。As described above, according to the present invention, a flat substrate made of an insulating material is formed on one side or both sides of a connector portion for connection with an external circuit formed along one side of the substrate. Forming a circuit board provided with a plurality of concave portions for inserting and fixing circuit parts and fixing circuit parts, and inserting and fixing a bare chip, a passive element, etc. in the concave portion of the circuit board for electrical connection. By encapsulating everything except the exterior resin part, the circuit components including the bare chip can be shielded from the external environment, so long-term reliability can be guaranteed, and the circuit components can be inserted and fixed in the recesses, so the whole The effect is that the thickness can be reduced.
【図１】本発明の第１の実施例を示す外観斜視図及び断
面図である。FIG. 1 is an external perspective view and a sectional view showing a first embodiment of the present invention.
【図２】図１に示された実施例の回路板及び回路部品の
分解斜視図並びに回路部品の挿入固定，接続の詳細を示
す断面図である。FIG. 2 is an exploded perspective view of a circuit board and circuit components of the embodiment shown in FIG. 1 and a sectional view showing details of insertion fixing and connection of the circuit components.
【図３】図１に示された実施例の回路部品の接続の他の
例を示す断面図である。FIG. 3 is a cross-sectional view showing another example of connection of the circuit components of the embodiment shown in FIG.
【図４】本発明の第２の実施例を示す断面図である。FIG. 4 is a sectional view showing a second embodiment of the present invention.
【図５】本発明の第３の実施例を示す断面図である。FIG. 5 is a sectional view showing a third embodiment of the present invention.
【図６】本発明の第４の実施例を示す断面図である。FIG. 6 is a sectional view showing a fourth embodiment of the present invention.
【図７】本発明の第５の実施例を示す断面図である。FIG. 7 is a sectional view showing a fifth embodiment of the present invention.
１，１ａ〜１ｅ 回路板 ２，２ａ〜２ｃ 外装樹脂部 ３ ベアチップ ４ 受動素子 ５ ボンディング線 ６ はんだ ７ ピン ８ 電気コネクタ ９ ヒートシンク １１ 基板 １２ コネクタ部 １３ 接続端子部 １４ パターン配線 １５ スルーホール １６ 凹部 １７ パッド １８ バンプ ３１ 電極 ８１ ばね接触子 1, 1a to 1e Circuit board 2, 2a to 2c Exterior resin part 3 Bare chip 4 Passive element 5 Bonding wire 6 Solder 7 pin 8 Electrical connector 9 Heat sink 11 Board 12 Connector part 13 Connection terminal part 14 Pattern wiring 15 Through hole 16 Recess 17 Pad 18 Bump 31 Electrode 81 Spring contact
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/29 23/31 Ｈ０５Ｋ 1/11 Ｃ 7511−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 23/29 23/31 H05K 1/11 C 7511-4E
Claims (3)
板の少なくとも１つの辺に沿って形成された外部回路と
の接続用のコネクタ部、少なくとも片面に形成されたパ
ターン配線、及び回路部品を挿入固定するための複数の
凹部を設けた回路板と、この回路板の各凹部にそれぞれ
前記パターン配線と接続して挿入固定されたＬＳＩのベ
アチップを含む複数の回路部品と、前記回路板のコネク
タ部以外の部分及び前記複数の回路部品全てを内部に封
入する外装樹脂部とを有することを特徴とする電子装置
用モジュール。1. A flat board made of an insulating material, and a connector portion for connection with an external circuit formed along at least one side of the board, a pattern wiring formed on at least one surface, and a circuit component. A circuit board having a plurality of recesses for inserting and fixing, a plurality of circuit components including an LSI bare chip inserted into and fixed to each of the recesses of the circuit board, and a connector of the circuit board. A module for an electronic device, comprising a portion other than a portion and an exterior resin portion that encloses all of the plurality of circuit components therein.
んだバンプが形成され、このはんだバンプに回路部品の
電極を接続する構造とした請求項１記載の電子装置用モ
ジュール。2. The module for an electronic device according to claim 1, wherein a solder bump for connecting to a pattern wiring is formed on the bottom surface of the recess, and the electrode of the circuit component is connected to the solder bump.
複数枚積層し、これらを外装樹脂により一体封入形成し
た構造の請求項１記載の電子装置用モジュール。3. The electronic device module according to claim 1, which has a structure in which a plurality of circuit boards, to which circuit components are connected, inserted and fixed, are laminated, and which are integrally encapsulated by an exterior resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4012643A JPH05275838A (en) | 1992-01-28 | 1992-01-28 | Module for electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4012643A JPH05275838A (en) | 1992-01-28 | 1992-01-28 | Module for electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05275838A true JPH05275838A (en) | 1993-10-22 |
Family
ID=11811047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4012643A Withdrawn JPH05275838A (en) | 1992-01-28 | 1992-01-28 | Module for electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05275838A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007531083A (en) * | 2003-07-17 | 2007-11-01 | サンディスク コーポレイション | Memory card with ridge |
| JP2008112929A (en) * | 2006-10-31 | 2008-05-15 | Sanyo Electric Co Ltd | Circuit device, and manufacturing method of the same |
| JP2011090658A (en) * | 2009-10-23 | 2011-05-06 | Walton Advanced Engineering Inc | Heat radiator and electronic circuit module |
| WO2014122867A1 (en) * | 2013-02-08 | 2014-08-14 | 株式会社ケーヒン | Electronic circuit device and method for manufacturing same |
| WO2015019423A1 (en) * | 2013-08-06 | 2015-02-12 | 本田技研工業株式会社 | Electronic circuit connecting structure |
-
1992
- 1992-01-28 JP JP4012643A patent/JPH05275838A/en not_active Withdrawn
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007531083A (en) * | 2003-07-17 | 2007-11-01 | サンディスク コーポレイション | Memory card with ridge |
| US7864540B2 (en) | 2003-07-17 | 2011-01-04 | Sandisk Corporation | Peripheral card with sloped edges |
| JP2008112929A (en) * | 2006-10-31 | 2008-05-15 | Sanyo Electric Co Ltd | Circuit device, and manufacturing method of the same |
| JP2011090658A (en) * | 2009-10-23 | 2011-05-06 | Walton Advanced Engineering Inc | Heat radiator and electronic circuit module |
| WO2014122867A1 (en) * | 2013-02-08 | 2014-08-14 | 株式会社ケーヒン | Electronic circuit device and method for manufacturing same |
| JPWO2014122867A1 (en) * | 2013-02-08 | 2017-01-26 | 株式会社ケーヒン | Electronic circuit device and manufacturing method thereof |
| US9713260B2 (en) | 2013-02-08 | 2017-07-18 | Keihin Corporation | Electronic circuit device and method for manufacturing same |
| WO2015019423A1 (en) * | 2013-08-06 | 2015-02-12 | 本田技研工業株式会社 | Electronic circuit connecting structure |
| JP5961763B2 (en) * | 2013-08-06 | 2016-08-02 | 本田技研工業株式会社 | Electronic circuit connection structure |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990408 |