JPH05260373A - Digital video signal processor - Google Patents

Abstract

PURPOSE:To make the processor compatible with the High Vision system by executing parallel arithmetic operation processing for plural programmable arithmetic operation processings at an operating speed being a half of a High Vision rate as to one instruction so as to realize the sophisticated arithmetic operation processing at a high speed thereby improving the degree of freedom of function revision and system revision. CONSTITUTION:Input processing sections 10(1), 10(2) receive 2-systems of 16-bit data IN-A, IN-B of a network 4 to apply synchronization flag processing and output the result to a selector 11. The selector 11 selects channel inputs selectively and sends the output to a processing section 12. An ALU 13 fetches output data of two systems of two channels selected by the selector 11, applies arithmetic operation processing and sends the result to one system of internal channel of the selector 11. AU14(1), 14(2) implement address operation for accessing a data memory and waveform generation and input the result to the selector 11. A mode processing section of the AU14 easily realizes 4-point interpolation calculation of the geometrical transformation and makes processing at an operating speed of a 1/2 of the sampling frequency as a High Vision Y signal especially.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal processing device used in broadcasting signal processing equipment such as a broadcasting station, and more particularly to an improvement for supporting a high-definition system.

[0002]

2. Description of the Related Art Generally, a digital video signal processing device used in a broadcasting station is composed of individual dedicated processing units according to the purpose of processing a video signal. Therefore, as the number of processing items increases, the number of units also increases, and the size of the entire apparatus becomes large. Along with this, a great deal of labor is required for construction work for realizing a desired processing function, such as device design, maintenance, and unit combination.

Therefore, recently, a digital image processing apparatus which can realize a desired processing function by software and does not require physical connection work is being put into practical use. This device is equipped with a plurality of arithmetic processing units and a network unit, and each arithmetic processing unit is externally provided with a program corresponding to a processing item of a video signal to realize a target processing function, and the network unit externally receives an entire image. A program is provided according to the purpose of signal processing to realize a connection line that connects the functions obtained in each arithmetic processing unit.

On the other hand, in order to improve the quality of broadcast video,
Hi-vision system is being developed. Compared with the conventional NTSC system and the like, this high-definition system has a very high sampling frequency and requires various processing functions. Broadcasting stations and the like tend to handle both high-definition and conventional video signals. However, the conventional digital video signal processing device has a low degree of freedom in calculation processing capability, function change, and system change, and cannot support the high-definition system.

From such a background, it is strongly required to develop the digital video signal processing device by the above software so as to be compatible with the high-definition system and to be used together with the conventional system.

[0006]

As described above, the conventional digital video signal processing device has a low degree of freedom in arithmetic processing capability, function change, and system change, and cannot support the high-definition system.

The present invention has been made in order to solve the above problems, and it is possible to realize high-speed and high-level arithmetic processing and to improve the degree of freedom in changing functions and changing systems. It is an object of the present invention to provide a digital video signal processing device that can also be used.

[0008]

In order to achieve the above object, the present invention provides a host control means for externally controlling the contents of each arithmetic processing of a plurality of programmable arithmetic processing units and the connection form of each programmable arithmetic processing unit by a network unit. In the digital video signal processing device configured to be freely set from the above, the programmable arithmetic processing unit has two input units to which the video signals are respectively supplied, and the video signal input to the input units is It is possible to supply a plurality of operands for performing arithmetic processing according to a program and deriving the result, input units to which output signals from the operands are respectively supplied, and two video signals from the network unit. Output section and final output respectively corresponding to each input section and the input sections of the plurality of operands A selector that has one output unit for deriving, can programmatically supply the signal of each input unit to the plurality of operands, and derives one of the input signals as a final output signal; Program control means for controlling the program of the operand and selector according to the instruction from the host control means, and the operation processing content of the operand and the connection form of each operand by the selector can be freely set from the outside through the host control means. It is characterized by having an operation speed of 1/2 of the high-definition rate for at least one instruction.

[0009]

In the digital video signal processing device having the above-mentioned configuration, the plurality of programmable arithmetic processing units each have an operation speed of 1/2 of the high definition rate for one instruction, but parallel arithmetic processing can be performed by a plurality of operands that each has. Therefore, even a high-definition video signal can be processed in real time, and can also be applied to a conventional system such as NTSC.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the overall structure of a digital video signal processing device according to the present invention. 1 (1) -1
(N) (n is arbitrary) has 16 input channels,
The signal processing cluster has 16 output channels (each channel is 16-bit parallel, and so on). The clusters 1 (1) to 1 (n) are connected in cascade, and each is a LAN.
Through the (local area network) 2, the host computer 3 switches and controls the processing function and the connection line according to the command input from the operator.

FIG. 2 shows the internal structure of the above-mentioned cluster (1 (1) is shown here as a representative). The network 4 and 16 programmable arithmetic units (PU) 5 (1)-
5 (16), and host controller 6.

The network 4 has 16 external input channels (IN1 to IN16) and 1 internal input channel.
6 (IN17 to IN32), 16 external output channels
(OUT1 to OUT16), 32 internal output channels
In (OUT17 to OUT48), the host controller 6
Any input channel can be connected to any output channel in response to a control signal from.

Programmable arithmetic units 5 (1) -5
(16) is a video rate video signal processing LSI that has the same configuration and can be applied from NTSC system to high-definition system, receives output data of two predetermined internal output channels of the network 4, and specifies it by the host controller 6. The arithmetic processing is performed according to the program, and the processing result is sent to one predetermined internal input channel of the network 4. Especially in video signal processing,
Various operations are performed with a cycle of 27 ns (= 1 / 37.125 MHz) and 24-bit precision.

The host controller 6 is for connecting the host computer 3 to the network 4 and the programmable devices 5 (1) to 5 (16) through the LAN 2.

FIG. 3 shows a specific configuration of the programmable arithmetic unit (here, 5 (1) is shown as a representative), and 7 is a DSP (digital signal processor) unit for performing digital signal processing. 8 is a DSP unit 7
A program memory for storing the processing function given to the above and the program of the connection line, and a data memory 9 for appropriately storing data necessary for the processing process of the DSP unit 7. This data memory 9 has two systems, DM-A and DM-B,
Each of them can store up to 1 Mbytes (corresponding to one field of a high-definition signal) and can be used as a lookup table (LUT) in a non-linear arithmetic unit. FIG. 4 shows a specific configuration of the DSP unit 7.

In FIG. 4, input processing units 10 (1), 1
0 (2) inputs 16-bit data IN-A and IN-B of the two internal output channels of the network 4, respectively, and performs a synchronization flag process. The synchronization flag is used to synchronize with the preceding circuit and is 8000H (-327).
The value of 68) is taken. Therefore, the data is 7FFFH
The range is (32767) to 8001H (-32767). The outputs of the input processing units 10 (1) and 10 (2) are sent to two external input channels (16 bits) of the selector 11.

The selector 11 has two external input channels, nine internal input channels, one external output channel, and four internal output channels for data output, and any channel input according to given program data. Is selectively switched to an arbitrary channel output.

The output processing unit 12 takes in the output data of the external output channel 1 system (16 bits) of the selector 11, performs the synchronization flag process, and sends it to the internal input channel 1 system of the network 4. As the synchronization flag processing here, when the synchronization is OFF, the data is replaced with 8001H when the data is 8000H, and when the synchronization is ON, it is forced to
Replace with 00H.

ALU (arithmetic logic operation unit) 13 (1), 1
3 (2) fetches output data of two channels (24 bits) selected by the selector 11, performs arithmetic processing specified by given program data, and outputs the processing result (24 bits) to the selector 11 It is sent to one internal input channel of. As the arithmetic processing,
In addition to the usual arithmetic logic operation, the maximum / minimum value and absolute value operation functions that are often used in TV signal processing are included and processed with 24 bits. On overflow during 24-bit operation, it is clipped to the maximum positive or negative value.

Concretely, as shown in FIG. 5, one channel input has a variable delay A1 of maximum 3 taps.
Then, the delay compensation is performed so as to match the input timing of the other channel, and it is supplied to the calculator A2 together with the input of the other channel. Delay amount of variable delay A1 and calculator A2
The calculation content of is switched and set according to the program data. The calculation result of the calculator A2 is supplied to the register bank A3.

The register bank A3 includes a plurality of (here, six) 24-bit arithmetic registers. One (or two) of them is the global register A31.
And the stored data becomes the ALU output,
The other four are used as local registers A32, and the held data are provided to the arithmetic operation of the arithmetic unit A2 as necessary. The global register A31 functions as a pipeline register.

AU (address calculation unit) 14 (1), 14
(2) is used for address calculation for accessing the data memory 9 or waveform generation, and for example, one can perform horizontal address calculation and the other vertical address calculation. The output address data of one channel (24 bits) selected by the selector 11 is fetched, the address calculation processing designated by the given program data is performed, and the processing result (24 + 6 bits) is input to the internal input channel of the selector 11. Send to one system.

Specifically, it is constructed as shown in FIG. 6 and has an address generator B1 inside. The address generator B1 is composed of an address calculator B11 and an address register bank B12. The address register bank B12 has 6 arithmetic registers and can perform addition, subtraction, 1/2 operation, etc. together with the address arithmetic unit B11. The calculation content is set by the program data.

The address data generated by the address generator B1 is supplied to the internal selector B2 together with the external input address data (internal output of the selector 11). The internal selector B2 takes in the internally generated address data and the external input address data, and selectively derives one of them to the comparator B3 and the address processing unit B4 according to the program data.

The comparator B3 compares the input address data with a preset specified value (for example, maximum and minimum limit values), and when the specified value is exceeded, sets a flag and sends it to the address processing unit B4.

The address processing unit B4 is a replacement processing unit B4.
1, a shifter unit B42, and a mode processing unit B43. The replacement processing unit B41 is used for clipping, for example, and replaces the input address data with a predetermined value according to the flag from the comparator B3. The shifter unit B42 is a barrel shifter capable of bit shifting in eight modes, and can set the decimal point position of 24-bit input address data arbitrarily.

The mode processing unit B43 is through, plus 1, right 1 for the integer part after being shifted by the shifter unit B42.
Bit shift and LSB processing can be selected, and through and 1 minus can be selected for the decimal part. The selection is performed based on the program data, and there are cases where it is fixedly selected and cases where it is automatically selected by the calculated LSB of the integer part. The processed data is divided into an integer part of 20 bits and a decimal part of 6 bits and output. The 6 bits of fractional part are used for adjacent 4-point interpolation calculation at the time of reduction / enlargement in the digital special effect.

By this mode processing, 4 at the time of geometric conversion
Calculation of point interpolation can be easily realized. In particular, when sub-sampling is performed at 1/2 the sampling frequency, like the high definition Y signal, the "automatic selection mode by LSB of the integer part" is effective. AU14 (1), 1 with this configuration
By using 4 (2), the data memory 9 can be accessed in parallel with the data calculation.

MPY (multiplier) 15 (1), 15 (2)
Uses a macro cell of 16 × 16 = 32 bits, and 24 bits can be cut out from 32 bits in three kinds of modes. The output data of the two channels (16 bits) selected by the selector 11 are respectively fetched, and both input data are multiplied in the format specified by the given program data,
The calculation result is used as the internal input channel (1
(6 bits) Send to one system.

Concretely, as shown in FIG. 7, one channel input has a variable delay C1 of maximum 3 taps.
The delay compensation is performed so as to match the input timing of the other channel, and the signal is supplied to the multiplier C2 together with the input of the other channel. Delay amount of variable delay C1 and multiplier C2
The calculation content of is switched and set according to the program data. The calculation result of the multiplier C2 is supplied to the register bank C3.

The register bank C3 includes a plurality of (here, six) 24-bit arithmetic registers. One (or two) of them is the global register C31.
Is used as, and the held data becomes MPY output,
The other four are used as local registers C32, and the held data are provided to the operation of the multiplier C2 as needed. The global register C31 functions as a pipeline register.

The variable delays 16 (1) and 16 (2) are
Output data of one channel (16 bits) selected by the selector 11 is fetched, timing adjustment is performed with 16 taps, and the data is sent to one internal input channel (16 bits) of the selector 11. Mainly used for delay phasing during multiprocessor operation. Each delay 1
If the selector 11 is assembled so that 6 (1) and 16 (2) are connected in cascade, a 32-tap delay can be achieved.

Data memory I / O (interface)
Reference numeral 17 denotes output data of one channel (16 bits) selected by the selector 11, channel (20 bits)
The output address data of one system is fetched, and the data memory 9 is written and read in accordance with the program data. The read data and address data are the selector 1
One internal input channel (16 bits) is sent out to one system.

Specifically, as shown in FIG. 8, data (1
6 bits) and address data (20 bits) are bit-shifted by the shifters D1 and D2 as needed, and one of the bank areas of the data memory 9 is selected by the selectors D3 and D4 in accordance with the program data for writing or writing. Read out.

Here, the data memory 9 has a two-bank configuration (DM-A, DM-B), and both A-system and B-system have 512 banks.
It has an address space of KW (1024 KB). At the time of high-definition, it can correspond to the data of 1/2 field in word and 1 field in byte. With this configuration, for example, a process of reading out a motion vector calculated using one data memory (field memory) from the other data memory is realized in real time, or a conversion process of image signal data is performed as a lookup table (LUT). It is possible to realize the processing that is performed in real time.

The selector 11, ALU 13 (1), 1
3 (2), AU14 (1), 14 (2), MPY15
(1), 15 (2), variable delay 16 (1), 16
(2) All the data memory I / Os 17 (hereinafter collectively referred to as operands) are connected to the internal bus 18. A host I / O 19 and a sequencer 20 are further connected to the internal bus 18.

The host I / O 19 is the host controller 6
For connecting the respective operands of the host computer 3 and the DSP unit 7. It has two banks of 16W × 16-bit registers for transfer with the host.

One bank faces the host, and the two banks are exchanged by manipulating the MSB of the 0th register. Further, by inserting the program start address in the 0th register, a plurality of operations are written in one program memory 8 and only the start address is switched, so that the functions can be switched instantaneously. Normally, such a switching operation can be performed in synchronization with vertical blanking and can be performed without affecting the effective period of the video, and the synchronization operation by multiple programmable arithmetic units can be easily performed. You can

The sequencer 20, which is the central part of the control mechanism, adopts a microprogram control system for performing instruction latching, decoding, branch control, operand control, etc. using the program memory 8 and collapses at the time of conditional branching. It has a structure suitable for video signal processing such as no pipeline operation and parallel operation of operands. The program is stored in the external program memory 8, and one cycle is 27 ns, and the pipeline operates in three stages of fetch, decode, and execute.

The program memory 8 can be switched between two modes of external 32 KW and internal 64 W, and the bit width of the microprogram is set to 48 bits. In the external mode, the internal program RAM is used as a cache when a branch instruction occurs, and a pipe break does not occur even when branching.

The structure of the 48-bit microinstruction consists of a SEQ instruction for branch control, a standard configuration instruction in which a FUNC instruction for operation control can be independently set in one instruction, and a full-field instruction having an immediate value as an operand. Divided into two types. Unlike ordinary general-purpose processors, the SEQ instruction has a three-branch structure of repeat, continue, and jump, and repeats the characteristic of image signal processing that often repeats the same processing for each pixel, and conditional branching with the same signal as the operation flag. The characteristics of the TV signal processing that simultaneously performs are reflected in the continue and jump.

Besides the SEQ instruction, an RST instruction for starting a program and a P instruction for a subroutine are also provided.
F for controlling all operands at the same time when handling time-axis multiplexed signals such as USH, POP commands, and standard TV component signals at high definition rates
There is an NC command.

Here, the program memory 8 and the sequencer 20 are conceptually constructed as shown in FIG. 9, and look-up tables LUT1 to LUT for each operand.
9 is provided. Program data for each function is stored in each table. The sequencer 20 identifies the function index data for each table from the host instruction, reads the corresponding program data from each table, and sends it to each operand through the internal bus 18. The sequencer 20 can also rewrite the function-specific program data of each table according to the control signal.

In this way, by designating one of the control tables for each operand by the index, 1
Indexes for multiple operands in an instruction are realized without increasing the instruction bit width. This command causes R
When processing time-division-multiplexed low-speed signals such as GB signals, the processing for each RGB signal can be changed,
One DSP unit can be used.

Inside the DSP unit 7, two data formats of 16 bits and 24 bits coexist. There are two types of data format conversion during this time, the standard transfer mode and the extended transfer mode, and it is possible to ensure sufficient accuracy.

For example, in the standard transfer mode, as shown in FIG. 10, 4-bit sign extension data is added before 16-bit data, 4-bit 0 data is added after 16-bit data, and 2
Convert to 4-bit data format. After the calculation, the leading and trailing bits are truncated and 16-bit data is taken out. In the extended transfer mode, 8-bit data is 4 + 4 as shown in FIG.
It is divided into bits, and a non-writable area corresponding to 16 bits is provided in the middle to convert to a 24-bit data format. After the calculation, only the preceding and following 4 bits are taken out and converted into 8-bit data.

Although not described in detail, the DSP unit further includes a line memory drive circuit, a program debug support circuit, and a synchronization circuit for parallel operation of a plurality of processors. Further, the variable pipeline structure which is a feature of the present invention will be described in detail.

In the conventional digital video signal processing device, a large number of arithmetic units (operands) having different functions are connected by a fixed path to form a pipeline. Such a circuit is suitable for performing only one kind of signal processing, but when a plurality of functions are realized by pressing switches in accordance with the operation on the operation panel, circuits corresponding to the number of functions are prepared.

Therefore, the connection of a plurality of arithmetic units has a variable pipeline structure in which the number of pipes can be changed, and a single circuit can be used to support a plurality of different functions. As described above, the variable delays A1 and C1 are provided on one operand input line, and the register banks A3 and C3 are provided on the output line.

According to this structure, it is possible to connect arbitrary arithmetic units by the selector 11. For example, the functional block of output = (input 1) + (constant) × (input 2) is as shown in FIG.
This is realized by using (1) and MPY15 (1) and connecting the selector 11 as shown in FIG. 12 (b). Further, the functional block of output = (input 1) × (constant 1) + (input 2) × (constant 2) is as shown in FIG. 12C, which is further used by the MPY15 (2) to select the selector 11
Is realized by connecting as shown in FIG.

As can be seen from FIG. 12, two different types of arithmetic processing can be realized by changing the connection with a single circuit. That is, an arbitrary circuit can be realized by adopting the variable pipeline structure. In FIG. 12 (a), two pipes,
In (c), there are three pipes, and the number of pipes can be set arbitrarily. In order to absorb the path difference (difference in the cumulative number of latches) that occurs when this connection is changed, the input variable delay A
1, C3 works effectively.

Therefore, by adopting the variable pipeline structure, an arbitrary circuit can be realized by a single circuit by changing the connection of the selector 11, the versatility is improved, and the operation efficiency of the arithmetic unit is increased. it can.

By the way, in a high-speed CPU or signal processor, as a debugging method, there are a software method using an internal interrupt and a hardware method using an emulator. However, in the case of a signal processor that emphasizes real-time property such as processing a TV digital signal, there is a possibility that a soft method may not completely correspond to a state where no debugging is performed. On the other hand, a hardware method using an in-circuit emulator is not realistic considering the multiprocessor configuration and the speeding up of the clock frequency. After all, in the past, it was necessary to make a judgment by looking at an image or to analyze the output result off-line via an image memory for debugging.

Therefore, here, the hardware necessary for debugging is incorporated in the DSP unit 7 in advance so that the debugging work can be easily realized. FIG. 13 shows its configuration.

In FIG. 13, 8 is the above-mentioned program memory, and 20 is a sequencer. This sequencer 20
An address latch F1 and an instruction latch F2 are provided for. The sequencer 20 causes the address latch F1 to latch the address for program instruction fetch, accesses the program memory 8 to fetch the instruction into the instruction latch F2, decodes the fetched instruction, and performs branch control by an operation flag or the like.

The address output to the address latch F1 is simultaneously sent to the comparator F3 and compared with the preset contents of the break point register F4. When a match is determined in this comparison, a match flag is set as the output of the comparator F3. When the match flag is set, the sequencer 20 stops its operation and also stops all clocks and sets the operand (A
The update of the contents of the output register of the LU 13 (1) etc. is stopped. At that time, through the external interface F5,
The output register of the operand enables the data to be read from outside the DSP unit 7.

In the above structure, when the program address to be interrupted is set in the breakpoint register F4 in advance, the comparator F3 compares the breakpoint address with the accessed program address. When the comparator F3 determines the match, the output register of the operand reads the data from the outside through the external interface F5.

Therefore, by suspending the processing at an arbitrary program location and checking the output register of the internal operand, it is possible to easily realize the debanging processing having a high real-time property. Some applications of the digital video signal processing device having the above configuration will be given.

FIG. 14 shows a functional configuration in the case of performing key mixing by one cluster for two digital video signals A and B of the high definition system. It should be noted that the video signals A and B are distributed to two systems with luminance signals Y1 and Y2 and color signals Pr and Pb, respectively. In this case, since the cluster operation speed is 1/2 of the high-definition rate, the real-time processing is performed at the high-definition rate by parallel calculation.

In FIG. 14, K is a key signal. The cluster is divided into four Y1 processing, Y2 processing, Pr processing, and Pb processing, and the programmable arithmetic unit 5 is used for Y1 processing.
(1) to 5 (3) are used, and the arithmetic unit 5 is used for Y2 processing.
(4) to 5 (6) are used, and 5 (7) to
5 (9) is used, and 5 (10) to 5 (1
2) is used.

In Y1 processing, 5 (1) is a multiplier, 5
(2) is programmed in the subtractor and multiplier, and 5 (3) is programmed in the adder. By the network 4 (not shown),
5 (1) is supplied with K and A-Y1, 5 (2) is supplied with K and B-Y1, and 5 (3) is supplied with respective operation outputs of 5 (1) and 5 (2). Supplied. That is, 5
(1) derives A-Y1 when K = 1, and 5 (2) K
When = 0, B-Y1 is derived, and 5 (3) adds and combines the operation outputs of 5 (1) and 5 (2). by this,
A-Y1 and B-Y1 key mixing signals are obtained.

In Y2 processing, 5 (4) is a multiplier, 5
(5) is programmed in the subtractor and multiplier, and 5 (6) is programmed in the adder. By the network 4 (not shown),
5 (4) is supplied with K and A-Y2, 5 (5) is supplied with K and B-Y2, and 5 (6) is supplied with respective operation outputs of 5 (4) and 5 (5). Supplied. That is, 5
(4) derives A-Y2 when K = 1, and 5 (5) K
When = 0, B-Y2 is derived, and 5 (6) adds and combines the operation outputs of 5 (4) and 5 (5). by this,
Key mixing signals of A-Y2 and B-Y2 are obtained.

In Pr processing, 5 (7) is a multiplier, 5
(8) is programmed in the subtractor and multiplier, and 5 (9) is programmed in the adder. By the network 4 (not shown),
5 (7) is supplied with K and A-Pr, 5 (8) is supplied with K and B-Pr, and 5 (9) is supplied with respective operation outputs of 5 (7) and 5 (8). Supplied. That is, 5
(7) derives A-Pr when K = 1, and 5 (8) K
When = 0, B-Pr is derived, and 5 (9) adds and combines the arithmetic outputs of 5 (7) and 5 (8). by this,
A key mixing signal of A-Pr and B-Pr is obtained.

In Pb processing, 5 (10) is a multiplier,
5 (11) is programmed in the subtractor and multiplier, and 5 (12) is programmed in the adder. The network 4 (not shown) supplies K and A-Pb to 5 (10).
K and B-Pb are supplied to (11), and the operation outputs of 5 (10) and 5 (11) are supplied to 5 (12). That is, 5 (10) derives A-Pb when K = 1, and 5 (11) derives B-Pb when K = 0, 5
In (12), the arithmetic outputs of 5 (10) and 5 (11) are added and combined. As a result, A-Pb and B-Pb key mixing signals are obtained.

FIG. 15 shows a functional configuration when key mixing is performed by one cluster for two NTSC digital video signals A and B. in this case,
Since the signal rate is as low as 1/4 with respect to the cluster operation speed, it is possible to collectively process the luminance signal and the color signal.

In FIG. 15, three programmable arithmetic units 5 (1) to 5 (3) are used in the cluster, and 5
(1) is a multiplier, 5 (2) is a subtractor and a multiplier, 5
(3) is programmed into the adder. Network 4 (not shown) provides 5 (1) with K and A, 5 (2) with K and B, and 5 (3) with 5
The respective calculation outputs of (1) and 5 (2) are supplied. That is, 5 (1) derives A when K = 1, and 5 (2) K
B is derived when = 0, and 5 (3) is 5 (1) and 5
The respective operation outputs of (2) are added and combined. by this,
A and B key mixing signals are obtained.

FIG. 16 shows a functional configuration in the case where a chroma key is generated by one cluster for the color signals Pr and Pb in the high definition digital video signal.

In this case, three programmable arithmetic units 5
Using (1) to (3), Pr (4) and P (b) are supplied to 5 (1) and 5 (2) by the network 4 (not shown), and 5 (1) and 5 (2) are supplied to 5 (3). Supply each operation output of.

Both 5 (1) and 5 (2) have the same structure,
P input by internal MPY 15 (1), 15 (2)
After multiplying r and Pb by a coefficient and amplifying, ALU13 (1)
Then, both are added to generate a chroma signal according to the table program stored in the data memory 9. 5 (3) adds the chroma signals obtained by 5 (1) and 5 (2) in the internal ALU 13 (1) and generates a chroma key signal according to the table program stored in the data memory 9.

This functional configuration is also applicable to the case where the chroma key is generated by one cluster for the color signals CR and CB in the NTSC digital video signal. The functional block diagram is omitted. FIG. 17 shows a part of a matrix functional configuration for synthesizing and outputting RGB of a high-definition digital video signal into three systems in one cluster.

Since the high-definition system has a high data rate, it is necessary to calculate RGB independently. In this case, the six programmable arithmetic units 5 (1)-
5 (6) is used. 5 (1), 5 (3), 5 (5) is 2
The inputs are amplified by MPYs 15 (1) and 15 (2), respectively, and further added and output by ALU 13 (1). 5
For (2), 5 (4), and 5 (6), one input is MPY15
Amplification is performed in (1), and the other input is added and output in the ALU 13 (1).

That is, R and G are added by 5 (1), and B is added by 5 (2) to output the first system OUT.
Sent to 1. R (G) is added by 5 (3), B is further added by 5 (4), and the result is sent to the second system OUT2. 5 (5) adds R and G, and then 5
In (6), B is added and sent to the third system OUT3. Note that the circuit of FIG. 17 carries out processing at half the data rate of the high-definition system, and in reality another circuit having the same configuration as the circuit of FIG. 17 is required.

On the other hand, since the data rate is low in the NTSC system, RGB can be collectively processed.
FIG. 18 shows the functional configuration, and the RGB signals are supplied to the arithmetic units 5 (1) and 5 (2). In 5 (1), RGB inputs are distributed to two systems, and MPY1
ALU13 after amplification with 5 (1) and 15 (2)
The constants are added in (1) and 13 (2) to become the outputs of the first and second systems OUT1 and OUT2. At 5 (2), the RGB inputs are amplified by MPY15 (1) and then A
A constant is added by LU13 (1) and the third system OUT3
Is output.

As is clear from the above application, high-speed and high-performance arithmetic processing is realized for one cluster, and the degree of freedom for function change and system change is improved, so that not only the conventional NTSC system but also high-definition It is possible to correspond to the system.

It is needless to say that the above specific examples do not limit the present invention, and that various modifications may be made without departing from the scope of the present invention.

[0077]

As described above, according to the present invention, it is possible to realize high-speed and high-level arithmetic processing, and to improve the degree of freedom in changing functions and changing systems, which makes it possible to use a high-definition system. A video signal processing device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration as an embodiment of a digital video signal processing device according to the present invention.

FIG. 2 is a block diagram showing a specific configuration of a cluster according to the embodiment.

FIG. 3 is a block diagram showing a specific configuration of a programmable arithmetic unit of the embodiment.

FIG. 4 is a block diagram showing a specific configuration of the DSP unit according to the embodiment.

FIG. 5 is a block diagram showing a specific configuration of an ALU of the same embodiment.

FIG. 6 is a block diagram showing a specific configuration of an AU of the same embodiment.

FIG. 7 is a block diagram showing a specific configuration of MPY of the same embodiment.

FIG. 8 is a block diagram showing a specific configuration of a data memory I / O of the same embodiment.

FIG. 9 is a conceptual diagram showing a conceptual configuration of a program memory and a sequencer of the same embodiment.

FIG. 10 is a diagram showing a data format of a standard transfer mode in the DPS unit of the embodiment.

FIG. 11 is a diagram showing a data format of an extended transfer mode in the DPS unit of the same embodiment.

FIG. 12 is a functional configuration diagram for explaining the variable pipeline structure of the embodiment.

FIG. 13 is a block diagram showing a hardware configuration for performing a debugging process of the embodiment.

FIG. 14 is a block diagram showing a high-vision key mixing function configuration as an application of the embodiment.

FIG. 15 is NTSC as an application of the embodiment.
FIG. 3 is a block diagram showing the configuration of a key mixing function of the method.

FIG. 16 is a block diagram showing the configuration of a high-definition chroma key generation function as an application of the embodiment.

FIG. 17 is a block diagram showing a high-definition RGB matrix functional configuration as an application of the embodiment.

FIG. 18 is NTSC as an application of the embodiment.
FIG. 3 is a block diagram showing a functional RGB matrix functional configuration.

[Explanation of symbols]

1 (1) to 1 (n) ... Signal processing cluster, 2 ... LAN,
3 ... Host computer, 4 ... Network, 5 (1)
5 (16) ... Programmable arithmetic unit (PU), 6 ... Host controller, 7 ... DSP unit, 8 ... Program memory, 9 ... Data memory, 10 (1), 10 (2)
Input processing unit, 11 Selector, 12 Output processing unit, 1
3 (1), 13 (2) ... Arithmetic logic unit (ALU), 1
4 (1), 14 (2) ... Address operation unit (AU), 15
(1), 15 (2) ... MPY (multiplier), 16 (1),
16 (2) ... variable delay, 17 ... data memory I /
O, 18 ... Internal bus, 19 ... Host I / O, 20 ... Sequencer.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hidetaka Saito 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa Inside the Komu factory of Toshiba Corporation (72) Inventor Ryuichiro Tomita Toshiba, Komukai-shi, Kawasaki-shi, Kanagawa Town No. 1 Incorporation company Toshiba Komukai factory (72) Inventor Nobuyuki Yagi 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the Broadcasting Technology Research Institute of Japan Broadcasting Corporation (72) Kazuo Fukui Kinichi Setagaya-ku, Tokyo Broadcasting Technology Research Institute, Japan Broadcasting Corporation (72) Inventor, Kazumasa Enami 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Broadcasting Technology Research Institute, Japan Broadcasting Association

Claims (6)

[Claims] 1. A plurality of programmable arithmetic processing units each having two input units to which a video signal is supplied, arithmetically processing a video signal input to the input unit according to a program, and deriving the result. Input units to which the output signals from the plurality of programmable calculation processing units are respectively supplied, input units to which a plurality of video signals can be supplied from the outside, and input units of the plurality of programmable calculation processing units. And a plurality of output units for deriving a final output respectively, and the signals of the respective input units can be supplied to the plurality of programmable arithmetic processing units in a programmable manner. A network unit for deriving a signal as a final output signal, and an external instruction for the programs of the plurality of programmable arithmetic processing units and the network unit. Therefore, in a digital video signal processing device comprising a host control means for controlling, and capable of externally freely setting the contents of arithmetic processing of the programmable arithmetic processing unit and the connection form of each programmable arithmetic processing unit by the network unit. The programmable arithmetic processing unit has two input units to which a video signal is supplied,
2) a plurality of operands for processing the video signal input to the input unit according to a program and deriving the result, each input unit to which each output signal from the plurality of operands is supplied, and 2 from the network unit. Each input unit capable of supplying one video signal, each output unit corresponding to each of the input units of the plurality of operands, and one output unit for deriving a final output. A signal that can be supplied to the plurality of operands and derives one of the input signals as a final output signal; and a program that controls the programs of the plurality of operands and the selector according to an instruction from the host control means. A control means, and the operation contents of the operand and each operation by the selector. Constructed a command of connection form so as to be set freely from the outside through the host control means, the digital video signal processing apparatus characterized by having half the operating speed of the HDTV rate for at least one instruction. 2. The digital video signal processing according to claim 1, further comprising: a parallel operation processing unit for dividing the high-definition video signal into at least two systems and performing parallel operation processing on the programmable operation processing unit. apparatus. 3. The programmable arithmetic processing section adjusts a variable delay provided in one video signal input section of the operand, and a delay amount of the variable delay through the program control means, to the other video signal input section. A variable pipeline structure is provided, which includes delay amount control means for matching input timings and an output register provided in an output part of the operand and holding output data, and capable of cascade connecting arbitrary operands by the selector. The digital video signal processing device according to claim 1, which is characterized in that. 4. The program control means stores a program memory for storing a plurality of programs for each of the plurality of operands in a table, and a program of a corresponding table from the program memory based on an instruction from the host control means. 2. The digital video signal processing device according to claim 1, further comprising a sequencer for reading out and transmitting the data to a target operand. 5. The program control means includes a break point register in which an address value is stored in advance as a break point, and a comparator for comparing the address value stored in this register with the address value for the program memory of the sequencer. And a debugging processing means for stopping the operation of the sequencer and stopping all the clocks to stop the update of the output data of each operand when the comparator detects a match between the two address values. The digital video signal processing device according to claim 4. 6. The digital video signal processing apparatus according to claim 1, wherein the programmable arithmetic processing unit increases the number of bits of the input data, performs arithmetic processing, and then converts and outputs the number of bits.