JPH05267654A - Mos transistor - Google Patents

Abstract

PURPOSE:To reduce the drop in signal voltage when an operating voltage is lowered, by constituting the vicinity of the interface of a gate insulating film in a gate electrode by using semiconductor in which the concentration by conducting impurities is low. CONSTITUTION:P-type poly silicon 105 of low impurity concentration, and a gate electrode of N-type poly silicon of high impurity concentration are formed. P-type low concentration regions 102, 103 are a drain and a source, respectively. When the band of a silicon substrate 101 is flat, positive fixed charges in a gate oxide film 104 are neutralized, so that electrons are stored on the surface of a silicon substrate 101, the gate electrode surface is turned into a depletion layer, and negative accepter ions are formed. When negative charges are applied to the gate and the silicon substrate 101 surface is inverted, electrons are concentrated on the sate electrode surface. As the result, the effective thickness of the gate oxide film at the time of cut-off differs from the thickness at the time of conduction, and this difference exerts influence on a threshold voltage. That is, a high threshold voltage is obtained at the time of cut-off, and a low threshold voltage is obtained at the time of conduction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor suitable for a switching element of a semiconductor memory cell.

[0002]

2. Description of the Related Art A semiconductor memory cell (hereinafter referred to as 1T) composed of one MOS transistor and one capacitor
The cell (abbreviated as cell) has a small number of constituent elements and is easily miniaturized, and is therefore widely used in highly integrated semiconductor memories. In this 1T cell, the signal voltage output from the 1T cell is proportional to the charge / discharge voltage difference of the capacitor. Here, the charge / discharge voltage difference is V ₁ −V ₀ when the write voltages to the capacitors corresponding to binary information are V ₀ and V ₁ , respectively. For example, consider the case of an n-channel MOS transistor. In this case, normally V ₀ is 0V. V ₁ is
Threshold voltage (V _TH ) when a high potential V _H is applied to the gate voltage of the MOS transistor V _H -V _TH
Is. Therefore, in order to highly integrate the 1T cell and keep its signal voltage at a sufficiently large value, it is necessary to downsize the memory cell while keeping _VH - _VTH large.

[0003]

However, in order to reduce the size of the 1T cell, it is necessary to reduce the size of the MOS transistor which is a constituent element of the 1T cell. For that purpose, the planar size and gate of the MOS transistor are to some extent according to the proportional reduction rule. It is necessary to reduce the insulator film thickness and the operating voltage. Therefore, in the conventional 1T cell, it has been necessary to reduce the high potential V _H to some extent as the size is reduced.
On the other hand, the threshold voltage V _TH of the MOS transistor needs to be maintained at a value of about 0.7 V or higher because it is necessary to hold the charge accumulated in the capacitor for a certain period with the gate voltage set to 0 V. Therefore, miniaturization of 1T cell is _VH- V
_TH was lowered, and eventually the signal voltage was lowered.

An object of the present invention is to provide a MOS transistor in which the plane size of the MOS transistor and the film thickness of the gate insulator are reduced to some extent according to the proportional reduction rule, and the signal voltage is not significantly lowered even when the operating voltage is lowered. ..

[0005]

According to the present invention, there is a fixed charge of the first conductivity type near the gate insulating film and the interface between the gate insulating film and the semiconductor substrate, and the gate electrode near the interface between the gate insulating film and the gate electrode is A semiconductor which does not contain a high concentration of conductive impurities, and the other gate electrodes are composed of a semiconductor which contains a high concentration of a second conductivity type impurity.
It is a conductive type MOS transistor.

[0006]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a structural sectional view for explaining a MOS transistor according to an embodiment of the present invention. 101 of the figure
Is an n-type silicon crystal substrate, 102 and 103 are p-type low resistance regions, 104 is a gate silicon oxide film, 105 is p-type low impurity concentration polysilicon, and 106 is n-type high impurity concentration polysilicon. In this embodiment, 105,1
A p-type channel MOS transistor having 06 as a gate electrode and 102 and 103 as a drain and a source is formed.

FIG. 2 shows a band structure when the gate electrode portion of the MOS transistor of FIG. 1 is cut out in a direction perpendicular to the silicon substrate 101. The figure (a) shows the interruption | blocking state which the band of the silicon substrate 101 is substantially flat, and the figure (b) shows the conduction | electrical_connection state which the surface of the silicon substrate 101 inverted. In the figure, 107 is a positive fixed charge in the gate oxide film, and 108 is a Fermi level.

When the band of the silicon substrate 101 is almost flat as shown in FIG. 2A, the silicon substrate 10 is neutralized to neutralize the positive fixed charges 107 in the gate oxide film 104.
Electrons are accumulated on the surface 1 and the surface of the gate electrode is depleted to form negative acceptor ions. In this case, the negative charges in the gate electrode do not concentrate on the surface of the gate electrode,
It is distributed in the depletion layer. Therefore, the gate electrode exerting a field effect on the surface of the silicon substrate is separated from the gate oxide film 104, which is equivalent to the effective gate oxide film 104 being thick. On the other hand, as shown in FIG. 2B, when a negative voltage is applied to the gate and the surface of the silicon substrate 101 is inverted, the p-type low resistance polysilicon 105 on the surface of the gate electrode is also inverted and electrons are concentrated on the surface of the gate electrode. .. in this case,
The effective gate oxide film thickness matches that of the actual gate oxide film 104.

The threshold voltage of the p-channel MOS transistor is V _TH = Φ _MS −2 · Φ _f − (Q _SS + Q _B ) / C _OX
It is represented by. Here, φ _MS is the work function difference between the gate electrode and the silicon substrate, φ _f is the potential difference between the Fermi level of the silicon substrate and the band center, Q _SS is the fixed charge density of the oxide film per unit area, and C _OX is the unit The gate oxide film capacitance per area, Q _B , represents the space charge per unit area of the silicon substrate surface depletion layer. In the MOS transistor of this embodiment, as described above, the effective gate oxide film thickness is different when it is cut off and when it is conductive. The difference affects the threshold voltage through C _{OX in} the third term on the right side, and makes the threshold voltage of this MOS transistor more negative when it is conducting than when it is conducting. .. As a result, this MOS transistor has a high threshold voltage which is convenient (in the negative direction) to hold the accumulated charge when cut off,
It has a low threshold voltage which is convenient for increasing | V _H −V _TH | during conduction. In this embodiment, p channel M
Since it is an OS transistor, both V _H and V _TH are negative values.

In order that the MOS transistor of this embodiment can be applied to a 1T cell, it is cut off when the gate voltage is 0 V and the gate electrode surface is depleted, and when the gate voltage is V _H , the gate electrode surface is Need to be reversed. However, these things are possible by controlling the impurity concentration of the silicon substrate surface under the gate electrode and the p-type low-concentration polysilicon 105, so that the MOS transistor of this embodiment can be easily applied to the 1T cell. Further, in order to realize the MOS transistor of this embodiment, it is necessary that an appropriate amount of positive fixed charges exist in the gate oxide film. However, this also does not pose a problem because the normal thermal silicon oxide film has a positive fixed charge of about 10 ¹¹ cm ⁻² per unit area.

[0012]

Since the properties described above do not depend on the size of the MOS transistor, the MOS transistor of the present invention is downsized to some extent according to the proportional reduction rule, and even if the operating voltage is lowered, the signal voltage is not lowered. Few.

[Brief description of drawings]

FIG. 1 is a structural cross-sectional view for explaining a MOS transistor according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing an energy band structure when a gate electrode portion of the MOS transistor of FIG. 1 is cut out in a direction perpendicular to a silicon substrate.

[Explanation of symbols]

 101 n-type silicon substrate 102 p-type low resistance region (drain) 103 p-type low resistance region (source) 104 gate silicon oxide film 105 p-type low concentration polysilicon 106 n-type high concentration polysilicon 107 fixed charge 108 Fermi level

Claims (1)

[Claims] 1. A fixed impurity of the first conductivity type is present in the vicinity of the gate insulating film and the interface between the gate insulating film and the semiconductor substrate, and a portion of the gate electrode near the interface with the gate insulating film has a high concentration of conductive impurities. 1. A first-conductivity-type MOS transistor, wherein the first-conductivity-type MOS transistor is a semiconductor that does not contain, and the other part of the gate electrode is composed of a semiconductor containing a high-concentration second-conductivity-type impurity.