JPH05267579A - Input protection network of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent an input wiring and semiconductor substrate from short- circuiting due to heat generated through the breakdown current of an input protection bipolar transistor by suppressing the localized concentration of the breakdown current, when overvoltage is applied to the input terminal of IC. CONSTITUTION:The input protection network of IC has an input protection parasitic npn transistor 30, of which collector region 31 is connected with the input wiring 12 of the IC and emitter region 32 is connected with a ground potential wiring 33 and semiconductor substrate becomes a base region, and parallel-formed collector contact region 34 and emitter contact region 35; and the collector region is formed in the manner of being longer than the emitter region and both ends of the collector region extending in the longitudinal direction are formed in the manner of protruding more than those of the emitter region extending in the same direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input protection circuit for a semiconductor integrated circuit, and more particularly to the structure of an input protection bipolar transistor.

[0002]

2. Description of the Related Art Generally, a semiconductor memory device or the like is provided with an input protection circuit for protecting a gate insulating film of an input circuit from being destroyed when a surge voltage is applied to an external input terminal. FIG. 3 shows an example of an input protection circuit provided corresponding to an address input terminal and an input / output terminal in a conventional LSI memory.

Here, 11 is an input pad connected to an input terminal, 12 is an input wiring between the input pad 11 and an input circuit (not shown), and 13 is formed in the middle of the input wiring 12. It is the input resistance. Reference numeral 14 is a parasitic bipolar transistor for input protection formed between the input wiring 12 and the ground potential node and having the semiconductor substrate as a base region. In this case, if the semiconductor substrate is a p-type, the bipolar transistor 14 is an npn transistor, its collector region is connected to the input wiring 12, its emitter region is connected to a ground potential node, and the semiconductor substrate is ground potential. Is given. On the other hand, if the semiconductor substrate is n-type, the bipolar transistor is p-type.
It is an np transistor (not shown), the emitter region thereof is connected to the input wiring 12, and the collector region thereof is connected to the ground potential node.

Here, the operation of the npn transistor 14 for input protection shown in FIG. 3 will be described. When an excessive voltage such as a surge voltage is applied to the input pad 11,
A breakdown occurs at the pn junction of the npn transistor 14, and a large current flows to the ground potential through the semiconductor substrate. At this time, the substrate potential rises due to the voltage drop due to the resistance component of the semiconductor substrate, and the base potential of the npn transistor 14 also rises. As a result, the npn transistor 1
4 is turned on, and its amplifying action causes a large current to flow to the ground potential. Therefore, the excessive voltage is not directly applied to the gate of the MOS transistor (not shown) of the input circuit, and the reliability of the LSI memory against electrostatic breakdown is improved. 4 and 5 show an example of a plane pattern and a sectional structure of the npn transistor 14 for input protection shown in FIG.

Here, 20 is a p-type semiconductor substrate, 21 is a collector region (n + impurity region), 22 is an emitter region (n + impurity region), 23 is a field oxide film, 24 is an insulating film on the substrate, 25 Is a pad wiring (corresponding to the input wiring 12 in FIG. 3) contacting the collector region 21 through a contact hole opened in the insulating film 24, and 26 is a contact region between the collector region 21 and the pad wiring 25 (collector). Contact regions) and 27 are ground potential wirings that are in contact with the emitter region 22 through contact holes formed in the insulating film 24,
Reference numeral 28 denotes a contact region (emitter contact region) between the emitter region 22 and the ground potential wiring 27. In addition, 11 is an input pad and 13 is an input resistor.

An electrostatic breakdown (ESD) evaluation test is one of the reliability tests for LSI memories (large-scale integrated circuits). In this test, the internal circuit of the memory is evaluated by modeling the case where a charged person touches the external input terminal of the memory.

FIG. 5 shows an example of a test apparatus for evaluating electrostatic breakdown of an LSI device. When the evaluation test of the LSI device 30 on the product level is performed using this apparatus, for example, in the US MIL standard, the capacitor C is 100 pF,
The DC power supply voltage E is ± 2000 V, the resistance R is 1.5 KΩ, and the voltage E is applied between any two of the pins (external terminals) of the LSI device 30.

By the way, as one of the examples in which the conventional LSI memory is defective when subjected to the electrostatic breakdown evaluation test as described above, the pad wiring 25 and the semiconductor substrate 20.
There is a short circuit with. As a result of observing with a scanning electron microscope (SEM), the electrostatic breakdown failure as described above is n
When an excessive voltage is applied to the pn junction of the pn transistor 14, extremely high heat is generated in the pn junction, and when this heat is higher than the melting point of the pad wiring (usually aluminum wiring) 25, It is considered that this is because the pad wiring 25 melts and flows out along the path of the current flowing through the pn junction, and the collector region 21 and the emitter region 22 are short-circuited. Particularly, the edge portion of the collector region 21 where the breakdown of the pn junction portion is likely to occur and the edge portion of the emitter contact region 28 are very close to each other, and the collector region 2 of the pad wiring 25 is the same.
It can be pointed out that a large amount of heat is generated due to the concentration of the current in the portion close to the edge portion of 1.

[0009]

As described above, in the conventional input protection circuit of the semiconductor integrated circuit, when an excessive voltage is applied to the input terminal, breakdown occurs at the pn junction of the bipolar transistor for input protection. When a large current flows through the semiconductor substrate to the ground potential due to the generation,
There is a problem that the input wiring is melted and flows out due to heat generated by locally concentrating the electric current, so that the input wiring and the semiconductor substrate are short-circuited and a defect may occur in the electrostatic breakdown evaluation test.

The present invention has been made to solve the above problems, and when an excessive voltage is applied to the input terminal, a breakdown occurs at the pn junction of the bipolar transistor for input protection, resulting in a large current. When the current flows to the ground potential through the semiconductor substrate, the current is suppressed from locally concentrating, and the heat generated by this current prevents the input wiring and the semiconductor substrate from being short-circuited. It is an object of the present invention to provide an input protection circuit for a semiconductor integrated circuit that can reduce the number of defects that occur.

[0011]

An input protection circuit for a semiconductor integrated circuit according to the present invention includes a first impurity region of a second conductivity type and a first impurity region of a second conductivity type selectively formed in a surface layer portion of a semiconductor substrate of the first conductivity type. A semiconductor substrate having two impurity regions, the first impurity region is connected to an input wiring connecting an input terminal of a semiconductor integrated circuit and an input circuit, and the second impurity region is connected to a ground potential wiring. A base bipolar region for input protection, a first contact region where the input wiring contacts the first impurity region, and a first contact region formed in parallel with the first contact region, and the ground potential connection And a second contact region in contact with the second impurity region, wherein the first impurity region is formed longer than the second impurity region and the first impurity region is formed. Both end portions of the longitudinal direction are formed so as to protrude from both end portions in the length direction of the second impurity region or the second contact region is first
Is formed longer than the contact region, and a distance between one end of the first contact region in the length direction and one end of the first impurity region in the length direction is equal to one end of the first contact region in the width direction. It is characterized in that it is set to be longer than a distance from one end of the first impurity region in the width direction.

[0012]

The first impurity region is formed so that both ends thereof in the lengthwise direction project more than both ends of the second impurity region in the lengthwise direction.
The structure is such that the edge portion of the contact region of is not close to. Therefore, when an excessive voltage is applied to the input terminal, a large current flows to the ground potential through the semiconductor substrate due to breakdown at the pn junction of the input protection transistor. It flows in the substrate region between the two impurity regions evenly. That is, it is possible to suppress local concentration of the current, prevent the input wiring from being melted and short-circuited with the semiconductor substrate due to the heat generated by the current, and reduce the defects generated in the electrostatic breakdown evaluation test. It is possible.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows an LSI according to the first embodiment of the present invention.
N for input protection used in the memory input protection circuit
An example of the plane pattern of a pn transistor is shown.

The circuit structure of the input protection circuit of this embodiment is as described above with reference to FIG.
The sectional structure of the npn transistor for input protection used in this input protection circuit is as described above with reference to FIG. 5, for example, and the plane pattern of the npn transistor for input protection is as described below. Has been formed.

In FIG. 1, 11 is an input pad, 12 is an input wiring (usually an aluminum wiring), 13 is an input resistance, and 30 is a region in which an npn transistor for input protection is formed. Reference numerals 31 and 32 denote a second impurity type (n + type in this example) first impurity region and a second impurity type second impurity type (n + type in this example) selectively formed in the surface layer portion of the first conductive type (p type in this example) semiconductor substrate. The first impurity region 31 is an impurity region.
Is a collector region and the second impurity region 32 is an emitter region, and a parasitic npn transistor for input protection in which the semiconductor substrate serves as a base region is formed. Between the collector region 31 and the emitter region 32, a field oxide film for element isolation, which is selectively formed in the surface layer portion of the semiconductor substrate, is provided. The collector region 31 is connected to the input wiring 12 that connects the input pad 11 and an input circuit (not shown), and the emitter region 32 is connected to the ground potential wiring 33. Reference numeral 34 denotes a first contact region (collector contact region) in which the input wiring 12 contacts the collector region 31 through a contact hole formed in an insulating film on a semiconductor substrate, and 35 is formed in parallel with the collector contact region 34. The ground potential wiring 33 is a second contact region (emitter contact region) in contact with the emitter region 32 through a contact hole opened in an insulating film on a semiconductor substrate.

In this example, the collector region 31
Is formed to be longer than the length L2 of the emitter region 32, and both ends of the collector region 31 in the length direction are formed to project from both ends of the emitter region 32 in the length direction. Therefore, the edge portion of the collector contact region 34 and the edge portion of the emitter contact region 35 do not come close to each other.

According to the first embodiment described above, the collector region 3
1 is formed so that both ends in the length direction of 1 project more than both ends in the length direction of the emitter region 32, and the edge part of the collector contact region 34 and the edge part of the emitter contact region 35 are not close to each other. Therefore, when an excessive voltage is applied to the input pad 11, when a large current flows to the ground potential through the semiconductor substrate due to breakdown occurring at the pn junction of the npn transistor for input protection, the current is The substrate region between the collector region 31 and the emitter region 32 flows on average. That is, it is possible to suppress local concentration of the current, prevent the input wiring 11 from being melted and short-circuited with the semiconductor substrate due to the heat generated by the current, and reduce the defects generated in the electrostatic breakdown evaluation test. Is possible. FIG. 2 shows an example of a plane pattern of an npn transistor for input protection used in the input protection circuit of the LSI memory according to the second embodiment of the present invention.

In the second embodiment, the length L3 of the emitter contact region 35 is formed longer than the length L4 of the collector contact region 34 and the length of the collector contact region 34 is longer than that in the first embodiment. A distance d2 between one end in the direction and one end in the length direction of the collector region 31 is set to be longer than a distance d1 between one end in the width direction of the collector contact region 34 and one end in the width direction of the collector region 31 ( For example, d2 = 2 × d1).

Also in the second embodiment, as in the first embodiment, when an excessive voltage is applied to the input pad 11, breakdown occurs at the pn junction of the npn transistor for input protection. When a large current flows to the ground potential through the semiconductor substrate, the current is suppressed from locally concentrating, the input wiring 11 is prevented from being melted and short-circuited with the semiconductor substrate due to the heat generated by this current, and electrostatic breakdown is caused. It is possible to reduce defects that occur in the evaluation test.

[0020]

As described above, according to the present invention, when an excessive voltage is applied to the input terminal, a breakdown occurs at the pn junction of the bipolar transistor for input protection, so that a large current flows through the semiconductor substrate. Suppresses local concentration of current when flowing to the ground potential, prevents short circuit between input wiring and semiconductor substrate due to heat generated by this current, and reduces defects generated in electrostatic breakdown evaluation test Thus, it is possible to realize an input protection circuit for a semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a plane pattern of an npn transistor for input protection used in an input protection circuit of an LSI memory according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a plane pattern of an npn transistor for input protection used in an input protection circuit of an LSI memory according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of an input protection circuit provided in a conventional LSI memory.

FIG. 4 is a diagram showing an example of a plane pattern of an npn transistor for input protection shown in FIG.

FIG. 5 is a diagram showing an example of a cross-sectional structure of an npn transistor for input protection in FIG.

FIG. 6 is a diagram showing an example of a test apparatus for evaluating electrostatic breakdown of an LSI device.

[Explanation of symbols]

11 ... Input pad, 12 ... Input wiring, 30 ... Npn transistor formation region, 31 ... Collector region, 32 ... Emitter region, 33 ... Ground potential wiring, 34 ... Collector contact region, 35 ... Emitter contact region.

Claims (2)

[Claims] 1. A semiconductor device having a first impurity region and a second impurity region of a second conductivity type selectively formed in a surface layer portion of a semiconductor substrate of a first conductivity type, wherein the first impurity region is a semiconductor. A parasitic bipolar transistor for input protection, which is connected to an input wiring connecting an input terminal of the integrated circuit and the input circuit, the second impurity region is connected to a ground potential wiring, and the semiconductor substrate serves as a base region; An input wiring is formed in parallel with the first contact region, which contacts the first impurity region, and a second contact region, in which the ground potential wiring is in contact with the second impurity region.
Contact region, the first impurity region is formed longer than the second impurity region, and both ends in the length direction of the first impurity region are formed in the length direction of the second impurity region. An input protection circuit for a semiconductor integrated circuit, wherein the input protection circuit is formed so as to protrude from both ends of the. 2. A semiconductor substrate having a first conductivity type semiconductor substrate and a second conductivity type first impurity region and a second impurity region selectively formed in a surface layer portion of the semiconductor substrate, wherein the first impurity region is a semiconductor. A parasitic bipolar transistor for input protection, which is connected to an input wiring connecting an input terminal of the integrated circuit and the input circuit, the second impurity region is connected to a ground potential wiring, and the semiconductor substrate serves as a base region; An input wiring is formed in parallel with a first contact region contacting the first impurity region, and a second contact wiring is formed in parallel with the first contact region and the ground potential connecting wiring is in contact with the second impurity region. A contact region, the second contact region is formed longer than the first contact region, and one end of the first contact region in the length direction and the length of the first impurity region. The input to the semiconductor integrated circuit is characterized in that the distance from one end in the direction is set to be longer than the distance between one end in the width direction of the first contact region and one end in the width direction of the first impurity region. Protection circuit.