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JPH05267480A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH05267480A
JPH05267480A JP4094796A JP9479692A JPH05267480A JP H05267480 A JPH05267480 A JP H05267480A JP 4094796 A JP4094796 A JP 4094796A JP 9479692 A JP9479692 A JP 9479692A JP H05267480 A JPH05267480 A JP H05267480A
Authority
JP
Japan
Prior art keywords
flow rate
teos
film
interlayer insulating
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4094796A
Other languages
Japanese (ja)
Inventor
Kimihiko Yamashita
公彦 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP4094796A priority Critical patent/JPH05267480A/en
Publication of JPH05267480A publication Critical patent/JPH05267480A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To prevent detrimental affect on device properties by reducing an amount of carbon atom taken into a silicon oxide film when a silicon oxide film is formed by plasma CVD method using organic oxysilane such as TEOS as a main material. CONSTITUTION:A silicon substrate 26 is arranged on a lower electrode 23 and heated by a lamp 22. Reaction gas is supplied through a gas supply port 29 and a high frequency voltage is applied between both electrodes 23, 24 from a high frequency power supply 28. Thereby, reaction gas reacts and a BPSG film or a PSG film is deposited on the silicon substrate 26. Conditions of plasma CVD are; a pressure inside a CVD reaction chamber 21 of 6.5Torr, a substrate temperature of 300 to 450 deg.C, a power of the high frequency power supply 28 of 100 to 500W. The BPSG film is deposited supplying TEOS kept at 40 deg.C together with oxygen, TMP and TMB as a reaction gas from a gas supply port 29 to the reaction chamber 21 while making helium gas flow. Ratio of O2 flow rate/TEOS flow rate is 2.0 or above.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は層間絶縁膜としてシリコ
ン酸化膜を有する半導体装置と、そのシリコン酸化膜層
間絶縁膜をプラズマCVD法により堆積する製造方法に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a silicon oxide film as an interlayer insulating film, and a manufacturing method for depositing the silicon oxide film interlayer insulating film by a plasma CVD method.

【0002】[0002]

【従来の技術】半導体装置の層間絶縁膜としてプラズマ
CVD法によりTEOS(テトラエチルオルソシリケー
ト)を主成分とする方法が用いられている。この方法に
より形成したシリコン酸化膜は、シランを主原料として
常圧CVD法により形成したシリコン酸化膜よりもステ
ップカバレッジが優れており、またTEOSを主原料と
して常圧CVD法により形成したシリコン酸化膜よりも
膜質が安定しているという利点を備えている。
2. Description of the Related Art A method using TEOS (tetraethyl orthosilicate) as a main component by a plasma CVD method is used as an interlayer insulating film of a semiconductor device. The silicon oxide film formed by this method has better step coverage than the silicon oxide film formed by the atmospheric pressure CVD method using silane as the main raw material, and the silicon oxide film formed by the atmospheric pressure CVD method using TEOS as the main raw material. It has the advantage of stable film quality.

【0003】MOS型半導体装置のゲート配線(ポリシ
リコン又はポリサイドなど)と第1層目メタル配線との
間の層間絶縁膜としてBPSG膜やPSG膜などのシリ
コン酸化膜が広く用いられており、その層間絶縁膜とし
てステップカバレッジがよくリフロー後の平坦度を向上
させる目的でTEOSを主原料としたプラズマCVD法
が採用されている。しかし、TEOSを主原料としてプ
ラズマCVD法で形成されたシリコン酸化膜は、シリコ
ン酸化膜形成の過程で発生する有機成分がシリコン酸化
膜中に取り込まれる傾向が強い。現在主流となっている
絶縁膜形成材料であるシラン(SiH4)は、その分子
構造に有機成分を含んでおらず、したがってシランを主
原料として形成したシリコン酸化膜には炭素は含有され
ない。
A silicon oxide film such as a BPSG film or a PSG film is widely used as an interlayer insulating film between the gate wiring (polysilicon or polycide) of the MOS type semiconductor device and the first layer metal wiring. As an interlayer insulating film, a plasma CVD method using TEOS as a main material is adopted for the purpose of providing good step coverage and improving flatness after reflow. However, in the silicon oxide film formed by the plasma CVD method using TEOS as a main raw material, the organic components generated in the process of forming the silicon oxide film have a strong tendency to be taken into the silicon oxide film. Silane (SiH 4 ) which is a mainstream insulating film forming material at present does not contain an organic component in its molecular structure. Therefore, carbon is not contained in a silicon oxide film formed by using silane as a main raw material.

【0004】TEOSを主原料としてプラズマCVD法
により形成したシリコン酸化膜をメタル配線とメタル配
線の間の層間絶縁膜として利用する場合はシリコン酸化
膜中に取り込まれた炭素原子は安定であり、半導体装置
の特性に悪影響を与えることはない。しかし、そのシリ
コン酸化膜をゲート配線とメタル配線間の層間絶縁膜に
用いた場合、通常、CVD膜形成後に平坦化と注入不純
物の活性化を目的とした熱処理(リフロー工程)が行な
われるので、TEOSを原料として形成されたシリコン
酸化膜中に取り込まれた炭素原子がその熱処理により半
導体基板中に拡散し、デバイス特性に悪影響を与える。
When a silicon oxide film formed by a plasma CVD method using TEOS as a main material is used as an interlayer insulating film between metal wirings, carbon atoms taken in the silicon oxide film are stable and the semiconductor It does not adversely affect the characteristics of the device. However, when the silicon oxide film is used as an interlayer insulating film between the gate wiring and the metal wiring, a heat treatment (reflow step) is usually performed after the CVD film for the purpose of planarization and activation of implanted impurities. The carbon atoms taken into the silicon oxide film formed from TEOS as a raw material diffuse into the semiconductor substrate due to the heat treatment, which adversely affects the device characteristics.

【0005】そこで、プラズマCVD法によりTEOS
を主原料として形成されるシリコン酸化膜中に炭素など
の不純物が取り込まれるのを防ぐためにいくつかの方法
が提案されている。例えば、TEOSを窒素で通気して
CVD装置に導くことにより膜中に取り込まれる炭素量
を減らす方法(特開平1−238024号公報参照)、
TEOSを主原料として生成したシリコン酸化膜をオゾ
ン雰囲気中又は酸素プラズマ中でアニール処理すること
により膜中の不純物を減少させる方法(特開平3−41
731号公報参照)、シリコン酸化膜を酸素プラズマ又
は酸素ラジカルで処理することにより不純物を減少させ
てリーク電流を低減する方法(特開平2−219232
号公報参照)、TEOSに水素又は水蒸気を混合するこ
とにより酸化膜に取り込まれる炭素量を減らす方法(特
開平2−285636号公報参照)などである。
Therefore, TEOS is formed by the plasma CVD method.
Several methods have been proposed in order to prevent impurities such as carbon from being incorporated into a silicon oxide film formed by using as a main material. For example, a method of reducing the amount of carbon taken into the film by introducing TEOS into the CVD apparatus by aeration with nitrogen (see Japanese Patent Laid-Open No. 1-238024),
A method for reducing impurities in a film by annealing a silicon oxide film formed using TEOS as a main material in an ozone atmosphere or oxygen plasma (Japanese Patent Laid-Open No. 3-41).
No. 731232), a method of reducing impurities by reducing impurities by treating a silicon oxide film with oxygen plasma or oxygen radicals (Japanese Patent Laid-Open No. 2-219232).
(See Japanese Patent Laid-Open No. 2-285636), and a method of reducing the amount of carbon taken into the oxide film by mixing hydrogen or water vapor with TEOS (see Japanese Patent Laid-Open No. 2-285636).

【0006】[0006]

【発明が解決しようとする課題】本発明はTEOSなど
の有機オキシシランを主原料としてプラズマCVD法に
よりシリコン酸化膜を形成する際に、上記の提案された
方法とは別の方法によりシリコン酸化膜に取り込まれる
炭素原子の量を少なくしてデバイス特性に悪影響を与え
ないようにする方法と、そのように形成された層間絶縁
膜をもつ半導体装置を提供することを目的とするもので
ある。
SUMMARY OF THE INVENTION The present invention provides a method of forming a silicon oxide film by a plasma CVD method using an organic oxysilane such as TEOS as a main raw material. It is an object of the present invention to provide a method for reducing the amount of carbon atoms taken in so as not to adversely affect device characteristics, and a semiconductor device having an interlayer insulating film thus formed.

【0007】[0007]

【課題を解決するための手段】本発明の半導体装置で
は、メタル配線の下に形成される層間絶縁膜として有機
オキシシランを主成分としプラズマCVD法により堆積
された炭素含有量の少ないシリコン酸化膜が用いられて
いる。好ましい態様では、その層間絶縁膜はゲート配線
とメタル配線との間の層間絶縁膜である。本発明の製造
方法では、プラズマCVD法により半導体装置の層間絶
縁膜を堆積する際に、主原料として有機オキシシランを
用い、酸素流量と有機オキシシラン流量との比を、有機
オキシシランを通気ガス流量で表わしたときの流量比と
してO2/(有機オキシシラン)を2.0以上とする。
In the semiconductor device of the present invention, a silicon oxide film containing a small amount of carbon and containing organic oxysilane as a main component and deposited by plasma CVD is used as an interlayer insulating film formed under a metal wiring. It is used. In a preferred mode, the interlayer insulating film is an interlayer insulating film between the gate wiring and the metal wiring. In the manufacturing method of the present invention, when depositing the interlayer insulating film of the semiconductor device by the plasma CVD method, organic oxysilane is used as the main raw material, and the ratio of the oxygen flow rate to the organic oxysilane flow rate is expressed by the ventilation gas flow rate of the organic oxysilane. As a flow rate ratio at this time, O 2 / (organooxysilane) is set to 2.0 or more.

【0008】プラズマCVD法によるシリコン酸化膜形
成の主原料としての有機オキシシランは、TEOSの他
にC25Si(OC253やSi(OC374、Si
(OCH34などを用いることができる。有機オキシシ
ランを反応室へ導くには、適度に加熱した有機オキシシ
ランにヘリウムなどの不活性ガスや酸素を通気してその
通気ガスとともに導いたり、有機オキシシランを加熱し
てその蒸気を導くようにすればよい。TEOSの場合に
通気するときは、TEOSの温度を30〜50℃に設定
するのが適当である。
Organooxysilane, which is a main raw material for forming a silicon oxide film by the plasma CVD method, includes C 2 H 5 Si (OC 2 H 5 ) 3 and Si (OC 3 H 7 ) 4 Si in addition to TEOS.
(OCH 3 ) 4 or the like can be used. In order to guide the organic oxysilane to the reaction chamber, an inert gas such as helium or oxygen is passed through the appropriately heated organic oxysilane to guide the gas together with the ventilation gas, or the organic oxysilane is heated to guide the vapor. Good. When venting in the case of TEOS, it is suitable to set the temperature of TEOS to 30 to 50 ° C.

【0009】[0009]

【実施例】図1は本発明の半導体装置の一実施例を表わ
したものである。シリコン基板2にフィールド酸化膜4
により活性領域が形成され、その活性領域にはソース領
域6とドレイン領域8が不純物拡散により形成され、ソ
ース領域6とドレイン領域8の間のチャネル領域上には
ゲート酸化膜10を介してポリシリコンのゲート電極1
2が形成されている。ゲート電極12とメタル配線1
6,18との間の層間絶縁膜14としてTEOSを主成
分としプラズマCVD法により堆積された炭素含有量の
少ないシリコン酸化膜であるBPSG膜又はPSG膜が
形成されている。層間絶縁膜14にはコンタクトホール
が形成され、メタル配線16,18がそれぞれソース領
域16、ドレイン領域8と接続されている。
1 shows an embodiment of a semiconductor device of the present invention. Field oxide film 4 on silicon substrate 2
Form an active region, and a source region 6 and a drain region 8 are formed in the active region by impurity diffusion. Polysilicon is formed on the channel region between the source region 6 and the drain region 8 via a gate oxide film 10. Gate electrode 1
2 is formed. Gate electrode 12 and metal wiring 1
6 and 18, a BPSG film or a PSG film, which is a silicon oxide film containing TEOS as a main component and having a low carbon content and having a low carbon content, is formed as an interlayer insulating film 14 between the electrodes 6 and 18. Contact holes are formed in the interlayer insulating film 14, and the metal wirings 16 and 18 are connected to the source region 16 and the drain region 8, respectively.

【0010】図2は本発明の製造方法で用いるプラズマ
CVD装置を概略的に示したものである。図2で、反応
室21内にはランプ22により温度制御される接地され
た下部電極23と、反応ガスを放出するシャワーヘッド
を有し高周波印加電極を兼ねる上部電極24が配置され
ている。反応室21は排気口25から真空排気される。
下部電極23上にはシリコン酸化膜を堆積しようとする
シリコン基板26が上部電極24と対向するように配置
される。TEOSはヘリウムなどの不活性ガス又は酸素
によって通気され、その通気ガスのヘリウムや酸素とと
もにガス供給口29から反応室21へ供給される。ガス
供給口29からはTEOSを含む通気ガスの他に、酸素
と、TMP(トリメチルホスフェート;PO(OC
33)やTMB(トリメチルボレート;B(OC
33)などの不純物原料ガスも反応室21へ供給され
る。これらの反応ガスは上部電極24のシャワーヘッド
からシリコン基板26上に均一に供給され、排気口25
から排気される。上部電極24と下部電極23の間には
高周波電源28によって13.56MHzの高周波電圧
が印加される。
FIG. 2 schematically shows a plasma CVD apparatus used in the manufacturing method of the present invention. In FIG. 2, a grounded lower electrode 23 whose temperature is controlled by a lamp 22 and an upper electrode 24 having a shower head for emitting a reaction gas and also serving as a high frequency applying electrode are arranged in the reaction chamber 21. The reaction chamber 21 is evacuated from the exhaust port 25.
A silicon substrate 26 on which a silicon oxide film is to be deposited is arranged on the lower electrode 23 so as to face the upper electrode 24. TEOS is aerated with an inert gas such as helium or oxygen, and is supplied to the reaction chamber 21 from the gas supply port 29 together with helium and oxygen as the aeration gas. From the gas supply port 29, oxygen and TMP (trimethyl phosphate; PO (OC
H 3 ) 3 ) and TMB (trimethylborate; B (OC
Impurity source gas such as H 3 ) 3 ) is also supplied to the reaction chamber 21. These reaction gases are uniformly supplied from the shower head of the upper electrode 24 onto the silicon substrate 26, and the exhaust port 25
Exhausted from. A high frequency power supply 28 applies a high frequency voltage of 13.56 MHz between the upper electrode 24 and the lower electrode 23.

【0011】図2のCVD装置で、シリコン基板26を
下部電極23上に配置し、石英ガラス27を経てランプ
22から反応室21内に入射される光により基板26が
下地電極23を介して加熱される。ガス供給口29を経
て反応ガスが供給され、高周波電源28から両電極2
3,24間に高周波電圧が印加されることにより、反応
ガスが反応してシリコン基板6上にBPSG膜又はPS
G膜が堆積する。
In the CVD apparatus of FIG. 2, the silicon substrate 26 is placed on the lower electrode 23, and the substrate 26 is heated via the base electrode 23 by the light entering the reaction chamber 21 from the lamp 22 through the quartz glass 27. To be done. The reaction gas is supplied through the gas supply port 29, and the high frequency power supply 28 supplies the two electrodes 2 to each other.
When a high-frequency voltage is applied between 3 and 24, the reaction gas reacts and the BPSG film or PS on the silicon substrate 6.
G film is deposited.

【0012】プラズマCVDの条件として、CVD反応
室21内の圧力を2〜12Torr、例えば約6.5Torrと
し、基板温度を300〜450℃とし、高周波電源28
の電力を100〜500Wに設定する。TEOSとして
純度99.9999%のものを用い、約40℃に保温
し、ヘリウムガスで通気しながら酸素及びTMP、TM
Bとともにガス供給口29から反応室21へ供給しなが
らBPSG膜を堆積させた場合の、BPSG膜の成膜速
度とO2流量/TEOS流量比の関係を図3(A)に示
す。ここで、O2とTEOSの流量比は、TEOS流量
としては40℃に保温されたTEOSにヘリウムガスを
通気して気化させ、ヘリウムガスとともに反応室21へ
導くときのヘリウムガス流量として表わされている。図
3(A)によれば、O2流量/TEOS流量比が小さい
ほどBPSG膜の成膜速度が大きくなり、一般的には生
産性を考慮してその比が0.5〜2.0の範囲に設定され
て使用されている。しかし、そのような範囲で形成され
たBPSG膜には多量の炭素が取り込まれ、それがデバ
イス特性に悪影響を与えることがわかった。図3(B)
はBPSG膜形成時のO2流量/TEOS流量比とBP
SG膜中の炭素含有量との関係を表わしたものである。
炭素含有量はSIMS(二次イオン質量分析法)により
測定したものであり、BPSG膜成膜後リフロー工程
(920℃、窒素雰囲気、30分)を行なった試料をS
IMS分析し、BPSG膜とシリコン基板との界面に偏
析した炭素のピーク濃度を示している。また、シランを
主原料としたBPSG膜の膜中炭素濃度は約5.0×1
18原子/ccであり、これはSIMS分析のバックグ
ラウンド値とほぼ同じである。
As conditions for plasma CVD, the pressure in the CVD reaction chamber 21 is set to 2 to 12 Torr, for example, about 6.5 Torr, the substrate temperature is set to 300 to 450 ° C., and the high frequency power supply 28 is used.
Power of 100 to 500 W. Use TEOS with a purity of 99.9999%, keep it at about 40 ° C, and oxygen and TMP, TM while ventilating with helium gas.
FIG. 3A shows the relationship between the deposition rate of the BPSG film and the O 2 flow rate / TEOS flow rate ratio when the BPSG film is deposited while being supplied to the reaction chamber 21 through the gas supply port 29 together with B. Here, the flow rate ratio of O 2 and TEOS is expressed as a helium gas flow rate when TEOS is kept at 40 ° C. as a TEOS flow rate, and helium gas is aerated to vaporize the TEOS gas and lead the gas to the reaction chamber 21 together with the helium gas. ing. According to FIG. 3 (A), the smaller the O 2 flow rate / TEOS flow rate ratio is, the higher the deposition rate of the BPSG film is. It is set and used in the range. However, it has been found that a large amount of carbon is incorporated into the BPSG film formed in such a range, which adversely affects the device characteristics. Figure 3 (B)
Is the ratio of O 2 flow rate / TEOS flow rate during BPSG film formation and BP
It shows the relationship with the carbon content in the SG film.
The carbon content is measured by SIMS (secondary ion mass spectrometry), and the sample subjected to the reflow process (920 ° C., nitrogen atmosphere, 30 minutes) after forming the BPSG film is S
The peak concentration of carbon segregated at the interface between the BPSG film and the silicon substrate by IMS analysis is shown. In addition, the carbon concentration in the BPSG film made of silane as a main material is about 5.0 × 1.
0 18 atoms / cc, which is almost the same as the background value of SIMS analysis.

【0013】BPSG膜中に取り込まれた炭素のデバイ
ス特性に与える影響が最も顕著に現われるのは、CMO
SデバイスのP型拡散層の抵抗であり、取り込まれた炭
素量が多いほどP型拡散層の抵抗が高くなる傾向が見ら
れる。図3(C)はO2流量/TEOS流量比とP型拡
散層のシート抵抗値の関係を示したものである。シート
抵抗値はO2流量/TEOS流量比の増加にともない減
少していくのがわかる。
The most notable effect of the carbon incorporated in the BPSG film on the device characteristics is CMO.
It is the resistance of the P-type diffusion layer of the S device, and the resistance of the P-type diffusion layer tends to increase as the amount of carbon taken in increases. FIG. 3C shows the relationship between the O 2 flow rate / TEOS flow rate ratio and the sheet resistance value of the P-type diffusion layer. It can be seen that the sheet resistance value decreases as the O 2 flow rate / TEOS flow rate ratio increases.

【0014】図3の結果から、TEOSを主原料とする
プラズマCVDによるBPSG膜中の炭素量はO2流量
/TEOS流量比に依存し、デバイス特性に与える影響
も同様にその比に依存する。したがって、BPSG膜中
の炭素の影響を極力少なくするためには、その比をでき
るだけ高く設定する必要があり、その値は2.0以上と
するのが適当である。
From the results of FIG. 3, the amount of carbon in the BPSG film formed by plasma CVD using TEOS as a main material depends on the O 2 flow rate / TEOS flow rate ratio, and the influence on the device characteristics also depends on the ratio. Therefore, in order to reduce the influence of carbon in the BPSG film as much as possible, it is necessary to set the ratio as high as possible, and it is appropriate that the value is 2.0 or more.

【0015】実施例は主原料としてTEOSを取り上げ
ているが、有機オキシシランとしてはそれ以外にC25
Si(OC253、Si(OC374、Si(OCH
34などを用いることもでき、それらの有機オキシシラ
ンを主原料とした場合にも同様に炭素が取り込まれる傾
向があるので、それらの場合も本発明によO2流量/
(有機オキシシラン)流量比を2.0以上とすることに
より取り込まれる炭素量を少なくすることができる。
Although TEOS is taken as the main raw material in the examples, other organic oxysilanes such as C 2 H 5 are used.
Si (OC 2 H 5 ) 3 , Si (OC 3 H 7 ) 4 , Si (OCH
3) can also be used as 4, there is a tendency that the carbon is incorporated in the same manner when those organic oxysilane as a main raw material, by the present invention even if their O 2 flow /
(Organic oxysilane) By setting the flow rate ratio to be 2.0 or more, the amount of carbon taken in can be reduced.

【0016】[0016]

【発明の効果】本発明ではBPSG膜やPSG膜をTE
OSなどの有機オキシシランを主成分としてプラズマC
VD法により形成する際、O2流量/(有機オキシシラ
ン)流量比を2.0以上に設定したことにより、BPS
G膜やPSG膜などのシリコン酸化膜に取り込まれる炭
素量が減少してデバイス特性に悪影響を与えることな
く、良質の層間絶縁膜を形成することができる。この層
間絶縁膜はデバイス特性に悪影響を与えないことからゲ
ート配線とメタル配線の間の層間絶縁膜として利用する
ことができる。
According to the present invention, a BPSG film or a PSG film is formed by TE
Plasma C mainly composed of organic oxysilane such as OS
When forming by the VD method, by setting the O 2 flow rate / (organic oxysilane) flow rate ratio to 2.0 or more, BPS
It is possible to form a high-quality interlayer insulating film without reducing the amount of carbon taken into the silicon oxide film such as the G film or the PSG film and adversely affecting the device characteristics. Since this interlayer insulating film does not adversely affect the device characteristics, it can be used as an interlayer insulating film between the gate wiring and the metal wiring.

【図面の簡単な説明】[Brief description of drawings]

【図1】一実施例の半導体装置を示す断面図である。FIG. 1 is a cross-sectional view showing a semiconductor device of an embodiment.

【図2】本発明が適用されるプラズマCVD装置の一例
を概略的に示す断面図である。
FIG. 2 is a sectional view schematically showing an example of a plasma CVD apparatus to which the present invention is applied.

【図3】一実施例におけるO2流量/TEOS流量比と
成膜速度、炭素濃度、シート抵抗値の関係をそれぞれ示
す図である。
FIG. 3 is a diagram showing a relationship between an O 2 flow rate / TEOS flow rate ratio, a film forming rate, a carbon concentration, and a sheet resistance value in one example.

【符号の説明】[Explanation of symbols]

2 シリコン基板 6 ソース 8 ドレイン 10 ゲート酸化膜 12 ゲート電極 14 層間絶縁膜 16,18 メタル配線 21 CVD装置の反応室 22 温度制御用ランプ 23 下部電極 24 上部電極 26 シリコン基板 28 高周波電源 2 Silicon substrate 6 Source 8 Drain 10 Gate oxide film 12 Gate electrode 14 Interlayer insulating film 16, 18 Metal wiring 21 Reaction chamber of CVD apparatus 22 Temperature control lamp 23 Lower electrode 24 Upper electrode 26 Silicon substrate 28 High frequency power supply

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体装置のメタル配線の下に形成され
る層間絶縁膜として有機オキシシランを主成分としプラ
ズマCVD法により堆積された炭素含有量の少ないシリ
コン酸化膜が用いられていることを特徴とする半導体装
置。
1. A silicon oxide film containing organic oxysilane as a main component and having a low carbon content, which is deposited by a plasma CVD method, is used as an interlayer insulating film formed under a metal wiring of a semiconductor device. Semiconductor device.
【請求項2】 前記層間絶縁膜がゲート配線とメタル配
線との間の層間絶縁膜である請求項1に記載の半導体装
置。
2. The semiconductor device according to claim 1, wherein the interlayer insulating film is an interlayer insulating film between a gate wiring and a metal wiring.
【請求項3】 プラズマCVD法により半導体装置の層
間絶縁膜を堆積する方法において、主原料として有機オ
キシシランを用い、酸素流量と有機オキシシラン流量と
の比を、有機オキシシランを通気ガス流量で表わしたと
きの流量比としてO2/(有機オキシシラン)を2.0以
上とすることを特徴とする半導体装置の製造方法。
3. A method of depositing an interlayer insulating film of a semiconductor device by a plasma CVD method, wherein organic oxysilane is used as a main raw material, and the ratio of the oxygen flow rate to the organic oxysilane flow rate is expressed by the gas flow rate of the organic oxysilane. O 2 / (organooxysilane) is set to 2.0 or more as a flow rate ratio of the semiconductor device.
【請求項4】 前記層間絶縁膜がゲート配線とメタル配
線との間の層間絶縁膜である請求項3に記載の半導体装
置の製造方法。
4. The method of manufacturing a semiconductor device according to claim 3, wherein the interlayer insulating film is an interlayer insulating film between a gate wiring and a metal wiring.
JP4094796A 1992-03-21 1992-03-21 Semiconductor device and its manufacture Pending JPH05267480A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4094796A JPH05267480A (en) 1992-03-21 1992-03-21 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4094796A JPH05267480A (en) 1992-03-21 1992-03-21 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH05267480A true JPH05267480A (en) 1993-10-15

Family

ID=14120039

Family Applications (1)

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Country Status (1)

Country Link
JP (1) JPH05267480A (en)

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