JPH05266003A - Character processing method - Google Patents

Abstract

PURPOSE:To prevent the break of the cursor position which is due to the difference of numbers of characters caused by the conversion of characters by displaying the KANA (Japanese syllabary) data after addition of the voiced sound marks when the voiced sound mark data are inputted after the KANA data. CONSTITUTION:When the keys are pushed on a keyboard KB, the input data given from the KB are stored in a buffer KB BUFFER. If the data on a HIRAGANA (cursive form of Japanese syllabary) character 'KA' is inputted through the KB, this data varies according to the next key to be pushed. That is, if the next voiced sound mark '''' key is pushed, the data is changed to the data on 'KA'. Meanwhile the data on 'KA' is confirmed if other keys are pushed. For instance, no data is decided with input of the first key, i.e., 'Y' in a Roman character input mode for example. Then the definitive data 'YA' is obtained only when the next 'A', for example, is pushed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a character processing device for processing character data.

[0002]

2. Description of the Related Art When inputting and displaying character data, it is possible to input Roman characters or kana.
There is one that displays the character entered at the position of the cursor, moves the cursor by one digit, indicates that position as the display position of the character to be entered next, and waits for the input of the next character. ..

[0003]

However, in this case, even if the number of characters to be displayed changes after the character to be input next is converted to another character depending on the character already input, the position of the cursor is changed. Therefore, there is a problem that the display position of the converted character and the display position of the newly input character may not be continuous.

[0004]

In view of the above points, the present invention converts the consonant data and vowel data of the input alphabetic character data into corresponding kana data as kana of romanized characters in the roman character input state, The kana data to be converted is displayed without visually displaying the vowel data to be input, and in the kana input state, when kana point data is input after kana data is input, with respect to the kana data, It is an object of the present invention to provide a character processing method for controlling a display such that a dakuten is added and displayed.

[0005]

1 is a block diagram showing an embodiment of a character processing apparatus according to the present invention.

The KB is composed of a character key group for inputting a sentence on a keyboard and a function key group for realizing various functions associated with the present apparatus.

FIG. 6 shows the keyboard KB in more detail. The arrangement of the character keys is a so-called JIS keyboard with some modifications. The main change is the configuration of the shift key. That is, the keyboard KB has a hiragana shift key and a small hiragana shift key in order to enable hiragana input.

The function keys are DECIMAL
There are keys, full width keys, half width keys, romaji keys, and kana keys. Of these, the Romaji key and the Kana key are keys that determine the input mode for inputting characters, etc. from the character keys of the keyboard KB. When the Romaji key is pressed, Japanese sentences can be input in Romaji reading,
Also, by pressing the Kana key, it becomes possible to input Japanese sentences in Kana.

The DECIMAL key is a key for instructing a digital tab input, the full-width key is a key for instructing a normal size character input, and the half-width key is a key for instructing a half-size (horizontal direction) character input. (However, only specific characters such as alphanumeric characters).

When one key of the character key group and the function key group is pressed, a microprocessor CPU described later is passed through a control bus CB described later,
Give an interrupt. In addition, the code of the key pressed by the encoder provided on the keyboard KB can be known through the data bus DB described later.

The code of the key output from the encoder does not directly correspond to the character code, but is a code for discriminating each key.

From keyboard KB to microprocessor C
The interrupt given to the PU is a microprocessor CD
It can be masked by U. However, even if the keyboard KB interrupt is masked by the CPU, if the keyboard KB interrupt is unmasked by the microprocessor CPU, the KB interrupt generated when masked is not lost, and the operation of the KB interrupt works normally. And

KB BUFFER is a buffer for converting input data keyed from the keyboard KB into a character code and buffering it.

When a key on the keyboard KB is pressed, a keyboard KB input processing routine is started, and input data from the keyboard KB is stored in the buffer KB BUFFER.

Data such as characters stored in the buffer KB and BUFFER is used by reading the input data from the keyboard KB by various necessary processing routines such as an input processing routine and an editing processing routine. Since these processing routines are not directly related to the present invention, detailed description thereof will be omitted.

The details of the buffer KB BUFFER are shown in FIG.
Shown in. 21W (W: Ward, 1W-16bi
It has a capacity of t). The specific definition of each W is shown below.

All DATA stored in WORD 0 KB BUFFER LENGTH WORD 1 KB All DATA stored in KB BUFFER have completed processing of inner and semi-dakuten D
The DAT for which all the DATA stored in LENGTH WORD 2 KB BUFFER of ATA has been converted to Roman characters
The L of the DATA whose half width processing of all DATA stored in the LEGTH WORD 3 KB BUFFER of A has finished
ENGTH WORD 4 KB of all DATA stored in BUFFER, D for which DECIMAL processing has been completed
Area for storing DATA input from LENGTH WORD5 to 20 KB of ATA The first 5 W is filled with the characteristics of the data stored in the buffer KB BUFFER. Actual input data is stored after the sixth W.

Buffer KB BUFFER WORD 0
It is stored in the buffer KB BUFFER in (1 W of tsubo). The data LENGTH is entered. However, these data are not data that can be immediately processed by the various processing routines described above. For example, suppose that character data "ka" is input from the keyboard KB. However, this "ka" data changes depending on the next key pressed. That is, it is confirmed that the next time the """(voiced point) key is pressed, the data changes to" ka ", and when the other keys are pressed, the data changes to" ka ".

Further, for example, at the stage of inputting the first keystroke, for example, "Y", while inputting in the Roman character mode, it is not confirmed as data yet, and for example, only when the next keystroke is "A". It becomes the fixed "ya" data.

Further, for example, when the first keystroke, for example, "1" is input during half-width input, it is not confirmed as data yet, but is confirmed for the first time when, for example, "2" is next input. The data is "12". This is because, in this embodiment, the half-character is always treated in units of two characters.

Further, for example, when inputting with a decimal tab, the input character string is secured as a valid character only when a character for ending the decimal tab is input.

As described above, all the data defined by DATALENGTH stored in WORD0 of the buffer KB BUFFER is not always valid data.

Therefore, in order to clarify the characteristics of the data stored in the buffer KB BUFFER, the buffer KB
5W of the HEADER part of BURRERR is used.

WORD 0 of buffer KB BUFFER LENGTH of all data stored in buffer KB BUFFER WORD 1 of WORD 1 buffer of KB BUFFER LEN of data in which all of the data stored in buffer KB BUFFER is processed.
GTH KB BUFFER WORD2 Buffer KB BUFFER All the data stored in buffer BUFFER The half-voiced point and the data that has undergone the Romaji-Kana conversion process LENGTH KB BUFFER WORD3 Buffer KB BUFFER all the data stored LENGTH KB BUFFER WORD4 buffer of data that has undergone processing, Romaji-kana conversion processing, and half-width processing All of the data stored in the buffer KB BUFFER are processed by the internal dakuten-semi-dakuten processing, Roman-kana conversion processing, half-width processing, and decimal processing. Data LENGT
H. Of the data stored in the buffer KB BUFFER, the length of the data given by WORD4 of the buffer KB BUFFER is truly valid data.

In the present embodiment, the dakuten / sakudaku process, the Roman character / kana conversion process, the half width process, a part of the decimal process and the like are executed by a keyboard KB input processing routine which will be described later.
The results are stored in the buffer KB BUFFER, and various processing routines that require input data from the keyboard KB are configured to use the data resulting from the execution of the four types of processing. Therefore, other embodiments, for example,
Remove half width processing from KB processing routine
It is also possible to adopt a configuration in which various processing routines that require input data from the device perform half width processing. The same can be said for the four types of processing. If the present invention executes even one of the four kinds of processing by the KB input processing routine, the gist of the invention will not be impaired.

Buffer KB BUFFER WORD 5
The structure of the data stored in ~ 20 is as shown in FIG.

Bit0 Half-width = 1, full-width = 0 bit1 to 7 JIS CODE 1st BYTH bit8 REFRESH MEMORY Low luminance display = 1 and normal luminance display = 0. In KB BUFFER, the characters that make up the Roman alphabet = 1 and the independent characters = 0. D
ATA BUFFER, KB READ BUFFER
Within NOTICED bits 9 to 15 JIS CODE No. 2 BYTE <Note> Full-width time: JIS CODE No. YTE and JIS CODE
The JIS Kanji code (14 bits) is expressed by 2BTE. It is assumed that the FUNCTION code is also assigned to an empty area of the JIS Kanji code table.

Half-width: JIS CODE No. 1 BYTE
And JIS CODE2BYTE with JIS code (7bi
Two characters of t) are expressed.

That is, 1W width characters (normal size characters)
Express one character or two half-width characters. bit0
Use to distinguish between half-width characters and full-width characters. Full width bit1
~ 7 to JIS Kanji code first BYTE, bit9 ~ 1
The second BYTE of JIS Kanji code is stored in 5. In the case of half width, one character of 7-bit JIS CODE is assigned to bits 1 to 7, and another one character is assigned to bits 9 to 15.

Bit 8 is 1 to identify the code when it is a Roman character component, for example, "T" (a Roman character "TA" component).

KB READ BUFFER is a buffer used by various processing routines that require input data from the keyboard KB when requesting the data, and has a capacity of 21 W (1W-16 bits). The various processing routines are performed by the buffer KB READ.
DA required for WORD0 (1W) of BUFFER
Set TA LENGTH, KB BUFF to be described later
ER READ processing routine or KB BUFF
If you start the ER LOOK processing routine, KB
The requested data can be obtained from WORDs 5 to 20 of READ BUFFER. At that time, the buffer KB RE
WORD1 of AD BUFFER is actually WORD5
DATA LENGTH written in 20 is filled in. Actually, the KB BUFFER READ processing routine and the KB BUFFER LOOK processing routine are
The valid data (defined by KBBUFFER WORD4) stored in the buffer KB BUFFER will be transferred to the buffer KB READ BUFFER.

FIG. 4 shows the format of KB READ BUFFER.

In the figure, WORD 0 READ or LOOK request DATA L
ENGTH WORD 1 Actual READ or LOOK DATA
LENGTH WORD 2-4 NOT USED WORD 5-20 READ or LOOKed data In addition, the buffer KB READ BUFFER WOR
The format of the data stored in D5-20 differs from the format of the data stored in WORD5-20 of the buffer KB BUFFER only in the following points.
That is, bit8 is not used.

The CRT REFRESH MEMORY has a memory capacity of 8 × 16 W (1W-16 bits).

Memory CRT REFRESH MEMO
Codes such as characters stored in RY are patterned by the CRT controller CRT CONT described later and displayed on the CRT screen.

Memory CRT REFRESH MEMO
As shown in FIG. 3, the RY format is composed of 8 lines and 16 digits. Lines 1 to 7 are various character processing display regions and line 8 is a KB BUFFER monitor display region.
Such a memory can store codes such as characters of vertical 8 rows and horizontal 16 digits corresponding to a CRT screen described later. Memory C
The format of the data stored in the RT REFRESH MEMORY differs from the format of the data stored in the buffer KB BUFFER only in the following points. That is, when bit8 = 1, it is displayed on the CRT with low brightness, and when bit8 = 0, it is displayed on the CRT with normal brightness. This control is a CRT controller CRT
It is performed by CONT.

In addition, CRT REFRESH MEMOR
The 8th line of Y is an area for displaying the contents of the buffer KB NUFFER, and the 1st to 7th lines are areas used by various processing routines. In the present embodiment, the handling of the display from the first line to the seventh line has no direct relation to the present invention, and therefore will be omitted.

CRT CONT is a memory CRT REF
It is a CRT controller that controls the code information such as characters stored in the RESH MEMORY to be patterned and displayed on the CRT screen. A detailed view of the CRT controller CRT CONT is shown in FIG. The area surrounded by the one-dot chain line in FIG. 10 is the CRT CONT. The control circuit CRT is a memory CRT REFRESH MEM.
The address of the character code to be displayed is given to ORY and the character code is taken out. The extracted character code information is stored in the temporary storage register REG, and then the full width character generator CG, the half width character generator CGII and the half width character generator CGIII are accessed. The full width character generator CG stores full width character patterns. Bits 1 to 7 and bit 9 of the output data from the temporary storage register REG
A character is designated by 15, and R is output from the control circuit CRTC.
The ROW address of the character is designated by the OW address signal, and the horizontal row pattern of the corresponding ROW of the corresponding character is output.

Half-width character generator CGI, II
A half width character pattern is stored in. Bits 1 to 7 and bits 9 to 15 of the temporary storage register REG are input to the half-width character generators CGI and II, respectively, and the horizontal row patterns of the corresponding character patterns are output similarly to the full-width character generator CG. The selector SL selects the output data from the full-width character generator CG and the output data from the half-width character generators CGI and II.

The output of the temporary storage register REG also controls the selector SL by bit0. That is, b
Half-width character generator CGI when it0 = 1,
The output data from II is selected, and when bit0 = 0, the output data from the full width character generator CG is selected. The data output from the selected selector SL is output as serial data via the parallel-serial converter PS to the display device CRT. The data bit8 output from the temporary storage register REG is the display device CR.
It is output to the display device CRT for controlling the brightness of T.

The control circuit CRTC receives the vertical timing signal and the horizontal timing signal from the display device CRT, and successively receives the memory CRT REFRESH.
Characters are displayed on the display device CRT by changing the access address to the MEMORY and changing the ROW address signals for the full-width character generator CG and the half-width character generators CGI and II.

The CRT is a display device and is a CRT controller C.
The character information stored in the memory CRT REFRESH MEMORY by being controlled by RT CONT is displayed.

The display device CRT is a CRT controller C.
The vertical timing signal and the horizontal timing signal are sent to the RTCONT to match the timing of the CRT controller CRT CONT. Further, the display device CRT receives the VIDEO information and the brightness information from the control circuit CRTC, and outputs the VIDEO information of the specified brightness.

DATA BUFFER is a buffer that stores data used by various processing routines. It is not directly related to the present invention.

In the present embodiment, the buffer DATA B
The format of the data stored in UFFER is defined as shown in FIG.

RKCT is a Roman-Kana conversion table,
It is a conversion table for converting a Roman character string into a Kana character string. As shown in FIG. 9, Roman character strings correspond to Kana character strings.

ICT is a KB code / internal code conversion table, which is a table for converting the output data from the keyboard KB into the internal code FIG. In conversion, it should be noted that the code to be converted differs depending on the shift state and the input mode state. FIG. 7 shows the details of this table.

DHT is a dakuten-semi-dakuten table, and one code is given to the dakuten or the semi-dakuten as shown in FIG. It is a conversion table to a code system that does not give one code to the dakuten or the semi-voiced sound from the code system and includes the information of the dakuten and the semi-voiced sound in the character code.

The RAM is a random access memory and is used for temporary storage of various data. In the memory RAM,
A Roman character black FG, a half-width flag HWFG, a tesimal flag DECI MAL FG, a shift register SR, an internal code register IREG, a packing register PREG, a register DF, a register TDL, a register LEN, etc., which are used by a microprocessor CPU to be described later, are included. included.

The ROM is a control memory in which the control procedures shown in FIG. 11 and thereafter are stored.

The CPU uses a microprocessor to perform arithmetic operations and logical decisions.

Address bus AB and data bus D described later
B, control bus CB, keyboard KB, buffer KB BUFFER, memory CRT REFRE
SHMEMORY, buffer DATA BUFFER,
For the buffer KB READBUFFER, Roman character / Kana conversion table, RKCT KB code internal code conversion table ICT, memory RAM, control memory ROM,
Data can be read and written. AB
Is an address bus for transferring a signal indicating a control target. The CB applies a control signal to various control targets by a control bus. The DB transfers various types of DATA via a data bus.

The operation of this embodiment will be described based on the above configuration.

When the power is turned on, the initialization process shown in FIG. 11 is first executed. The contents of each step of this flow are shown below.

0,1 KB INT (UNTERRUR
Abbreviation of T) Put all NULL codes in MASK ON 0, 2 KB BUFFER. (Clear all to 0) 0, 3 Put all space code in CRT REFRESH MEMORY 0, 4 KB INT MASK OFF 0, 5 MAIN Processing 1 or 2 JUMP

As described above, KB IN is executed in step 0.1.
Turn on T MASK, and in step 0.2 KB BUF
Clear the FER. (Set to ALL 0) Next, in step 0.3, the memory CRT REFRESH MEMORY
Put all space codes in. K at steps 0 and 4
B INT MASK OFF, and M in steps 0 and 5.
JIMP to AIN processing 1 or 2. MAIN processing 1 or 2 shows two kinds of application examples of the present invention.

Step 0. of the above initialization processing.
At step 5, for example, the process proceeds to Main process 1 shown in FIG. 12
The contents of each step of the flow shown in are shown below.

READ request DATALENGTH is set in WORD0 of 1, 1 KB READ BUFFER.

1, 2 KB BUFFER READ processing 1, 3 KB READ BUFFER WORD 1
(DATA LEN GTH actually read) is 0
Or? 1, 4 Execution of various processes according to input data As described above, in order to read the data stored in KB BUFFER in steps 1 and 1, KB READ
Read request to DATA0 of BUFFER DATA L
Set ENGTH. KB in the next steps 1 and 2
Effective data stored in BUFFER (KB BU
FFER (specified in WORD 4) into the read buffer KB READ BUFFER. ) DATALENGTH to be transferred is the buffer KB READ BU
It is specified in WORD0 of FFER. When the transfer is completed, the data is removed from the buffer KB BUFFER.

In the next steps 1 and 3, KB BUFFER
It is checked whether or not LENGTH of the data transferred from to KB READ BUFFER is 0. If it is 0, repeat steps 1 and 2. If it is not 0, proceed to steps 1 and 4. In steps 1 and 4, various processes according to the input data are executed.

The specific contents of various processes are omitted because they are not directly related to the present invention, but there is, for example, a character input process.

FIG. 14 shows a detailed flow of the above-mentioned KB BUFFR READ processing. The details of each step are shown below.

1, 2, 1 KB MASK ON 1, 2, 2 KB BUFFER WORD 4 (DEC
After IMAL processing DATA LENGTH) From KB R
Is WORD0 of EAD BUFFER bigger?

[0064]

[Outer 1] Only 1, 2, and 5 TDL values are in D in KB BUFFER
Move ATA to KB READ BUFFER.

1, 2, 6 KB READ BUFFE
Set the value of TDL in R WORD1.

1, 2, 7 KB BUFFER WOR
The value of TDL is subtracted from the value of D0-4.

1, 2, 8 KB BUFFER WOR
The contents of D5 to 20 are all left-justified by the value of TDL.
(The head is deleted by the TDL value, and the rest is left-justified.) 1, 2, 9 DISPLAY processing (3.13) 1, 2, 10 KB INT MASK OFF As described above, in steps 1, 2, 1 KB INT MA
SIC is turned on and KB BUFF is performed in steps 1, 2 and 2.
From ER WORD4 (valid DATA LENGTH) KB FEAD BUFFER WORD0 (request DA
TA LENGTH) is larger than that.

If it is larger, the process proceeds to steps 1, 2, and 3.

If smaller, go to steps 1, 2, and 4.

KB RE is executed in steps 1, 2 and 3
Set to the value of ADBUFFER WORD0. Go to steps 1, 2, and 5.

In steps 1, 2, and 4, the TDL is set to KB BU.
Set to the value of FFER WORD0. Step 1,
Go to 2 and 5. Only K of TDL value in steps 1, 2 and 5
The data in BBUFFER is converted into KB READ BUFF
Move to ER.

KB READ B in steps 1, 2 and 6
Set the value of TDL in UFFER WORD1.

KB BUFFER in steps 1, 2, and 7
The value of TDL is subtracted from the value of WORD0-4.

KB BUFFER in steps 1, 2 and 8
The beginning of the TDL value is deleted from the DATA area and the rest is left aligned.

1, 2, 9 KB BUFFER DISP
LAY processing (3, 13) (DAT in KB BUFFER)
DISPLY A on CRT) 1, 2, 10 KB INT MASK OFF.

FIG. 15 shows a buffer KB BUFFER and a buffer K in the KB BUFFER READ processing.
It is an example of B READ BUFFER. Buffer KB
Buffer KB from BUFFER to 3-character DATA READ request Buffer from BUFFER
It can be seen that three characters are being moved with respect to READ BUFFER. HEADER of buffer KB BUFFER and buffer KB READ BUFFER
It can be seen that the part parameters also change accordingly.

The processing of MAIN1 is performed as described above.
Meanwhile, the processing of MAIN2 will be described in detail below. When the processing of MAIN2 is executed in step 0.5 of the initialization processing, each step of the flow shown in FIG. 13 is executed.
The steps of the flow are shown below.

2, 1 KB READ BUFFER
Set LOOK request DATALENGTH to WORD1.

2, 2 KB BUFFER LOOK processing Is the data processed by 2, 3 LOOK data DATA that can be processed? 2,4 KB BUFFER READ processing (1,2) 2,5 Various processing execution according to input data As shown in the above-mentioned flow, in steps 2 and 1, KBBUFF
To know the contents of the data stored in ER KB
Enter the LENGTH of the data you want to know in WORD0 of READ BUFFER.

At steps 2 and 2, the valid data stored in the KB BUFFER is transferred to the buffer KB READ.
DATA LENGTH to be transferred to BUFFER
Is specified in WORD0 of KB READ BUFFER. Buffer KB BUFFER even after transfer
Does not remove that data from. Next steps 2, 3
Then, it is checked whether or not the data put in the KB READ BUFFER is processable data.

If processing is possible, go to steps 2 and 4.

If processing is impossible, steps 2 and 2 are repeated.

In steps 2 and 4, KB BUFFER R
Performs EAD processing (1, 2) and buffers KB BUFFE
Remove from R the data to be processed.

KB READ BUF in steps 2 and 5
Various processes are executed according to the data read in the FER. The specific contents of various treatments are not directly related to the present invention, and therefore omitted. For example, in the kana-kanji conversion process, the conversion process cannot be executed until the input of one phrase is completed. Therefore, in steps 2 and 3, it is checked whether or not the input of one phrase from the KB is completed, and if it is completed, the kana-kanji conversion processing is performed in steps 2 and 5.

KB BUFFE in steps 2 and 2 above
Details of the R LOOK process are shown in FIG. The content of this flow is shown below.

2, 2, 1 KB INT MASK O
N 2, 2, 2 KB BUFFER WORD 4 (DEC
After IMAL processing DATA LENGTH) From KB R
Is EAD BUFFER WORD 0 bigger? 2,2,3 TDL = WORD4 of KB BUFFER 4 D value in KB BUFFER by 2, 2, 4 TDL value
Move ATA to KB READ BUFFER.

2, 2, 6 KB READ BUFFE
Set the value of TDL in R's WORD1.

2, 2, 7 KB INT MASK O
FF Each of the above steps is a KB BUFFER as shown below.
It is almost the same as READ processing, KBBUFFER
The difference from the READ processing is that the KB BUFFER LOOK processing does not affect the buffer KB BUFFER at all.

Steps 2, 2, 1 of the KB BRFFER LOOK process are the same as steps 1, 2, 2 in Steps 2, 2, 2
Is the same as 1, 2, 2 Steps 2, 2, 3 are the same as 1, 2, 3 Steps 2, 2, 4 are the same as 1, 2, 4 Steps 2, 2, 5 are the same as 1, 2, 5 Steps 2, 2, 6 are the same as 1, 2, 6 Steps 2, 2, 7 are the same as 1, 2, 10.

MAIB2 processing is performed as described above.

Next, the processing when the keyboard KB is operated will be described. FIG. 17 shows a flow of KB input processing.
The details of each step are shown below.

DATA is input from 3, 1 KB INT MASK ON 3, 2 KB.

3, 3 FG processing (set of flags, etc.) 3, 4 Valid data? Is the input data BS code? 3,6 BS processing (processing to remove data from KB BUFFER) 3,7 Code conversion processing 3,8 KB BUFFER writing processing 3,9 Dakuten, half-dakuten processing 3,10 Romaji-kana conversion processing 3,11 Half width Processing 3, 12 DECIMAL processing 3, 13 DISPLAY processing 3, 14 KB INT MASK OFF

KB IN in steps 3 and 1 as described above.
Turn on T MASK and input data from KB in steps 3 and 2. In the next steps 3 and 3, it is judged whether or not the data input in the FG processing (setting of input mode, shift, etc.) steps 3 and 4 is valid data for the change in KB BUFFER, and it is judged as valid. If yes, go to steps 3 and 5, and if no, go to steps 3 and 14.

Is the data input in steps 3 and 5 a BS code? If it is a BS code, go to steps 3 and 6.
If not, proceed to steps 3 and 7.

BS processing (KB BUF in steps 3 and 6)
Remove one data from FER), step 3, 14
Proceed to.

Code conversion processing in steps 3 and 7 (converts the KB code of the data input from the KB into an internal code for internal processing in preparation for inserting one data into KB BUFFER). Next step 3 , 8
And write KB BUFFER (write the converted internal code to the buffer KB BUFFER),
In steps 3 and 9, dakuten and semi-dakuten processing (KB BUFFE
DATA LENGTH, that is, KB BU, which has been subjected to the dakuten-semi-dakuten process on the data in R.
Determine FORD WORD 1).

In steps 3 and 10, the Roman character-Kana conversion processing (the data in the KB BUFFER is subjected to the Roman character-Kana conversion processing and the DA converted to the Roman character-Kana conversion processing) is performed.
TALENGTH or KB BUFFER WORD2
Process) and perform half width processing (KB in steps 3 and 11).
Half-width processing is performed on DATA in BUFFER, and half-width processing is performed DATA LENGTH, that is, K
Determine the value of WORD3 of B BUFFER). In steps 3 and 12, DECIMAL processing (KB B
DATALENGTH that is DECIMAL processing for the data in UFFER, that is, KB BUFFER
The value stored in KB BUFFER WORD4 of the data stored in KBBRFFER is determined.
Become ATA. DISPLAY processing in steps 3 and 13 (DATA in KB BUFFER is displayed on the CRT screen
I PLAY). Next, in steps 3 and 14, K
B INT MASK is turned off, and the process ends.

The FG processing shown in the above flow will be further described. FIG. 18 is a flow showing its details, and each step is shown below.

3, 3, 1 Is the entered data a mode key code? [Mode key: Romaji key, Kana key] 3, 3, 2 Set or reset Romaji input FG 3, 3, 3 Is the entered data a width designation key code?
[Width designation key: full width key, half width key] 3, 3, 4 Set or reset full width AWFG 3, 3, 5 Is the entered DATA a shift key code? [Shift key: English big shift key, English decimal shift key,
Katakana shift key, Katakana small shift key, Hiragana shift key, Hiragana small shift key 3, 3, 6 Save shift state in shift register SR 3, 3, 7 Is the input data DECIMAL key? Is 3, 3, 8 DECMAL FG already set? 3, 3, 9 DECMAL FG SET 3, 3, 10 Judge that the input data is valid data.

3, 3, 11 It is judged that the input data is invalid data.

As indicated above, steps 3, 3, 1,
If the data input in 3, 3 and 2 is the mode key, the Roman character flag FG is set or reset depending on whether it is the Roman character or the Kana key. Next steps 3, 3, 3,
If the data input in 3, 3 and 4 is the width designation key, the full width flag AWFG is set or reset according to whether it is the full width key or the kana key.

If the data input in steps 3, 3, 5, 3, 3, 6 is a shift key, it may be the English shift key.
The corresponding shift code is set in the shift register SR in accordance with the English decimal shift key, the Katakana shift key, the Katakana small shift key, the Hiragana shift key, or the Hiragana shift key.

If the data input in steps 3, 3, 7 to 3, 3, 9 is the DECIMAL key, the digital flag DECIMAL FG is set.

If the data entered in steps 3, 3, 10, 3, 3, 11 is the mode key, the width designation key, the shift key, or the DECIMAC key when the digital flag DECIMA FG is set, enter it. The determined data is judged to be invalid data, and if it is other data, it is judged to be valid data, and the FG processing is ended.

Next, the BS processing in steps 3 and 6 will be described with reference to FIG. The details of each step are shown below.

WOR of 3, 6, 1 KB BUFFER
D0 ≠ 0? 3, 6, 1 KB BUFFER WORD 0 decrement 3, 6, 3 KB BUFFER WORD 0 ≧ WORD 1? 3, 6, 4 KB BUFFER WORD 1 decrement 3, 6, 5 KB BUFFER WORD 0 ≧ WORD 2? 3, 6, 6 KB BUFFER WORD 2 decrement 3, 6, 7 KB BUFFER WORD 0 ≧ WORD 3? 3, 6, 8 KB BUFFER WORD 3 decrement 3, 6, 9 KB BUFFER WORD 0 ≧ WORD 4? 3, 6, 10 KB BUFFER WORD 4 decrement 3, 6, 11 DISPLAY processing 3, 13

As described above, steps 3, 6, 1-3,
At 6 and 10, one data stored therein is removed from the KB BUFFER. For that purpose KB BUFFE
Decrement WORD 0 of RQ. Another WOR
Even if D1 to WORD4 are larger than WORD0, only the WORD is decremented. In the next steps 3, 6, and 11, KB BUFFER is displayed on the display device CRT and the BS process is terminated.

Next, the code conversion processing in steps 3 and 7 will be further described. FIG. 20 shows the flow,
The contents are shown below.

The code of the data input from 3, 7, and 1 KB is converted into an internal code by referring to the KB code / internal code conversion table, and then stored in the internal code register.

3, 7, 2 Is Romaji input FG set? 3,7,3 Is the current shift status English shift or English shift? Bits 8 of the internal code registers IRFG are set to 1.

As described above, steps 3, 7, 1 to 3,
The KB code of the data input from KB in 7 and 4 is
The code is converted into an internal code by using the internal code conversion table, and the result is written in the internal code register IREG. At that time, the bit of the data written in the internal code register IREG in the Roman character input mode and in the Katakana shift, the Katakana small shift, or the Hiragana small shift.
8 is set to 1 to indicate that the data is a character forming a Roman character, and the code conversion process is ended.

Next, KB BUFFER in steps 3 and 8
The details of the writing process will be described. FIG. 21 shows the flow, and the contents of each step are shown below.

[0114]

[Outside 2] That is, the value of the internal code register is written to the DATA position indicated by the address of [value of WORD 0 + 1] of KB BUFFR.

3, 8, 2 KB BUFFER WOR
Increment D 0.

As described above, DAT of KB BUFFER
The character code in the internal code register is added to the end of the DATA string in the area A, and the work of KB BUFFER WORD1 (D
ATA LENGTH) and KB B
The UFFER writing process ends.

Details of the dakuten and semi-dakuten processing in step 3.9 will be described below. FIG. 22 shows the flow, and the contents of each step are shown below. 3.9.1 Roman alphabet FG = 1? 3.9.2 WORD 0> WORD 1? 3.9.3 Is KB BUFFER (WORD0) a dakuten code (″) or a semi-dakuten code? 3.9.4 KB BUFFER WORD0> WORD1 + 2?

[0118]

[Outside 3] 3.9.6 KB BUFFER (hereinafter KBS) (WO
Is RD0) a code that allows dakuten or semi-dakuten?

[0119]

[Outside 4] 3.9.8 WORD 0 ≧ WORD 1 + 2? 3.9.9 Refer to the dakuten and semi-dakuten table DHT and enter KB
2 codes of B (WORD 0-1) and KBB (WORD 0) are changed to JIS kanji code, and the result is KBB (W
ORD0-1).

[0120]

[Outside 5]

As described above, when the Roman character FG = 1 in step 3.9.1, the process proceeds to step 3.9.11, FG = 0.
If it is, the process proceeds to step 3.9.2, that is, if the kana input mode is selected, the process from step 3.9.2 is executed.

KB BUFFER in Step 3.9.2
When WORD 0> WORD 1, since there is a character string to be processed, the process proceeds to step 3.9.3. That is, WOR
The character string sandwiched between D0 and WORD1 is the processing target character string. In other words, DATA LE of the value shown in WORD1 of DATA in KB BUFFER
For NGTH, the dakuten and semi-dakuten processes have been completed, and therefore the process proceeds to step 3.9.3 to process other data.

In step 3.9.3, KBB (WORD
Check 0) whether it is a dakuten code or a semi-dakuten code. K
If BB (WORD0) is a dakuten code or a semi-dakuten code, the process proceeds to step 3.9.8. Otherwise, proceed to step 3.9.4.

(Here, KBB (WORD0) is K
The WORD 0th data of the data in B BUFFER is shown. (Same as below.) If WORD0 ≧ WORD1 + 2 in step 3.9.4, proceed to step 3.9.5. If not, proceed to step 3.9.6.

(Here, WORD0 is KB BUFF.
Refers to the 1st W of the ER. The same shall apply hereinafter) where WORD 0 ≧
What is WORD1 + 2 is data that has not been subjected to dakuten semi-dakuten processing before inputting data from KB.
This is equivalent to checking whether or not it was present in the ER.

WORD1 to WORD1 in step 3.9.5
Set the value of D0-1. That is, KBB (WORD0)
Was not a dakuten or semi-dakuten code, so KBB
All the codes up to (WORD 0-1) are not changed by the dakuten or the semi-dakuten, and those codes are removed from the dakuten-semi-dakuten target characters.

In step 3.9.6, KBB (WORD
If 0) is a code that allows dakuten or semi-dakuten, then WO
Return without changing the value of RD1. That is, the code may change depending on the data to be input next from KB, and KBB (WORD0) remains the subject character for the dakuten semi-voiced mark. If KBB (WORD0) is not dakuten semidakuten enabled, proceed to step 3.9.7 to remove KBB (WORD0) from the dakuten semidakuten target code.

[0128] In step 3.9.7, the word WO is written in WO1.
Set the value of RD0. Then return.

In step 3.9.8, WORD0 ≧ WO
If RD1 + 2, proceed to step 3.7.9. Otherwise, proceed to step 3.9.10.

That is, if there is a dakuten / semi-dakuten target character in the buffer KB BUFFER before the dakuten or semi-dakuten code is input from the KB, the process proceeds to 3.9.9.

In step 3.9.9, KBB (WORD
0-1), KBB (WORD0) 2 codes, and referring to the dakuten semi-dakuten table DHT, with dakuten or semi-dakuten 16
Change to bit internal code and change its value to KBB (WORD
0-1).

In step 3.9.10, WORD0 is decremented.

In step 3.9.11, WORD1 is set to W.
Set the same value as ORD0, and finish the dakuten and semi-dakuten processing.

FIG. 23 shows the details of the Roman-Kana conversion processing in step 3.10. The contents of each step shown in FIG. 23 are shown below. 3.10.1 Roman alphabet FG = 1? 3.10.2 WORD1> WORD2? 3.10.3 bit8 = 1 of KBB (WORD1)? 3.18 KBB (WORD1) bit8 = 0 3.10.5 KBB (WORD2 + 1) to KBB
Can Roman code strings up to (WORD1) be converted to Kana code strings? (Romaji-Kana conversion table RKCT
Refer to section 3.13.1 KBB (WORD 2 + 1) to KBB
The Romaji code string up to (WORD1) is converted into a Kana code string, and the conversion result (see the Romaji-Kana conversion table) is converted again from KBB (WORD2 + 1) to KBB (W
Write to the positions up to ORD1).

[0135]

[Outside 6]

As described above, in step 3.10.1,
When the Roman character FG = 1, the process proceeds to step 3.10.2.
When Romaji FG = 0, the process proceeds to step 3.10.

In step 3.10.2, WORD1> W
If it is ORD2, step 3.1 for the character string to be subjected to the Roman character / Kana conversion processing being present in KB BUFFER.
Proceed to 0.3. Return otherwise.

In step 3.10.3, (KBB (WOR
If bit8 of D1) is 1, KBB (WORD1)
Is a character to be subjected to the Roman-Kana conversion processing, and step 3.1
Proceed to 0.4.

Otherwise, go to step 3.10.

In step 1.10.4, KBB (WOR
D1) bit8 = 0.

At step 3.10.5, the Roman-Kana conversion table RKCT is referred to and KBB (WORD2 +
It is checked whether the Roman character code string from 1) to KBB (WORD1) can be converted into the Kana code string. If conversion is possible, proceed to step 3.10.6. If no, it returns.

In step 3.10.6, KBB (WOR
The Roman character code string from D2 + 1) to KBB (WORD1) is converted to the Kana code string, and the converted result is again K
The value is from BB (WORD2 + 1) to KBB (WORD1).

At step 3.10.7, the difference between the length of the Roman character code string and the length of the Kana code string is set to LEN.

In step 3.10.8, the value of WORD0 is decremented by the value of register LEN.

In step 3.10.9, the value of WORD1 is decremented by the value of register LEN.

In step 3.10.10, the value of WORD2 is set to the value of WORD1 and the Roman character-Kana conversion processing is terminated.

Details of the half-width processing in step 3.11 are shown in FIGS. 24a and 24b. The details of each step are shown below. 3.11.1 Half width flag HW FG = 1? 3.11.2 WORD2> WORD3? 3.11.3 DECIMAL FG = 1? 3.11.4 Is KBB (WORD2) a character code that can be packed? 3.11.5 WORD2 ≧ WORD3 + 2? 3.11.6 KBB (WORD2-1), and KBB
(WORD2) and packing, KBB (WORD2)
The result is written in -1).

[0148]

[Outside 7] 3.11.8 WORD2 ≧ WORD3 + 2? 3.11.9 KBB (WORD2-1) and space code are packed, and the result is KBB (WORD2).
-1).

[0149]

[Outside 8] 3.11.11 KBB (WORD2) is DECIMA
L TAB end code? 3.11.12 Is the value of [WORD2-WORD3] an odd number? 3.11.13 KBB (WORD 3 + 1) to KBB
The codes up to (WORD2-1) are packed code by code, and as a result, the values after KBB (WORD3 + 1) are set again.

[0150]

[Outside 9] 3.11.15 Space code and KBB (WOR
The codes from D3 + 1) to KBB (WORD2-1) are packed by two codes, and the result is again KBB.
The value after (WOR3 + 1) is used.

[0151]

[Outside 10]

As described above, in step 3.11.1,
Half-width flag HW If FG = 1, step 3.11.2
Proceed to. Half-width flag HW If FG = 0, step 3.
Proceed to 11.10.

In step 3.11.2, WORD2> W
If it is ORD3, there is a character string to be half-width processed, so the process proceeds to step 3.11.3. Otherwise return.

In step 3.11.3, DECIMAL
If FG = 1, go to step 3.111.11. (DE
(CIMAL half-width processing) If DECIMAL FG = 0, the process proceeds to step 3.11.4. (DECIMAL full width processing) In step 3.11.4, it is checked whether KBB (WORD2) is a packable character. The packing here is the character code that should be a half-width character code (1 character is 1
W) is a combination of two characters and is a half-width internal code (2 characters are 1
W). In this embodiment, the half width character code is a space code alphabet code, numeric code and period code.

If KBB (WORD2) is a packable character code, the process proceeds to step 3.11.5. If not, proceed to 3.11.8.

In step 3.11.5, WORD2 ≧ W
If it is ORD3 + 2, that is, if a half-width processing target column already exists in KB BUFFER other than KBB (WORD2), the process proceeds to step 3.11.6. If no, it returns and then waits for input from KB.

In step 3.11.6, KBB (WOR
D2) and KBB (WORD3) are packed into KBB
The result is written in (WORD2-1).

The packing method will be described later.

In step 3.11.7, WORD0, W
The value of WORD3 obtained by subtracting 1 from the values of ORD1 and WORD2 is set to the value of WORD2. Then return.

In step 3.11.8, WORD2 ≧ W
If ORD3 + 2, that is, if there is a single half-width object character in KBBUFFR, then step 3.11.9.
Proceed to. If not, proceed to 3.11.

In step 3.11.9, KBB (WOR
D2-1) and the space code are packed, and the result is used as the value of KBB (WORD2-1).

In step 3.11.10, the value of WORD3 is set to the value of WORD2.

In step 3.11.11, KBB (WO
If RD2) is the DECIMAL TAB end code, go to step 3.11.12. If no, it returns. That is, after step 11.12, DECIMAL
Perform after the TAB mode is completed. DECIMA here
The L TAB end code is a code other than numbers.

In step 3.11.12, WORD2-
If the value of WORD3 is odd, step 33.11.
Proceed to 13. If not, go to step 3.11.15.

In step 3.11.13, KBB (WO
The code strings from RD3 + 1) to KBB (WORD2-1) are packed every two codes, and as a result, KBB is again packed.
The value after (WORD3 +) is used.

In step 3.11.14, (WORD2
-Calculate the value of WORD3-1 / 2 and the result is DF
Put in REG. Then proceed to step 3.11.17.

In step 3.11.15, the space code and KBB (WORD3 + 1) to KBB (WORD2
The codes up to -1) are packed two by two, and the resulting code is used as the value after KBB (WORD3 + 1).

In step 3.11.16, (WORD2
Calculate WORD3) / 2 and put that value in DF REG.

In step 3.11.17, the value of WORD3 is increased by the value of DF REG.

In step 3.11.18, WORD2-
Calculate WORD3-1 and enter the value in DF REG.

In step 3.11.19, WORD0,
DF RE from each value of WORD1 and WORD2
The value of G is reduced and the half width processing is completed.

Next, the above-mentioned steps 3.11.6 and 3.1.
The packing process performed in 1.9, 3.11.13 and 3.11.15 will be described with reference to FIG. This process is a process for packing two units (2W) of the character code to be half-width processed into the half-width internal code (1W), and the contents of each step are shown below.

4.1 Is the packing target first W a full-width space code or period code? 4.2 Packing register bit1 to bit7 to 0
It is set to 100000 or 0101110.

4.3 Packing register bits 1 to
Bit7 is the packing target first W bit9 to bit1
The value is 5.

4.4 Is the 2nd W to be packed the full width space code or period code? 4.5 Let bit9 to bit15 of the packing register be 0100000 or 0101110.

4.6 Packing Register bits 9-
Bit 15 is packed in the second W bit 9 to bit
The value is 15.

As described above, in steps 4.1 to 4.6, the first width bit9 to bit15 of the half width target character is put into the packing register bit1 to bit7, and the second width bit9 to bit15 of the half width target character is stored in the packing register. Put in bit9 to bit15. After that, bit0 of the packing register is set to 1.

However, when the character code to be packed is a space code or a period, it is bit9 to bi.
"0100000" or "01011" instead of t15
10 "is used. Thus, the half width internal code packed in the packing register can be obtained.

26 and 27 show an example of packing processing.
26 shows an example of half width packing, and FIG. 27 also shows an example of half width packing.

Details of the DECIMAL processing at step 3.12 are shown in FIG. The contents of each step are shown below. 3.12.1 DECIMAL FG = 1? 3.12.2 KBB (WORD0) is DECIMAL
TAB exit code? 3.12.3 DECIMAL FG reset

[0181]

[Outside 11]

As described above, in step 3.12.1, D
When ECIMAL FG = 1, the process proceeds to step 3.12.2. If no, go to step 3.12.4.

In step 3.12.2, KBB (WOR
If D0) is the DECIMAM TAB exit code, go to step 3.12.3. If no, it returns. That is, until the DECIMAL TAB end code is typed from the KB, the DECIMAL is set in the KB BUFFER.
The data input in the TAB mode cannot be valid data.

The DECIMAL TMB end code is a code other than numbers.

In step 3.12.3, DECIMAL
Set FG to 0.

At step 3.12.4, the value of WORD4 is set to the value of WORD3, and the DECIMAL processing is terminated.

Next, the buffer KB BUF described above
The state of the data in the FER will be described with reference to FIGS.

In a, a processing example for the BS (backspace) key is shown. The last data "D" in KBBUFFER is deleted and KB BUFFER T is deleted.
It can be seen that a part of DATA LENGTH of the EADER section parameter is reduced. However, WO
After RD2, the influence does not reach.

In b, a processing example for the dakuten key is shown. There is no change in the value of VORD0, but WO
There is also an increase in RD2 and, by extension, an increase in WORD4 indicating the effective DATA LENGTH of KB BUFFER.

In c, KB for inputting Roman characters
You can see the inside of BUFFER. Also in this case, all DA
Although the value of WORD0 indicating TA LENGTH does not change, it can be seen that the value of WORD4 indicating effective DATA LENGTH increases.

D is the state of KB BUFFER when the "F" key is pressed in the half width input mode.

Reference character e shows the state of DECIMAL processing in the full-width mode.

Reference character f shows the state of DECIMAL processing in the half-width mode.

Next, the DISPLAY processing in step 3.13 will be described with reference to FIG.

The contents of each step are shown below. 3.13.1 CRT REFRESH MEMORY
Fill in all the space codes at the position corresponding to the 8th line of. 3.13.2 Codes KBB (1) to KBB (WORD0) are written in order from the position of the 1st digit of the 8th row of the CRT REFRESH MEMORY. KBB at that time
Bi from (WORD4 + 1) to KBB (WORD0)
Convert to t8 = 1 and write. (However, WORD4 = WOR
3.13 Cursor code is CRT REFRES
Write at the position of the (VORD0 + 1) th column of the 8th row of H MEMORY.

As described above, in step 3.13.1, C
Fill in all the space codes at positions corresponding to the 8th line of RT REFRESH MEMORY.

KB BUFFE in step 3.13.2
The data in R (whose length is specified by WORD0) is moved to the position corresponding to the 8th line of the CRT REFRESH MEMORY. At this time, if the values of WORD4 and WORD4 are different, the valid PATA LENGTH in DATA in the buffer KB BUFFER and all DAT
There will be a difference between A LENGTH. The effective data is displayed normally on the display position CRT, and the data which is not yet effective data is displayed on the low brightness. Therefore, the memory CRT corresponding to the [WORD4 + 1] th data to the [WORD0] th data
Bit 8 of the data in REFRESH MEMORY
To 1.

In step 3.13.3, the cursor code is added to the memory CRT REF in order to inform the user of the position of the data to be input next from the keyboard KB on the eighth line.
8th line of RESH MEMORY [WORD0 + 1]
Write at the position of the digit. The cursor code is a code assigned in correspondence with the cursor pattern.

The DISPLAY processing is completed as described above.

In the above-described embodiment, the period is packed with the numerical value after the decimal point in the half width DECIMAL processing, but the numerical value with the first digit and the period may be packed. ..

In the present embodiment, the effective data and the data which are not yet effective data are distinguished by changing the display brightness. However, a method of distinguishing by reverse display blinking display, high brightness display, etc. is also considered. Be done.

In the present embodiment, the input monitor device for sequentially displaying the input data has been described, but the present invention is not limited to the input monitor device and can be applied to any character processing device having an input means and an output means.

As described above, according to the present invention, the interruption of the position of the cursor due to the difference in the number of characters that occurs when the first character is converted into the second character is prevented, and the first character follows the second character. It can be seen on the display screen as if you are entering characters.

[0204]

As described above in detail, according to the present invention, in the Roman character input state, the consonant data and vowel data of the inputted English character data are converted into corresponding Kana data as Kana of the Roman character expression, and the inputted Kana data is inputted. The kana data to be converted is displayed without visually displaying vowel data, and in the kana input state, when kana data is input after the kana data is input, the kana data is compared to the kana data. It is now possible to provide a character processing method for controlling the display so that the display is added.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment according to the present invention.

FIG. 2 is a diagram illustrating a buffer KB BUFFER.

[FIG. 3] Memory LRY REFRESH MEMORY
FIG.

FIG. 4 is a diagram illustrating a buffer KB READ BUFFER.

FIG. 5 is a diagram illustrating a data configuration diagram.

FIG. 6 shows details of the keyboard KB.

FIG. 7 is a diagram showing a KB code internal code conversion table.

FIG. 8 is a diagram showing a dakuten and semi-dakuten table.

FIG. 9 is a diagram showing a Romaji-Kana conversion table.

FIG. 10 is a diagram illustrating a CRT controller.

FIG. 11 is a diagram illustrating initialization processing.

FIG. 12 is a diagram showing MAIN processing 1.

FIG. 13 is a diagram showing MAIN processing 2.

FIG. 14 is a diagram showing a KB BUFFER READ process.

FIG. 15 is a diagram showing changes in data.

FIG. 16 is a diagram showing a KB BUFFER LOOK process.

FIG. 17 is a diagram showing KB input processing.

FIG. 18 is a diagram showing FG processing.

FIG. 19 is a diagram showing BS processing.

FIG. 20 is a diagram showing code conversion processing.

FIG. 21 is a diagram showing a KB BUFFER write process.

FIG. 22 is a diagram showing a dakuten and semi-dakuten process.

FIG. 23 is a diagram showing Roman character-Kana conversion processing.

24A and 24B are diagrams showing half-width processing.

FIG. 25 is a diagram showing a packing process.

FIG. 26 is a diagram illustrating half-width packing.

FIG. 27 is a diagram illustrating half-width packing (when there is a space).

FIG. 28 is a diagram showing DECIMAL processing.

29A to 29F are diagrams showing data movement.

FIG. 30 is a diagram showing a DISPLAY process.

[Explanation of symbols]

 RAM memory ROM control memory CPU microprocessor CRT display device

Claims (1)

[Claims] 1. In Romaji input state, consonant data and vowel data of input English character data are converted into corresponding Kana data as Kana of Romaji expression,
The converted kana data is displayed without visually displaying the input vowel data, and in the kana input state, when kana data is input after kana data is input, the kana data is changed to the kana data. On the other hand, a character processing method characterized by controlling the display so as to add a dakuten to display.