JPH05251471A - Method of manufacturing field-effect transistor - Google Patents

Abstract

PURPOSE:To provide a field-effect transistor having a recess gate structure having a low parasitic resistance even if the recess is deep and an improved characteristic by a method wherein a part, with which a gate electrode comes into contact, is etched deeper than the periphery to form an etching shape having two steps. CONSTITUTION:In a field-effect transistor having a recess gate structure, in a layer to be removed by etching at forming a recess, an undope Al0.3Ga0.7As layer 43 (50Angstrom ) having a late etching speed is formed to etch these layers by a dry etching method, therefore the recess having a two-step shape is formed and a gate electrode 47 is so formed as to conform to the recess part on the lower side of the two-step shape.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a gate recess and a gate electrode of a field effect transistor (FET) which constitutes a microwave band transistor, an ultra high speed logic IC or the like using a compound semiconductor or the like. The present invention relates to a method of forming the.

[0002]

2. Description of the Related Art Conventionally, as a technique of this kind of field, for example, "T. Saito et al., IEEE Ga.
As IC Symp. Technical dige
st, pp. 117-120: 1989 ". FIG. 4 is a sectional view of a conventional field effect transistor.

As shown in this figure, in the transistor, the high-concentration n-type GaAs layer 8 provided for the purpose of reducing the parasitic resistance is removed by etching and recessed.
s) is formed and the Al gate electrode 9 is formed there. The threshold voltage of the transistor is
A desired value can be set by controlling the depth of this recess. The recess can be formed by using either wet etching method or dry etching method, but in the above-mentioned literature, it is excellent in depth controllability,
Cl ₂ ECR (Electr) capable of anisotropic etching
Reactive Ion Beam Etching Method (RIB) Using On-Cyclotron Resonance Plasma
E: Reactive Ion Beam Etchi
ng) is used.

In FIG. 4, 1 is a semi-insulating material (S.
I. ) GaAs substrate, 2 is an undoped GaAs layer formed on the GaAs substrate 1, 3 is an undoped AlGaAs layer formed on the GaAs layer 2, and 4 is Al
An n-type AlGaAs layer 5 formed on the GaAs layer 3 is an undoped A formed on the n-type AlGaAs layer 4.
lGaAs layer, 6 is an undoped GaAs layer formed on the AlGaAs layer 5, 7 is an n-type GaAs layer formed on the GaAs layer 6, 10 is a source / drain electrode, and is made of an AuGe / Ni / Au alloy. Become.

[0005]

However, in the above-mentioned conventional FET having a recess gate structure, a space is generated between the side surface of the recess and the gate electrode, and the resistance of the space increases as the recess becomes deeper. There was a problem. Particularly in the case of an enhancement mode transistor, since the recess is deep, the parasitic resistance is remarkably increased and the characteristics are deteriorated.

According to the present invention, in order to eliminate the above-mentioned problem that the parasitic resistance on the side of the gate electrode increases due to the deepening of the recess, the portion in contact with the gate electrode is etched deeper than the peripheral portion, and 2 It is an object of the present invention to provide a method for manufacturing a field effect transistor having a recess gate structure in which a stepped etching shape is formed, a parasitic resistance is low even when a recess is deep, and characteristics can be improved.

[0007]

In order to achieve the above object, the present invention provides a method of manufacturing a field effect transistor having a recess gate structure, in which a layer having a slow etching rate is inserted into a layer to be removed by etching during recess formation. And a step of forming a two-step-shaped recess by etching these layers by a dry etching method, and a step of forming a gate electrode so as to conform to the lower recessed part of the two-step shape. Is to be applied.

Further, the gate electrode is formed in the lower recess portion in a self-aligned manner by using the etching mask in the recess step.

[0009]

According to the present invention, as described above, a two-step recess is obtained by inserting a thin layer of a material having a slow etching rate into the layer to be removed by etching when forming the recess. A gate electrode is formed in the lower recess portion of the two-step shape. Therefore, the parasitic resistance beside the gate electrode can be reduced. In addition, the effective gate length can be shortened. Therefore, the field effect transistor characteristics can be improved.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a sectional view of a field-effect transistor (GaAs MESFET) manufacturing process showing an embodiment of the present invention, FIG. 2 is a view showing a layer structure of an epitaxial growth film of a field-effect transistor showing the embodiment of the present invention, and FIG.
[FIG. 3] is a cross-sectional view of a recess formed by etching an epitaxial growth film by an SEM (electron microscope).

As shown in FIG. 2, in order to make the shape of the recess into two stages, the epitaxial growth film is made of semi-insulating GaA.
undoped GaAs layer 21 on the s substrate, and undoped Al _0.3 Ga _0.7 As layer (50 Å) on the GaAs layer 21
22, undoped Ga on the Al _0.3 Ga _0.7 As layer
The As layer (1000 Å) 23 is sequentially grown by the MBE (molecular beam epitaxial) method.

Growth film according to the invention and conventional undoped G
FIG. 3 shows the result of SEM observation of the recess formed by using the grown film composed of only the aAs layer. Figure 3 (a)
Is a sectional view of a recess according to the present invention, and FIG. 3B is a sectional view of a recess according to a conventional technique. Here, the etching was performed by a reactive ion beam etching method using ECR plasma using a mixed gas of Cl ₂ and SF ₆ . A mask having an opening length of about 0.7 μm and an overhang shape is used.

In the conventional layer structure shown in FIG. 3B, the conventional undoped GaAs epitaxial growth film 30 is etched from the lower end of the etching mask 35, and a round recess shape is obtained. On the other hand, in the layer structure of the present invention shown in FIG. 3A, a flat portion appears at the undoped Al _0.3 Ga _0.7 As layer 22 (see FIG. 2), and a two-step recess shape is obtained. Reference numeral 25 is an etching mask.

This is undoped Al _0.3 Ga _0.7 As
This is because the etching rate of the layer 22 is smaller than that of the undoped GaAs layer. The etching rate selection ratio in this example was about 8. These two recesses can be controlled to have a desired shape by selecting the composition, position, thickness and selection ratio of the undoped GaAs layer.

Hereinafter, GaAsFE showing an embodiment of the present invention
A method of manufacturing T will be described. First, as shown in FIG. 1A, an undoped GaAs buffer layer 41 is formed on a semi-insulating GaAs substrate 40, and its undoped Ga is formed.
An n-type GaAs channel layer 42 is formed on the As buffer layer 41. A thin n-type Al _0.3 Ga _0.7 As layer 43 having a low etching rate is formed on the channel layer 42. On the Al _0.3 Ga _0.7 As layer 43, n ⁺ type Ga is formed.
The As contact layer 44 is formed, and the contact layer 4 is formed.
A source / drain electrode 45 is formed so as to be connected to No. 4.

Next, as shown in FIG. 1B, a resist 46 having an overhang shape is formed, and etching is performed using the resist 46 as a mask to obtain a two-step recess shape. Next, as shown in FIG. 1C, the resist 46 is used as it is, and a gate electrode 47 is formed in the recess.
To form.

As described above, n-type Al _0.3 Ga _0.7 A
Since the s layer 43 is inserted under the n ⁺ type GaAs contact layer 44, the recess is formed in the n ⁺ type GaAs contact layer 4
It has a two-tiered shape under 4. 2 for the gate electrode 47
It is formed in the lower recess portion of the step-shaped recess and is separated from the n ⁺ -type GaAs contact layer 44. With this shape, the gate electrode 47 is maintained while maintaining the gate breakdown voltage.
The parasitic resistance on the side can be reduced. Further, since the gate electrode 47 is formed in the round recess portion, the effective gate length becomes shorter than that of the conventional structure, and improvement in characteristics can be expected.

In the present embodiment, the reactive ion beam etching method was used and the AlGaAs layer was inserted. However, the combination of the etching method and the thin layer is not limited to this as long as the etching rate selectivity can be obtained. Any combination may be used as long as stacking is possible. It should be noted that the present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0019]

As described above in detail, according to the present invention, since a thin layer of a material having a different etching rate is inserted into the layer to be removed by etching when forming the recess, the recess has a two-step shape. Since the gate electrode is formed in the recess portion below the gate electrode, the parasitic resistance on the side of the gate electrode can be reduced. In addition, the effective gate length can be shortened. This can improve the characteristics of the field effect transistor.

[Brief description of drawings]

FIG. 1 is a sectional view of a field-effect transistor manufacturing process showing an embodiment of the present invention.

FIG. 2 is a diagram showing a layer structure of an epitaxial growth film of a field effect transistor showing an example of the present invention.

FIG. 3 is a sectional view by SEM of a recess formed by etching an epitaxial growth film.

FIG. 4 is a cross-sectional view of a conventional field effect transistor.

[Explanation of symbols]

21 undoped GaAs layer 22 undoped Al _0.3 Ga _0.7 As layer (50 Å) 23 undoped GaAs layer (1000 Å) 25, 35 etching mask 40 semi-insulating GaAs substrate 41 undoped GaAs buffer layer 42 n-type GaAs channel layer 43 n-type Al _0.3 Ga _0.7 As layer 44 n ⁺ type GaAs contact layer 45 source / drain electrode 46 resist 47 gate electrode

Claims (2)

[Claims] 1. A method of manufacturing a field effect transistor having a recess gate structure, comprising the steps of: (a) inserting a layer having a slow etching rate into a layer to be removed by etching during recess formation, and (b) dry etching these layers. Electric field characterized by performing a step of forming a recess having a two-step shape by etching by a method and (c) forming a gate electrode so as to conform to the recessed portion on the lower side of the two-step shape. Effect transistor manufacturing method. 2. The field effect transistor manufacturing method according to claim 1, wherein the gate electrode is formed in the lower recess portion in a self-aligned manner by using the etching mask of the recess step. Effect transistor manufacturing method.