JPH05259891A - Clocked inverter circuit - Google Patents

Abstract

PURPOSE:To minimize the speed reduction and the increase in the circuit area and to obtain high breakdown voltage and high reliability by adopting a MOS transistor(TR) of a specific structure for a 2nd N-channel MOS TR. CONSTITUTION:First and 2nd P-channel MOS TRs 102, 103 and 1st and 2nd N-channel MOS TRs 104, 105 are connected in series respectively. Drain electrodes of the 2nd P-channel MOS TR 103 and the 2nd N-channel MOS TR 105 are connected to an output signal line. An offset area 106 is provided to the drain electrode of the 2nd N-channel MOS TR 105. Or a TR of lightly doped drain structure may be adopted in place of the offset gate structure. Thus, a drain electric field of the 2nd N-channel TR 105 is relaxed and characteristic deterioration in the circuit due to production of a hot carrier is suppressed. High breakdown structure is not adopted for the 1st N-channel MOS TR 104.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to a clocked inverter circuit used in peripheral drive circuits such as liquid crystal displays, contact image sensors, liquid crystal shutters and the like.

[0002]

2. Description of the Related Art For the purpose of downsizing, cost reduction, and high reliability of liquid crystal displays, contact image sensors, liquid crystal shutters, etc., there is a technique for integrally manufacturing a thin film drive circuit. This results from the fact that the number of connection terminals and the number of external drive ICs can be significantly reduced by installing a peripheral drive circuit on the same substrate as the pixel electrodes, and the limitation of a large area and high-density bonding process. It is based on the concept of being able to solve reliability problems.

FIG. 6 shows two P-type MOS transistors P.
1, P2 and two N-type MOS transistors N1, N2
A circuit diagram of a clocked CMOS inverter (hereinafter referred to as a clocked inverter) configured by is shown. The clocked inverter can control the output timing by the clock signals φ and φ (inversion). That is,
When the clock φ is at the high level and the clock φ (inversion) is at the low level, a signal obtained by inverting the input signal is output. Next, the clock signal φ is low level, and the clock signal φ (inverted)
When becomes high level, the inverted signal is held by the output load capacitance. The input signal is input to the gate electrodes of P2 and N2, and the clock signals φ and φ (inversion) are input to N1 and P1 respectively.
Even if it is connected to the gate electrode of, the same operation is performed. These clocked inverters are now important constituent elements of peripheral drive circuits such as active matrix liquid crystal displays and contact image sensors.

7 and 8 are a plan view of a conventional clocked inverter composed of a polycrystalline silicon thin film transistor (hereinafter referred to as p-SiTFT) and a sectional view of a line segment AB. TFT structure is coplanar self-aligned TF
T. 7 and 8, the first P-type MOS transistor P1 102, the second P-type MOS transistor P2 103, and the first N-type MOS transistor N1.
Although the transistor sizes of 104 and the second N-type MOS transistor N2 105 are all designed to be the same,
Usually the size of P-type MOS transistor (W _p / L _p )
Is designed to be (μn / μp) times the size (W _n / L _n ) of the N-type MOS transistor. Here, μn and μp represent the field effect mobility of the N-type MOS transistor and the P-type MOS transistor, respectively. Also, the first and second P
The type MOS transistors are usually designed to have the same size, and the same applies to the sizes of the first and second N-type MOS transistors.

In FIGS. 7 and 8, 101 is a glass substrate, 107 is ap ⁺ -p-Si layer, and 108 is n ⁺ -p-.
Si layer, 109 is p-Si layer, 110 is gate SiO ₂
Layer, 111 is a gate n ⁺ -p-Si layer, 112 is Al
The layer 113 is a passivation SiO ₂ layer.

[0006]

In an active matrix liquid crystal display integrated with a peripheral drive circuit, a data signal having an amplitude of about 12 V is transferred to an N-type M arranged in each pixel.
In order to transfer to the pixel electrode via the OS transistor,
Normally, the pulse height is about 20V (12V + N type MOS
A gate pulse signal of the transistor threshold voltage VTn) is required. That is, the peripheral drive circuit must be driven by the power supply voltage of 20V. In that case, the sources of P1, P2, N1, and N2 that make up the clocked inverter
There is a state in which an absolute value of about 20 V is applied between the drains. Therefore, in order for the peripheral drive circuit to operate stably, a source-drain breakdown voltage of 20 V or higher is required.

On the other hand, with the shortening of the channel of the transistor, the generation of hot carriers becomes a problem especially in the N-type transistor. Hot carriers are generated because electrons flowing from the source to the drain are accelerated by a strong electric field near the drain to obtain large energy. The electrons injected into the strong electric field region near the drain generate a large number of electron-hole pairs by impact ionization. These hot carriers cause an excessive drain current or are injected into the oxide film to cause deterioration of drain breakdown voltage, increase of threshold voltage, and decrease of mutual conductance.

Single crystal silicon L generally driven by 5V
In SI, this hot carrier becomes a problem when the channel length is 2 μm or less. However, as described above, in the peripheral drive circuit of the liquid crystal display, 20V drive is required, so that a channel length region (for example, 6 μm) at which 5V drive does not cause any problem.
The problem of hot carrier generation also occurs in m). In order to solve this problem, it is most effective to adopt a structure for relaxing the electric field strength at the drain end, that is, an offset gate structure or an LDD (Lightly Doped Drain) structure. Further, it is naturally conceivable to increase the drain breakdown voltage by increasing the channel length. However, since these high breakdown voltage structures have a smaller ON current than the normal structure, they are not necessarily ideal structures in terms of the speed of the drive circuit. Further, when the channel width is increased to increase the ON current, the circuit area increases, which makes it difficult to increase the density and also reduces the yield.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clocked inverter circuit with high withstand voltage and high reliability, in which a decrease in speed and an increase in circuit area are suppressed to a minimum in order to solve the above problems.

[0010]

According to the present invention, there is provided a first P-type MOS transistor having a gate electrode connected to an input signal line and a source electrode connected to a power supply line, and a gate electrode having a first clock signal. A second line connected to the line, the source electrode connected to the drain electrode of the first P-type MOS transistor, and the drain electrode connected to the output signal line
P-type MOS transistor, a first N-type MOS transistor having a gate electrode connected to the input signal line and a source electrode connected to the ground line, and a gate electrode having a phase opposite to that of the first clock signal line. Is connected to the second clock signal line having the relationship
A second N-type MO connected to the drain electrode of the OS transistor and the drain electrode connected to the output signal line.
In the clocked inverter circuit including the S-transistor, the second N-type MOS transistor is a MOS transistor having an offset gate structure or a MOS transistor having a lightly doped drain structure.

According to the present invention, a first P-type MOS transistor having a gate electrode connected to an input signal line and a source electrode connected to a power supply line, and a gate electrode connected to a first clock signal line, and The source electrode is the first P-type MO
A second P-type MOS transistor connected to the drain electrode of the S transistor and having a drain electrode connected to the output signal line; and a gate electrode connected to the input signal line,
And a first N-type MOS whose source electrode is connected to the ground line
A transistor and a gate electrode connected to a second clock signal line having a phase opposite to that of the first clock signal line, and a source electrode connected to a drain electrode of the first N-type MOS transistor; In a clocked inverter circuit having a second N-type MOS transistor whose drain electrode is connected to the output signal line, the channel length of the second N-type MOS transistor is the first
Is larger than the channel length of the N-type MOS transistor.

[0012]

FIG. 9 shows an example of operation waveforms of the clocked inverter shown in FIG. Input signal, clock signal φ, clock signal φ (inversion), terminals A, B (output), C in order from the top
Voltage V (A), V (B), V (C), the first and second P
Source-drain voltage V of the p-type transistors P1 and P2
ds (P1), Vds (P2), the source-drain voltage Vds (N of the first and second N-type transistors N1, N2
1) and Vds (N2). From this operation waveform example, it can be seen that the maximum voltages between the source and drain of the four transistors forming the clocked inverter are as follows.

| Vds (P1) | max = | -VDD-VTP || Vds (P2) | max = | -VDD | | Vds (N2) | max = | VDD | | Vds (N1) | max = | VDD -VTN | where VDD is the drive voltage and VTP and VTN are the threshold voltages of the P-type and N-type transistors, respectively. For example, VDD = 20V, VTP = -5V, VTN = 3V
In this case, | Vds (P1) | max = 15V | Vds (P2) | max = 20V | Vds (N2) | max = 20V | Vds (N1) | max = 17V. Therefore, it is expected that the transistor most likely to cause the deterioration of the characteristics due to the generation of hot carriers described above is the second N-type transistor N2 in which the maximum value of the source-drain voltage is 20V.

Therefore, it is most effective to make the second N-type transistor have a high withstand voltage structure in order to increase the withstand voltage of the clocked inverter. In the clocked inverter of the present invention, the withstand voltage of the clocked inverter is increased by adopting the withstand voltage structure only for the second N-type transistor. In that case, compared with the clocked inverter that adopts the high breakdown voltage structure for the first N-type transistor, which does not require the breakdown voltage as much as the second N-type transistor, the speed due to the high breakdown voltage structure transistor is adopted. Since it is possible to suppress the decrease and also reduce the circuit area, it is advantageous for high density.

[0015]

Embodiments of the clocked inverter circuit of the present invention will be described in detail below.

1 and 2 are views showing a first embodiment of the clocked inverter of the present invention, FIG. 1 being a plan view and FIG.
Represents a cross-sectional view of the line segment AB. It was manufactured by integrating p-Si TFTs on the glass substrate 101. The TFT structure is a coplanar structure. As shown in the figure, the clocked inverter of the present embodiment has first and second P-series connected in series.
Of the type MOS transistors 102 and 103 and the first and second N-type MOS transistors 104 and 105, an offset region 106 is provided on the drain electrode side of the second N-type MOS transistor. An LDD structure transistor may be adopted instead of the offset gate structure. Thereby, the drain electric field of the second N-type transistor can be relaxed, and as described above, the deterioration of the circuit characteristics due to the generation of hot carriers can be effectively suppressed. The offset region is not provided on the source electrode side of the second N-type transistor because the transistor O
This is to suppress the decrease in N current. Furthermore, the first
Since no offset gate structure is adopted for the N-type transistor, the speed is higher than that of the clocked inverter adopting the offset gate structure for the first N-type transistor. However, as mentioned above,
Source-drain voltage Vds of the first N-type transistor
Since a maximum voltage (VDD-VTN) V is applied to (N1), the withstand voltage of the first N-type transistor is (VDD-VTN).
It is necessary to design the channel length to be V or more.

FIG. 5 shows the p-Si produced in this embodiment.
It is a figure which shows the channel length dependence of source-drain breakdown voltage BVds of an N-type transistor. A transistor having a normal single-gate structure and a transistor having an offset gate structure (offset length of 0.4 μm) are shown. BVds has a drain current of 1 when the gate voltage is 0V.
It was defined by the source-drain voltage of μA. From this graph, the channel lengths of the first and second N-type transistors were determined. That is, when the driving voltage VDD = 20V and the threshold voltage VTN of the N-type transistor VTN = 4V, the first and second N
The channel length of the type transistor was set to 8 μm. As a result, the drain withstand voltages of the first and second N-type transistors become 17V and 22V, respectively, and the required withstand voltage BVds (N1)> 16V and BVds (N
2)> 20V can be satisfied.

As a result of producing a vertical scanning circuit for a liquid crystal display by using the clocked inverter of the present invention, the speed is maintained even after continuous operation for 1500 minutes under the conditions of power supply voltage VDD = 20 V and clock frequency f = 1 MHz. No deterioration was observed. Further, the maximum clock frequency of the manufactured scanning circuit is 5 MHz when VDD = 12 V,
The characteristics are the same as those of the conventional scanning circuit that does not use a transistor with a high breakdown voltage structure.

Next, a second embodiment of the clocked inverter circuit of the present invention will be described.

FIGS. 3 and 4 are diagrams showing a second embodiment of the clocked inverter circuit of the present invention. 3 is a plan view, and FIG. 4 is a cross-sectional view of the line segment AB. Similar to the first embodiment, a coplanar p-S is formed on the glass substrate 101.
It was manufactured by integrating iTFT. The difference from the first embodiment is that the circuit withstand voltage is effectively increased by making the channel length of the second N-type transistor larger than that of the first N-type transistor. .. The transistor structure is similar to that of the first N-type transistor.
In this case, it is possible to avoid the problem that the transistor characteristics vary due to the variation in offset length as in the offset gate structure transistor. The channel lengths of the first and second N-type transistors were designed by utilizing the channel length dependence of the breakdown voltage between the source and drain shown in FIG. Drive voltage VDD = 20V, fabricated p-Si
Since the threshold voltage VTN of the n-channel TFT was 4V = 4V, the channel length L1 of the first and second N-type transistors was
L2 was set to 8 μm and 12 μm, respectively. This allows
The source-drain breakdown voltages of the first and second N-type transistors are 17 V and 21 V, respectively, and the required breakdown voltage BVds (N1)> 16 V, B for each transistor.
Vds (N2)> 20V can be satisfied.

The scanning circuit using the clocked inverter of this embodiment showed high withstand voltage and high reliability characteristics as in the first embodiment. Further, the maximum clock frequency of the manufactured scanning circuit was 4 MHz when VDD = 12V, which was equivalent to the characteristics of the conventional scanning circuit which does not use the transistor having the high breakdown voltage structure.

[0022]

As described above, by applying the clocked inverter circuit of the present invention, it is possible to effectively increase the withstand voltage of a scanning circuit such as a liquid crystal display, a contact image sensor, and the like. In comparison with the clocked inverter that adopts the high breakdown voltage structure for the first N-type transistor, which does not require the breakdown voltage as much as the N-type transistor, the reduction in speed due to the adoption of the high breakdown voltage structure transistor can be suppressed. In addition, the circuit area can be reduced, which is advantageous for high density. Therefore, the clocked inverter circuit of the present invention is extremely useful as a constituent element of a scanning circuit of an image input / output device.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of a clocked inverter circuit of the present invention.

FIG. 2 is a cross-sectional view showing a first embodiment of the clocked inverter circuit of the present invention.

FIG. 3 is a plan view showing a second embodiment of the clocked inverter circuit of the present invention.

FIG. 4 is a sectional view showing a second embodiment of the clocked inverter circuit of the present invention.

FIG. 5 is a diagram showing the channel length dependency of the source-drain breakdown voltage of an N-channel p-Si TFT.

FIG. 6 is a diagram showing a circuit configuration of a clocked inverter circuit.

FIG. 7 is a plan view of a conventional clocked inverter circuit.

FIG. 8 is a cross-sectional view of a conventional clocked inverter circuit.

FIG. 9 is a diagram showing an example of operation waveforms of a clocked inverter circuit.

[Explanation of symbols]

101 glass substrate 102 first P-type MOS transistor P1 103 second P-type MOS transistor P2 104 first N-type MOS transistor N1 105 second N-type MOS transistor N2 106 offset region 107 p ⁺ -p-Si layer 108 n ⁺ -p-Si layer 109 p-Si layer 110 Gate SiO ₂ layer 111 Gate n ⁺ -p-Si layer 112 Al layer 113 Passivation SiO ₂ layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/12 Z 29/784

Claims (2)

[Claims] 1. A first P-type MOS transistor having a gate electrode connected to an input signal line and a source electrode connected to a power supply line, and a gate electrode connected to a first clock signal line and a source electrode. Is connected to the drain electrode of the first P-type MOS transistor, and the drain electrode is connected to the output signal line; and the gate electrode is connected to the input signal line and the source electrode A first N-type MOS transistor connected to a ground line, a gate electrode connected to a second clock signal line having a phase opposite to that of the first clock signal line, and a source electrode connected to the first electrode. Of the second N-type MOS transistor connected to the drain electrode of the N-type MOS transistor and the drain electrode of which is connected to the output signal line. In over-capacitor circuit, the second N-type MOS transistor, the clocked inverter circuit, characterized in that one MOS transistor of the offset gate structure or a MOS transistor of the lightly doped drain structure. 2. A first P-type MOS transistor having a gate electrode connected to an input signal line and a source electrode connected to a power supply line, and a gate electrode connected to a first clock signal line and a source electrode. Is connected to the drain electrode of the first P-type MOS transistor, and the drain electrode is connected to the output signal line; and the gate electrode is connected to the input signal line and the source electrode A first N-type MOS transistor connected to a ground line, a gate electrode connected to a second clock signal line having a phase opposite to that of the first clock signal line, and a source electrode connected to the first electrode. Of the second N-type MOS transistor connected to the drain electrode of the N-type MOS transistor and the drain electrode of which is connected to the output signal line. In over-capacitor circuit, the channel length of the second N-type MOS transistor, the clocked inverter circuit being greater than the channel length of the first N-type MOS transistor.