JPH05259790A - Subminiature electromagnetic delay line - Google Patents

Abstract

PURPOSE:To obtain a subminiature lumped constant type electromagnetic delay line offering ease of chip processing. CONSTITUTION:An inductor element 25 having plural taps 25c is formed by winding a conductor wire to a thin long and flat insulation bobbin 27. A common electrode 29b is formed to one side of a chip dielectric board 29a and a capacitor array 29 having plural split electrodes 29c with a prescribed pitch is formed to an opposite face. A lead frame 33 is formed, in which the common electrode 29b and an input electrode plate 35 and an output electrode plate 37 having the electrode 29b inbetween are provided. The capacitor array 29 is fixed by overlapping the common electrode 29b onto the common electrode plate 31. Both ends 25a, 25b of the inductance element 25 and plural taps 25c are connected to input output electrode plates 35, 37 and the split electrode 29 and the inductance element 25 is overlapped and fixed on to the capacitor array 29 via an insulation sheet 39.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lumped-constant type ultra-small electromagnetic delay line, and more particularly to improvement of an electromagnetic delay line which can obtain a large amount of delay at an ultra-high speed.

[0002]

2. Description of the Related Art Generally, a lumped-constant type electromagnetic delay line has a structure in which a plurality of taps provided on an inductance element formed by winding a conductor is connected to a chip capacitor in a ladder shape to have a plurality of sections. However, since the circuit configuration of about 10 sections is standard, 9 or 11 chip capacitors are required for practical use, and it is necessary to place them at intervals so that adjacent chip capacitors do not touch each other. Therefore, it has been difficult to reduce the size significantly and reduce the cost.

Therefore, the Applicant has proposed that US Pat.
We proposed an electromagnetic delay line as shown in No. 9,356. In this electromagnetic delay line, as shown in FIG. 16, one side of the rectangular relay substrate 1 is provided with a pair of first input / output electrodes.
Relay electrodes 3 and 5 and a plurality of second relay electrodes 7 are formed between these first relay electrodes 3 and 5 with a space therebetween, and an inductance element in which a lead wire is wound around an elongated flat bobbin 9 for a plurality of sections. 11 is formed.

Both ends 11 of the inductance element 11
a, 11b and the tap 11c are soldered and connected to the first relay electrodes 3, 5 and the second relay electrode 7 at one long side portion of the relay substrate 1, and between the first relay electrodes 3, 5. The elongated capacitor array 13 is soldered and connected to the first relay electrodes 3 and 5 and the second relay electrode 7 so as to pass. Further, the first relay electrodes 3 and 5 are extended to the long side portion of the relay substrate 1 opposite to the inductance element 11, and the connection electrode 15 is formed in the vicinity thereof, and the connection electrode 15 and the capacitor array 13 are connected to each other. 17
Input / output terminals 19 and 21 and a common terminal 23 are connected to the first relay electrodes 3 and 5 and the connection electrode 15.

The capacitor array 13 is shown in FIG.
As shown in A, the thin and elongated dielectric plate 13a has a common electrode 13b (located on the back side in FIG. 17A) on one entire surface, and the first relay electrodes 3 and 5 and the second relay electrode shown in FIG. Has a plurality of divided electrodes 13c at the arrangement pitch of the relay electrodes 7, and the divided electrodes 13c are soldered and connected so as to overlap the first relay electrodes 3 and 5 and the second relay electrode 7, and the electromagnetic delay The lines are made up. This capacitor array 13 has a relative dielectric constant of 100 or 200 and a side length of 25.
mm square ceramic dielectric plate is ground to a thickness of 0.2 mm, silver paste is printed on one side of the plate, and a blind-shaped (striped) pattern is printed on the opposite side to about 800 ° C.
17B, a large dielectric plate 13 having a common electrode (which is hidden on the back side in FIG. 17B) 13d formed on the entire one surface and a blind-shaped electrode 13e formed on the opposite surface, as shown in FIG. 17B.
It is formed by preparing f and cutting the electrode 13e slenderly as shown by a broken line.

In such an electromagnetic delay line, since the individual capacitors connected to both ends 11a and 11b of the inductance element 11 and the tap 11c are realized by one array component, the arrangement pitch of the divided electrodes 13c of the capacitor array 13 is set. Width of 4.4m by setting to about 0.7mm
Even if a small relay board 1 having m × 11 mm length is used, for example, 1
A circuit configuration of about 5 sections can be easily realized, and it has become possible to achieve high density and high performance while achieving miniaturization that cannot be obtained with the previous configuration of the electromagnetic delay line. Further, the electromagnetic delay line of FIG. 16 can be thinned by suppressing the thickness to 2.5 mm or less even if the whole is coated with an epoxy resin to be a product, so that it can be arranged at a high density together with an IC or the like.

[0007]

However, with the recent miniaturization of electronic equipment, not only active components such as ICs but also resistors,
The miniaturization of passive components such as capacitors and inductors is progressing, and further miniaturization of delay lines is required.
Moreover, electronic components are being made into chips to mount the electronic components on one surface of the circuit board to improve the assembling efficiency of electronic devices, and the delay lines are also required to be made into chips.

In this respect, in the above-mentioned electromagnetic delay line of FIG. 16, for example, the relay board 1 having a width of 4.4 mm and a length of 11 mm.
The product obtained by transfer molding with epoxy resin etc. is 5.4mm in width × 13 in length when made into chips using 1
Since it is about mm, it occupies a large area on the circuit board of the electronic device, and miniaturization is insufficient as a chip component. Therefore, the arrangement pitch of the divided electrodes 13c of the capacitor array 13 shown in FIG. 17A is changed from 0.7 mm described above to, for example, 0.5 mm, and the interval between the divided electrodes 13c is narrowed to about 0.1 mm to further reduce the size. The following problems arise when attempting to plot.

That is, it becomes extremely difficult to solder the divided electrode 13c with the divided electrode 13c facing downward so as to be aligned with the first relay electrode 3, 5 and the second relay electrode 7, and the divided electrode 13c of the capacitor array 13 and the divided electrode 13c. Even a slight deviation from the first relay electrodes 3, 5 and the second relay electrode 7 is not allowed. Furthermore, the split electrode 1 of the capacitor array 13
Since 3c has a variation that must be allowed in manufacturing, it becomes extremely difficult to reliably connect the divided electrode 13c to the first relay electrode 3, 5 and the second relay electrode 7, and the solder for connection is used. The amount also becomes delicate, and if there is any excess solder, it will run off from the divided electrodes 13c and cause solder bridges or bonding defects between the electrodes. Moreover, in many cases, they are hidden by the downward facing capacitor array 13 and cannot be seen.

Therefore, in the electromagnetic delay line of FIG. 16 described above, the pitch of the divided electrodes 13c of the capacitor array 13 is considered to be 0.7 mm, which is currently in practical use, at a value close to the limit. The present invention has been made in order to solve such a conventional problem, and provides an electromagnetic delay line in which the number of parts is extremely reduced, ultra-miniaturization is easy, and there is no problem in assembly. To aim.

[0011]

In order to solve such a problem, the present invention provides a capacitor element in which a plurality of divided electrodes are formed on one surface of a chip-shaped dielectric plate with a slight interval, and the divided capacitor element. A common electrode plate that supports the capacitor element by stacking opposing surfaces facing the electrodes, an input / output electrode plate arranged in a planar relationship with the common electrode plate around the common electrode plate, and a flat bobbin provided with a plurality of taps. An inductance element formed by winding a conductor wire on both ends of the conductor wire to the input / output electrode plate and the taps directly connected to the split electrodes, respectively. The capacitor element side or the common electrode plate side includes an inductance element stacked with an insulating sheet interposed therebetween.

Further, according to the present invention, the insulating sheet containing an adhesive material that exhibits viscosity when heated may be used, and the inductance element may be fixed to the capacitor element or the common electrode plate through the insulating sheet by heating. .. Further, the common electrode plate and the input / output electrode plate may be formed by a circuit pattern of a lead frame or a circuit board.

According to the present invention, a capacitor element in which a plurality of divided electrodes are formed on one surface of a chip-shaped dielectric plate with a slight interval, and one surface of the capacitor element is opposed to the divided electrodes. A common electrode plate supporting the surface,
An inductance element in which a conductor is wound around a flat bobbin so that multiple taps are provided, and both ends of the conductor and taps are connected to the split electrodes, and both ends and taps are folded so that the capacitor element side or common The inductance element, which is stacked on the electrode plate side via an insulating sheet, is supported by the common electrode plate, and both ends and taps of the conductor are directly or indirectly connected to control signal input / output to both ends and taps. And a plurality of input / output electrode plates connected to the integrated circuit and the common electrode plate which are arranged in a planar relationship with the common electrode plate around the common electrode plate and which are formed of a lead frame. be able to.

[0014]

In the present invention having such means, since the capacitor element is superposed and supported on the common electrode plate, the input / output electrode plate and the divided electrodes of the capacitor element are located at the same surface side and the inductance element. Both ends and the tap can be easily connected, and each can be directly connected. Moreover, since the inductance element is superposed on the capacitor element side or the common electrode plate side via the insulating sheet, the area becomes smaller and the area becomes thinner as a whole.

Further, in the structure using the insulating sheet containing the adhesive material that exhibits viscosity when heated, the inductance element is fixed to the capacitor element or the common electrode plate at a stable and constant interval. Further, the common electrode plate supports the capacitor element and the chip-shaped integrated circuit, the inductance element is connected to the capacitor element and the integrated circuit, and the integrated circuit and the common electrode plate are connected to a plurality of input / output electrode plates including lead frames. With this configuration, the common electrode plate can be formed as a part of the lead frame, and the active circuits connected to the outside can be collectively arranged on the common electrode plate, so that there is no need to arrange the active circuit outside.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are a schematic perspective view and a schematic exploded perspective view showing an embodiment of a microminiature electromagnetic delay line according to the present invention. In FIG. 1 and FIG. 2, the inductance element 25
Is formed by winding a conductive wire around the outer periphery of a slender flat insulating bobbin 27 and twisting a plurality of taps 25c from one end along the longitudinal direction of the bobbin 27 between one end 25a and the other end 25b. 16 is similar to the inductance element 11 of FIG. 16, but is smaller in dimension.

In actual production of the inductance element 25, instead of individually winding the bobbin 27, the plurality of inductance elements 25 are continuously arranged on the flat rod-shaped bobbin 27a as shown in FIG. 3 at a time, and after connecting a capacitor array 29 as a capacitor element in which a plurality of capacitors are combined as described later,
Each inductance element 25 is cut along the broken line in the figure.
Forming improves productivity. Returning to FIG. 1 and FIG. 2, the capacitor array 29 has a common electrode (located on the back side in the figure) 29b on one entire surface of a thin and long chip-shaped dielectric plate 29a, and has a predetermined arrangement pitch on the opposite surface. It has a plurality of divided electrodes 29c. This capacitor array 29 has a common electrode 29b placed on a common electrode plate 31 and is supported and fixed by bonding, and has a configuration similar to that of the capacitor array 13 shown in FIG.

In the capacitor array 29, a ceramic dielectric plate is thinned to a thickness of about 0.1 mm, and the divided electrodes 29c are formed.
Width of 0.4 mm and the distance between adjacent divided electrodes 29
The distance between c is narrowed to about 0.1 mm, for example, 0.5 mm
The divided electrodes 29c are arranged at a pitch. It should be noted that such a capacitor array 29 becomes unusable because the dielectric plate is warped when fired at a high temperature as shown in FIG. 17B described above, and it is difficult to secure the electrode spacing accuracy of 0.1 mm by the silver paste. For example, it is preferable to pattern copper, for example, with a thickness of 3 μm on the dielectric plate by a sputtering method.

Such a capacitor array 29 is significantly smaller than the size of the capacitor array 11 shown in FIG. For example, when considering a lumped-constant type electromagnetic delay line having a delay time of 10 ns and a characteristic impedance of 50Ω, the size required for the conventional capacitor array 11 (width 2.
A small size (width 1.5 mm x length 6.95 mm) can be realized for 3 mm x length 9.65 mm. The above-mentioned common electrode plate 31 that is in contact with the common electrode 29b and supports the capacitor array 29 is formed of a part of the lead frame 33.

That is, in a lead frame 33 elongated in one direction having a plurality of frame-shaped window portions 33a, the middle of the connecting piece 33b crossing the window portions 33a becomes wide to form a rectangular common electrode plate 31, and the lead frame is formed. The connecting piece 33b portion up to the main body 33 functions as a common terminal.
In addition, a pair of pieces are juxtaposed from the main body of the lead frame 33 side by side with the connecting piece 33b so as to face the vicinity of the common electrode 29b in the window 33a. Input electrode plate 3
5 and the output electrode plate 37. It goes without saying that the common electrode plate 31 and the input / output electrode plates 35, 37 are actually formed by cutting from the lead frame 33 at the locations shown by the broken lines in FIG.

Individual taps 25c of the inductance element 25 are connected, for example, by soldering, to one end side in the longitudinal direction of the divided electrodes 29c on the surface side of the capacitor array 29 supported by the common electrode plate 31. Input electrode plate 3
One end 25a of the inductance element 25 is attached to the tip of 5.
The other end 25b of the inductance element 25 is also soldered to the tip of the output electrode plate 37. In the drawings, the reference numerals of solder are omitted. Therefore, the input / output electrode plate 35,
The connecting portion between the inductance element 25 and 37 and the divided electrode 29c is located on one end side in the longitudinal direction of the capacitor array 29.

As shown in FIG. 4, the inductance element 25 is bent so that both ends 25a and 25b and the tap 25c are folded back to be stacked on the capacitor array 29, and is fixed by heating and pressure bonding via an insulating sheet 39. Thus, a chip-shaped microminiature electromagnetic delay line having a plurality of sections is configured. In FIG. 4, it is shown for the sake of convenience not being crimped. The insulating sheet 39 is, for example, a pellet (sheet) made of a thermoplastic epoxy resin as an adhesive, and if the inductance element 25 is placed on the capacitor array 29 and is thermocompression-bonded and cured, the inductance element 25 is fixed. Can be fixed at regular intervals.

The insulating sheet 39 need not contain an adhesive, and may be a simple insulating layer. However, if an adhesive is included, the inductance element 25 can be stably fixed on the capacitor array 29, and the characteristics are also stable. There are advantages. When commercializing the microminiature electromagnetic delay line of the present invention,
Finally, as shown in FIG. 5, the outer periphery is formed by transfer molding. Reference numeral 41 in the figure denotes a mold portion. The common electrode plate 31 and the input / output electrode plates 35 and 37 are cut from the lead frame 33 after transfer molding,
It serves as an external connection terminal board. Reference numeral 33b in FIG. 5 is a connecting piece portion left after cutting.

In the electromagnetic delay line having such a structure, only the minimum three main components required, that is, one inductance element 25 and capacitor array 29, and the common electrode plate 31 including the lead frame 33, and the like. Since it is composed of only the input / output electrode plates 35, 37, the number of parts is extremely small. In addition, the inductance element 25 includes the capacitor array 29, the common electrode plate 31, and the input / output electrode plate 3.
5, 37, which does not require the relay substrate 1 as in the configuration of FIG. 16 described above, but also has an electrode portion connecting the inductance element 11 and the first and second relay electrodes 3, 5, and 7. Since it is not necessary, the inductance element 25 is superposed on the capacitor array 29, so that the size is extremely small.

Therefore, it is possible to make the entire shape of the electromagnetic delay line ultra-small and to easily form a chip without requiring an extra part, an area, and an extra assembling process. In other words, when considering the structure of the electromagnetic delay line, it is considered that the number of parts, the size, and the assembly process have been simplified to the extent that they cannot be further reduced or simplified. Next, a method for manufacturing the above-mentioned electromagnetic delay line of the present invention will be briefly described. First, as shown in FIG. 2, both ends 25
An inductance element 25 having a and 25b and a tap 25c, a capacitor array 29 having a common electrode 29b and a divided electrode 29c are prepared.

On the other hand, the input / output electrode plates 35 and 37 are arranged on both sides of the common electrode plate 31, and the common electrode 29b is placed on the common electrode plate 31 to support and fix the capacitor array 29. Both ends 25a and 25b of the inductance element 25 and the tap 25c are soldered and connected to 37 and the divided electrode 29c. Then, the insulation sheet 39
Both ends 25a, 25b and tap 25c through the
The part is folded back and the inductance element 25 is superposed on the capacitor array 29, and a pressure is applied between the inductance element 25 and the capacitor array 29, and these are placed in a high temperature atmosphere to melt and harden the insulating sheet 39, so that the inductance element 25 becomes a capacitor. It is fixed to the array 29 to manufacture a microminiature electromagnetic delay line.

Then, the outer periphery is appropriately transfer-molded, and the common electrode plate 31 and the input / output electrode plates 35 and 37 are cut from the lead frame 33 to be commercialized. In such a manufacturing method, the divided electrodes 29c of the capacitor array 29 are used.
Is located on the surface side, the inductance element 11 can be directly connected to the capacitor array 29, the common electrode plate 31, and the input / output electrode plates 35, 37, and the connection state can be easily checked, and the manufacturing is simplified. The manufacturing yield is also improved.

In the above-mentioned electromagnetic delay line according to the present invention, the structure in which the inductance element 25 is superposed on the side of the capacitor array 29 has been described, but as shown in FIG. 6, in the present invention, the inductance element 25 is interposed via the insulating sheet 39. The inductance element 25 is similarly stacked on the lead frame 33 side.
It is also possible to heat-press the lead frame 33, that is, the common electrode plate 31 and the input / output electrode plates 35 and 37. In the electromagnetic delay line having such a structure, as shown in FIG. 7, when the common electrode plate 31 and the input / output electrode plates 35 and 37 are bent downward, for example, and the outer periphery is transfer-molded, a dual in-line (DIP) structure is formed. good. FIG. 8 is a perspective view of the final product after transfer molding.

Further, in the electromagnetic delay line of the present invention, as shown in FIG. 9, the common electrode plate 31a and the input / output electrode plates 35a and 37a are provided in the window portion 33a from the same side of the window portion 33a of the lead frame 33. The common electrode plate 31 is projected by the length.
The capacitor array 29 is fixed to the wide portion of a, and the input / output electrode plates 35a, 37a and the split electrode 29 of the capacitor array 29 are attached to the tip ends of the input / output electrode plates 35a, 37a.
An inductance element 25 is connected to c to form a single in-line (SIP) type structure. Further, as shown in FIG. 10, a common electrode plate 31b that is the same as the common electrode plate 31a that projects from the same side facing the window 33a of the lead frame 33, and input / output electrode plates 35b and 37b that are shorter than the common electrode plate 31b. Form and short input / output electrode plate 35
A SIP configuration in which the inductance element 25 is connected to the electrodes b, 37b and the divided electrode 29c is also possible.

By the way, the divided electrodes 29c of the capacitor array 29 and the input / output electrode plates 35, 35a, 35b, 3 are provided.
It is easier to connect the inductance element 25 by an automatic machine if the respective surfaces of 7, 37a, 37b are arranged so as to be located on substantially the same plane. Therefore, the common electrode plates 31, 31a
And input / output electrode plates 35, 35a, 35b, 37, 37a,
Even if 37b is arranged up and down to some extent, it is within the scope of the present invention. Although the above-described embodiments are examples in which the lead frame 33 is used, the present invention is not necessarily limited to the example in which the lead frame 33 is used, and the common electrode plate 31 and the input / output electrode plates 35, 37 that are independent from the beginning are used. Can be formed with.

Further, as shown in FIG. 11, the circuit board 43
By using the common electrode plate 31c and the input / output electrode plate 35c,
37c is formed by the circuit pattern of the circuit board 43, and the input / output electrode plates 35c, 37c are connected to the input / output terminals 45, 4
A SIP configuration in which 7 is connected and the common terminal 49 is connected to the common electrode plate 31c is also possible. In this configuration, the circuit board 4
3 may be used, the outer diameter shape may be slightly increased, but the inductance element 25 is replaced by the capacitor array 29.
And common electrode plate 31c and input / output electrode plates 35c, 37c
Since it can be directly connected to the capacitor array 29, it is much smaller than the configuration of FIG.
It is possible to check the connection state without worrying about the displacement of the connection position, and the manufacturing yield is good.

Next, an application example of the electromagnetic delay line according to the present invention will be described. In each of the above-described embodiments, the common electrode plates 31, 31a, 31b formed on the lead frame 33 and the circuit board 43 are formed.
In the present invention, the common electrode plate 31c also supports the capacitor array 29. However, in the present invention, the common electrode plate 31c also supports the chip-shaped integrated circuit, and this integrated circuit delays the tap 25c of the inductance element 25 from the tap 25c. It is possible to output or input signals with different times.

That is, as shown in FIG. 12, the lead frame 51 is punched so that the rectangular common electrode plate 51a and the common electrode plate 51a extend radially from the vicinity of both long sides of the common electrode plate 51a. It integrally has a plurality of arranged input / output electrode plates 51b and 51c. The common electrode 29b of the capacitor array 29 shown in FIG. 2 is bonded to the common electrode plate 51a of the lead frame 51, and the capacitor array 29 is supported and fixed thereto. At each end of the divided electrode 29c of the capacitor array 29, the inductance element 25 as shown in FIG.
Both ends 25a, 25b and the tap 25c are connected by soldering.

On the common electrode plate 51a of the lead frame 51, for example, a chip-shaped integrated circuit (IC bare chip) 53 having a plurality of inverters I integrated as shown in FIG. It is supported and fixed along. The inductance element 25 and the integrated circuit 53 are connected to the tap 25c so that the output side of one inverter I in the integrated circuit 53 is connected to the input terminal of the inductance element 25 and the input side of the other inverter I is connected to the tap 25c. Connected by. Integrated circuit 53 and a plurality of input / output electrode plates 51 arranged in the vicinity thereof
b is connected by a gold wire 55, and the input side of one inverter I and the output side of another inverter I are connected to these input / output electrode plates 51b.

A terminating resistor 57 connected to the end of the inductance element 25 is fixed to the common electrode plate 51a of the lead frame 51 so as to come close to the terminating end, and one end of the terminating resistor 57 is an inductance with a gold wire 55. It is connected to the end of the element 25 and the terminating resistor 5
The other end of 7 is directly connected to the common electrode plate 51a by a gold wire 55. The common electrode plate 51a is an input / output electrode plate 5 opposite to the input / output electrode plate 51b to which the integrated circuit 53 is connected.
It is integrally connected to one of 1c.

The inductance element 25 has two ends 2
5a, 25b and tap 25c are bent so as to be folded back and stacked on the capacitor array 29, and the capacitor array 29 and the integrated circuit 5 are stacked via an insulating sheet (not shown).
An electromagnetic delay line having a plurality of sections is formed by being thermocompression-bonded and fixed to No. 3. However, the inductance element 2
5 can be heat-pressed to one of the capacitor array 29 or the integrated circuit 53, or may be folded back to the common electrode plate 51a side and heat-pressed. It should be noted that in FIG. 12, the inductance element 25 is arranged at both ends 25a and 25b and the tap 25.
It is shown in a state before the part c is not folded back.

Common electrode plate 51a and input / output electrode plate 51
b and 51c are actually cut from the main body of the lead frame 51 at the locations indicated by the broken lines in FIG. 12, the input / output electrode plates 51b and 51c are bent downward, and the outer periphery is transferred as shown in FIG. By molding, a surface mount type package (SOP) structure is obtained and commercialized. Reference numeral 61 in FIG. 15 is a mold portion, and FIG.
Then, the input / output electrode plate 51c is hidden and invisible. In the configuration in which the integrated circuit 53 together with the capacitor array 29 is supported on the common electrode plate 51a of the lead frame 51, a signal input (In) from the input side of one inverter I is input to the inductance element 25 as shown in FIG. A delay signal with a delay time corresponding to the number of sections from the input end is output (Out) from each tap 25c via the inverter I and the input / output electrode plate 51b, and propagates to the other end of the inductance element 25. The generated signal is consumed by the terminating resistor 57. This configuration is called a so-called active delay line.

In this way, the electromagnetic delay line in which the common electrode plate 51a also supports the chip-shaped integrated circuit 53 together with the capacitor array 29 has the following advantages in addition to the effects of the configuration of FIG. That is, the lumped constant electromagnetic delay line could not be formed directly on the lead frame, and when the integrated circuit in which the active circuit such as the inverter I is integrated and the electromagnetic delay line are connected and used, the conventional structure is used. Since the premolded integrated circuit was mounted on and connected to the printed circuit board such as the relay board 1 shown in FIG. 16 described above, the overall shape could not be downsized.

However, in the configuration of the present invention, the chip-shaped integrated circuit 53 is also supported by the common electrode plate 51a together with the capacitor array 29, and the integrated circuits before molding are collectively arranged on the common electrode plate 51a and built-in. Therefore, the configuration including the active circuit becomes extremely small, and the number of parts is reduced when the electromagnetic delay line is used in electronic equipment. Further, in the electromagnetic delay line that also supports the integrated circuit 53 on the common electrode plate 51a, it is possible to obtain an arbitrary delay circuit configuration depending on the configuration of the integrated circuit 53. For example, in FIG.
4, the inverter I in the integrated circuit 59 including the inverter I and the multiplexer M is connected to the input terminal of the inductance element 25, and the inductance element 2
Each tap 25c of 5 is connected to the multiplexer M, each tap 25c of the inductance element 25 is selected by the bit configuration of the digital signal applied to the control terminals D0, D1, and D2 of the multiplexer M, and the delay from the selected tap 25c is selected. A signal can be output. Such a configuration of FIG. 14 is called a so-called programmable delay line.

[0040]

As described above, according to the present invention, a chip-shaped capacitor element having a plurality of divided electrodes on one surface,
A common electrode plate that supports the capacitor elements so that the surfaces facing the split electrodes overlap each other, an input / output electrode plate arranged in a planar relationship with the common electrode plate, and a plurality of taps at both ends of which the input / output is provided. The electrode plate has an inductance element in which a tap is directly connected to each of the divided electrodes, and both ends of the element and the tapped portion are folded back so that the inductance is provided to the capacitor element side or the common electrode plate side through an insulating sheet. Since the elements are stacked, the number of parts is extremely small, and the inductance element is directly connected to the capacitor element and the common terminal plate and the input / output electrode plate.
The electromagnetic delay line is extremely thin and has a small area, and it is easy to form a chip, and the manufacturing yield is high. Moreover, since the divided electrodes of the capacitor element are located on the front surface side without being hidden behind, there is an advantage that a reliable connection with the inductance element is possible and the connection relationship can be easily confirmed. Further, in the configuration in which the inductance element is fixed through the insulating sheet containing an adhesive material that exhibits viscosity when heated, the inductance element can be stably fixed and the characteristics are also stable. Further, the common electrode plate supports the capacitor element and the chip-shaped integrated circuit, the inductance element is connected to the capacitor element and the integrated circuit, and the integrated circuit and the common electrode plate are connected to a plurality of input / output electrode plates including lead frames. In this configuration, the active circuits connected to the outside are collectively arranged on the common electrode plate, and a separate active circuit is not required outside, so the number of parts is reduced and the electronic device equipped with the electromagnetic delay line is made extremely small. can do.

[Brief description of drawings]

FIG. 1 is a schematic perspective view showing one embodiment of a microminiature electromagnetic delay line according to the present invention.

FIG. 2 is a schematic exploded view of the microminiature electromagnetic delay line of FIG.

FIG. 3 is a schematic plan view showing an example of a method for manufacturing the microminiature electromagnetic delay line of FIG.

FIG. 4 is a schematic side view of the microminiature electromagnetic delay line according to FIG.

FIG. 5 is an external perspective view showing an example of a microminiature electromagnetic delay line manufactured by the present invention.

FIG. 6 is a schematic side view showing another embodiment of the microminiature electromagnetic delay line according to the present invention.

FIG. 7 is a side view showing a state where the outer periphery of the microminiature electromagnetic delay line of FIG. 6 is molded (partially shown by an imaginary line).

8 is an external perspective view showing a state in which the outer periphery of the microminiature electromagnetic delay line of FIG. 7 is molded.

FIG. 9 is a schematic perspective view showing another embodiment of the microminiature electromagnetic delay line of the present invention.

FIG. 10 is a schematic perspective view showing another embodiment of the microminiature electromagnetic delay line of the present invention.

FIG. 11 is a schematic perspective view showing another embodiment of the microminiature electromagnetic delay line of the present invention.

FIG. 12 is a schematic perspective view showing an application example of the microminiature electromagnetic delay line of the present invention.

13 is a circuit diagram showing a configuration example of the microminiature electromagnetic delay line of FIG.

14 is a circuit diagram showing another configuration example of the microminiature electromagnetic delay line of FIG.

FIG. 15 is an external perspective view showing the state in which the microminiature electromagnetic delay line shown in FIG. 12 is molded.

FIG. 16 is a perspective view showing a conventional small electromagnetic delay line.

FIG. 17 is a capacitor array (A) suitable for a capacitor element forming an electromagnetic delay line and a manufacturing method (B) thereof.
It is a perspective view explaining.

[Explanation of symbols]

1 Relay Substrate 3, 5 First Relay Electrode 7 Second Relay Electrode 9, 27 Bobbin 11, 25 Inductance Element 11a, 11b, 25a, 25b Both Ends of Inductance Element 11c, 25c Inductor Tap 13, 29 Capacitor Element ( Capacitor array) 13a, 13f, 29a Dielectric plates 13b, 13d, 29b Common electrodes 13c, 29c Split electrodes 13e Electrodes 15 Connection electrodes 19, 21, 45, 47 Input / output terminals 23, 49 Common terminals 27a Rod-shaped bobbins 31, 31a, 31b, 31c, 51a Common electrode plate 33, 51 Lead frame 33a Window part 33b Connecting piece 35, 35a, 35b, 35c Input electrode plate 37, 37a, 37b, 37c Output electrode plate 39 Insulating sheet 41, 61 Mold part 43 Circuit board 51b, 51c I / O power Plate 53, 59 chip-like integrated circuit 55 gold wire 57 terminating resistors I inverters M multiplexer

Claims (6)

[Claims] 1. A capacitor element in which a plurality of divided electrodes are formed on one surface of a chip-shaped dielectric plate at a slight interval, and a facing surface of the capacitor element facing the one surface is formed so as to face the divided electrodes. A common electrode plate for supporting, an input / output electrode plate arranged in a planar relationship with the common electrode plate around the common electrode plate, and an inductance element in which a plurality of taps are provided and a conductive wire is wound around a flat bobbin, Both ends of the conducting wire are directly connected to the input / output electrode plate and the tap is directly connected to the split electrode, respectively, and the both ends and the tap are folded back so as to interpose an insulating sheet on the capacitor element side or the common electrode plate side. An ultra-compact electromagnetic delay line that includes a stack of inductance elements. 2. The microminiature according to claim 1, wherein the insulating sheet includes an adhesive material that exhibits viscosity when heated, and the inductance element is fixed to the capacitor element or the common electrode plate through the insulating sheet by heating. Electromagnetic delay line. 3. The microminiature electromagnetic delay line according to claim 1, wherein the common electrode plate and the input / output electrode plate are lead frames. 4. The microminiature electromagnetic delay line according to claim 1, wherein the common electrode plate and the input / output electrode plate are circuit patterns of a circuit board. 5. A capacitor element in which a plurality of divided electrodes are formed on one surface of a chip-shaped dielectric plate at a slight interval, and a facing surface of the capacitor element facing the one surface is formed so as to face the divided electrodes. A common electrode plate for supporting, and an inductance element formed by winding a conducting wire around a flat bobbin so as to provide a plurality of taps, and connecting both ends and the tap of the conducting wire to the split electrode, An inductance element, which is folded back and is stacked on the capacitor element side or the common electrode plate side via an insulating sheet, is directly or indirectly connected to both ends of the lead wire and the taps while being supported by the common electrode plate. And a chip-shaped integrated circuit for controlling input / output of signals to / from the both ends and the tap, and a lead frame. It is arranged in a planar relationship therewith to enclose the integrated circuit and a plurality of input and output electrode plates connected to the common electrode plate comprises a micro electromagnetic delay line. 6. The insulating sheet includes an adhesive that exhibits viscosity when heated, and the inductance element is fixed to the capacitor element and / or the integrated circuit or the common electrode plate through the insulating sheet when heated. The microminiature electromagnetic delay line according to claim 5.