JPH05259159A - Shape of wiring in semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To minimize the increase in parasitic capacitance produced in a wiring and prevent photoresist from falling on a semiconductor integrated circuit having wirings having constant widths on a semiconductor substrate by making at least one part of the wirings wider than the rest thereof. CONSTITUTION:A semiconductor integrate circuit device has wirings 1 and 2 having constant widths on a semiconductor substrate. At least one part 20 of the wirings 1 and 2 is made wider than the rest thereof. Or, parts 20 of the wirings 1 and 2 are made wider than the rest thereof with the wider parts 20 of one 2 of the adjacent wirings shifted in position from those of the other in the wiring longitudinal direction. For example, in a wiring pattern 2 of a minimum wiring width, parts are formed 20 with the cross-sectional width approx. 1.5 to 2 times the thicknesses and length several mum lengths at a specified interval. Or, the position of the parts 20 of a larger width is, in addition, shifted in the lengthwise direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to improvement of the shape of wiring close to the minimum wiring width.

[0002]

2. Description of the Related Art As shown in FIGS. 3 and 4, a wiring pattern in a conventional semiconductor integrated circuit device has a large number of portions set to have a constant thickness. In particular, the wiring connecting the active element to the active element has a constant width determined by the semiconductor integrated circuit device of several 100 μm to several 1000 μm.
It is formed over m.

The width of the wiring is determined by factors such as the magnitude of the current flowing through the wiring and the resistance of the wiring. Then, regarding the wiring of the signal in which this factor does not cause any particular problem, it is formed close to the minimum wiring width in the semiconductor integrated circuit device in order to make the parasitic capacitance as small as possible. Alternatively, in order to improve the degree of integration, the wiring is formed so as to have the minimum wiring width and spacing.

Regarding the thickness of the wiring layer, thinning the wiring layer reduces the cross-sectional area and increases the current density. Then, since it becomes worse against electromigration, the thickness is not changed even if the minimum line width is reduced.

[0005]

FIG. 5 shows a state after the photoresist 3 is patterned. Recently, since the wiring width is about 0.6 to 0.8 μm, the width of the photoresist 3 is necessarily 0.6.
.About.0.8 .mu.m, the thickness is determined by the thickness of the wiring layer, and the thickness is about 1 to 3 .mu.m. In FIG. 5, the case where the width is 0.8 μm and the thickness is 2 μm is shown as an example. Thus, the photoresist 3 has a vertically long cross-sectional shape, and in an extreme case, the photoresist 3 collapses when etching the wiring layer, and even up to the portion where the wiring layer under it is left. There was a problem that the peach was etched.

This problem becomes more remarkable as the linear portion of the wiring pattern becomes longer, and as shown in FIG. 5, when the wiring layer 4 is provided in parallel with the lower two wiring layers 8, a photoresist is formed due to a step. However, the thickness of the photoresist 3 becomes inevitably increased, and the cross-sectional shape of the photoresist 3 becomes more vertically long, which also leaves a problem.

To prevent this, the width of the wiring should be increased so that the photoresist does not fall over, but this causes a problem that the parasitic capacitance increases.

The present invention has been proposed in view of the above problems of the prior art, and in a semiconductor integrated circuit in which a wiring extending in one direction with a constant width is provided on a semiconductor substrate, parasitic capacitance attached to the wiring is provided. It is intended to suppress the increase of the photoresist to a minimum and prevent the photoresist from falling down.

[0009]

According to the present invention, in a semiconductor integrated circuit in which a wiring extending in one direction with a constant width is provided on a semiconductor substrate, a part of the wiring is provided with at least one wide portion. It is characterized by

[0010]

Since the wiring has a narrow wiring width as a whole, it is possible to suppress an increase in parasitic capacitance and prevent the photoresist from falling due to the presence of the wide portion.

[0011]

EXAMPLE A first example of the present invention will be described. Figure 1
FIG. 3 is a plan view of the first embodiment, in which two wiring patterns 2 using the minimum wiring width of the present invention exist between the wiring patterns 1 on both sides. The width of the cross section of each of these wiring patterns 2 is set to be 1.5 to 2 times the thickness, and the wide portions 20 whose length is set to several μm are spaced at predetermined intervals. Has been formed. The presence of the wide portion 20 prevents the photoresist from falling.

In the first embodiment described above, the wide portions 20 formed on the wiring patterns 2 having the minimum line widths are provided at positions facing each other, but in the second embodiment, as shown in FIG. The wide portions formed in the wiring pattern 2 having the minimum line width are positioned so as to be displaced from each other in the longitudinal direction.
As a result, both wiring patterns 2 can be brought close to each other,
It is possible to narrow the interval between the wiring patterns 2.

[0013]

As described above, according to the present invention, in a semiconductor integrated circuit device provided with a wiring extending in one direction on a semiconductor substrate with a constant width, a wide portion is provided in a part of the wiring. As a result, it is possible to effectively prevent the photoresist from collapsing while suppressing an increase in the parasitic capacitance of the wiring to the minimum.

Further, even when the remaining width of the photoresist becomes narrow due to manufacturing variations, it is possible to prevent the photoresist from falling.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a plan view showing a second embodiment of the present invention.

FIG. 3 is a plan view showing conventional wiring.

FIG. 4 is a cross-sectional view showing a conventional wiring.

FIG. 5 is a cross-sectional view showing a state after patterning of a photoresist according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Wiring 2 ... Wiring of this invention 3 ... Photoresist after patterning 20 ... Wide part

Claims (2)

[Claims] 1. A semiconductor integrated circuit device having a wiring extending over a semiconductor substrate with a constant width, wherein at least one wide portion having a predetermined size is formed in a part of the wiring. A wiring shape in a semiconductor integrated circuit device characterized in that. 2. A semiconductor integrated circuit device having a wiring extending on a semiconductor substrate with a constant width, wherein a wide portion is formed in a part of the wiring, and the wide portion of the adjacent wiring is formed. A wiring shape in a semiconductor integrated circuit device, wherein the wiring shapes are provided at positions displaced in the wiring longitudinal direction.