JPH05243476A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05243476A JPH05243476A JP7542892A JP7542892A JPH05243476A JP H05243476 A JPH05243476 A JP H05243476A JP 7542892 A JP7542892 A JP 7542892A JP 7542892 A JP7542892 A JP 7542892A JP H05243476 A JPH05243476 A JP H05243476A
- Authority
- JP
- Japan
- Prior art keywords
- island
- semiconductor device
- lead
- metal plate
- thin plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子を搭載したア
イランドと内部リードを有するリードフレームを含む樹
脂封止形半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device including an island on which a semiconductor element is mounted and a lead frame having internal leads.
【０００２】[0002]
【従来の技術】半導体装置はその大容量化により半導体
素子から発生する熱量が多くなっていることから、半導
体パッケージの熱をいかに外部に逃がすかが技術課題に
なっている。図５は従来の樹脂封止形半導体装置の構造
を示す平面図および断面図である。図６は細線結線部分
の拡大図である。リードフレーム２のアイランド１部に
半導体素子４は固着されており、半導体素子の電極部と
リードフレームの内部リード３の先端は細線５で結線さ
れている。半導体装置動作時の熱を逃がすために、アイ
ランドおよび内部リード先端部の裏面には熱伝導率の高
い金属、例えば銅の薄板を非導電性の樹脂シート６を介
して貼り付けた構造を採用している。樹脂シート６は金
属板７とリードとが電気的に短絡するのを防止するため
に設けたものである。なお、図中では樹脂部は省略され
ているが、半導体装置の構造としては素子，細線，内部
リード，アイランド等すべて樹脂封止された構造となっ
ている。2. Description of the Related Art A semiconductor device has a large amount of heat generated from a semiconductor element due to its large capacity. Therefore, how to dissipate the heat of a semiconductor package to the outside has become a technical issue. FIG. 5 is a plan view and a sectional view showing the structure of a conventional resin-sealed semiconductor device. FIG. 6 is an enlarged view of a thin wire connection portion. The semiconductor element 4 is fixed to the island 1 portion of the lead frame 2, and the electrode portion of the semiconductor element and the tip of the internal lead 3 of the lead frame are connected by a thin wire 5. In order to dissipate heat during operation of the semiconductor device, a structure is used in which a thin plate of metal with high thermal conductivity, such as copper, is attached to the back surface of the tip of the island and the inner lead via a non-conductive resin sheet 6. ing. The resin sheet 6 is provided to prevent an electrical short circuit between the metal plate 7 and the lead. Although the resin portion is omitted in the figure, the semiconductor device has a structure in which all elements, thin wires, internal leads, islands, etc. are resin-sealed.
【０００３】[0003]
【発明が解決しようとする課題】さて、従来の半導体装
置は放熱効果を高めるために貼付されている金属板が樹
脂シートを介して貼り付けられているため内部リードが
柔らかい樹脂シート上に位置する構造となっている。こ
のため、半導体素子と内部リードをボンディングすると
きのボンディング荷重や超音波振動のエネルギーが逃
げ、適切なボンディングを行われず、ワイヤのボンディ
ング強度が低下するという不具合があった。従来、この
ような構造のリードに対してのワイヤボンディング条件
は超音波振動を通常の２倍のパワーをかけて行わなけれ
ば接合が起こらない。しかし、超音波振動パワーを２倍
にすることはワイヤがボンディングのネック部で切れ易
くなるという問題が生じていた。本発明の目的は上記問
題を解決するもので、ボンディングの荷重や超音波の力
をロスすることなくボンディングすることができ、ボン
ディングしたワイヤとリードの接合強度が高く安定な半
導体装置を提供することにある。In the conventional semiconductor device, the internal leads are located on the soft resin sheet because the metal plate attached to enhance the heat dissipation effect is attached via the resin sheet. It has a structure. Therefore, the bonding load and the energy of ultrasonic vibration when bonding the semiconductor element and the internal lead escape, the proper bonding is not performed, and the bonding strength of the wire is lowered. Conventionally, under the wire bonding conditions for the lead having such a structure, the ultrasonic vibration is applied at a power twice as high as usual, and the bonding does not occur. However, doubling the ultrasonic vibration power causes a problem that the wire is easily broken at the bonding neck portion. An object of the present invention is to solve the above problems, and to provide a stable semiconductor device in which bonding can be performed without loss of bonding load or ultrasonic force, and the bonding strength between a bonded wire and a lead is high. It is in.
【０００４】[0004]
【課題を解決するための手段】前記目的を達成するため
に本発明による半導体装置は素子搭載用アイランドと、
前記アイランドの周囲に配置された内部リードを有する
リードフレームを含む樹脂封止形半導体装置において、
前記アイランドと前記内部リードの先端部分を、セラミ
ック薄板と非導電性の樹脂シートと熱伝導率の高い金属
板をこの順番で形成した３層構造部に搭載して構成して
ある。また、本発明は素子搭載用アイランドと、前記ア
イランドの周囲に配置された内部リードを有するリード
フレームを含む樹脂封止形半導体装置において、前記ア
イランド裏面は樹脂シートと金属板との２層構造部に貼
り付けられ、前記内部リードの先端部分は前記２層構造
部の上に搭載したセラミック薄板の上に貼付して構成し
てある。さらに本発明は素子搭載用アイランドと、前記
アイランドの周囲に配置された内部リードを有するリー
ドフレームを含む樹脂封止形半導体装置において、前記
アイランドと前記内部リードの先端部分の裏面に、セラ
ミック薄板と熱伝導率の高い金属板をこの順番に形成し
た２層構造部に貼り付けて構成してある。To achieve the above object, a semiconductor device according to the present invention comprises an element mounting island,
In a resin-sealed semiconductor device including a lead frame having internal leads arranged around the island,
The island and the tip of the internal lead are configured by mounting a ceramic thin plate, a non-conductive resin sheet, and a metal plate having a high thermal conductivity in this order in a three-layer structure. Further, according to the present invention, in a resin-sealed semiconductor device including an element mounting island and a lead frame having internal leads arranged around the island, the back surface of the island has a two-layer structure portion of a resin sheet and a metal plate. And the tip portions of the internal leads are attached on a ceramic thin plate mounted on the two-layer structure portion. Furthermore, the present invention provides a resin-sealed semiconductor device including an element mounting island and a lead frame having internal leads arranged around the island, wherein a ceramic thin plate is formed on the back surface of the tip of the island and the internal lead. A metal plate having a high thermal conductivity is attached to the two-layer structure portion formed in this order.
【０００５】[0005]
【実施例】以下、図面を参照して本発明をさらに詳しく
説明する。図１（ａ）および（ｂ）は本発明による半導
体装置の実施例を示す平面図および断面で示した側面図
である。また、図２は図１（ｂ）の部分拡大図である。
半導体素子４を搭載したアイランド１と内部リード３
が、放熱のための金属板７の上に樹脂シート６とセラミ
ック薄板８を介して搭載されている。セラミック薄板８
の材質としてはアルミナまたは低融点鉛ガラスが適して
いる。各層間は接着剤により貼付されている。なお、セ
ラミック薄板として低融点鉛ガラスを用いる場合にはア
イランドおよびリードと、低融点ガラスとはガラスを溶
融することにより接着することが可能であり、接着剤は
不要である。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail below with reference to the drawings. 1A and 1B are a plan view and a cross-sectional side view showing an embodiment of a semiconductor device according to the present invention. 2 is a partially enlarged view of FIG. 1 (b).
Island 1 with semiconductor element 4 and internal leads 3
Are mounted on the metal plate 7 for heat dissipation via the resin sheet 6 and the ceramic thin plate 8. Ceramic thin plate 8
Alumina or low melting point lead glass is suitable for the material. The layers are attached with an adhesive. When low melting point lead glass is used as the ceramic thin plate, the island and the lead can be bonded to the low melting point glass by melting the glass, and no adhesive is required.
【０００６】図３は本発明の第２の実施例を示す部分拡
大図である。セラミック薄板１８が内部リード３の裏面
にあたる部分にのみ貼り付けられており、アイランド１
の裏面は樹脂シート６と金属板７との２層で構成されて
いる。他の構成部分は図１と変わらない。FIG. 3 is a partially enlarged view showing the second embodiment of the present invention. The ceramic thin plate 18 is attached only to the portion corresponding to the back surface of the inner lead 3, and the island 1
The back surface of is composed of two layers of a resin sheet 6 and a metal plate 7. The other components are the same as in FIG.
【０００７】図４は本発明の第３の実施例を示す部分拡
大図である。金属板７とセラミック薄板２８の２層で構
成された部分にアイランド１と内部リード３が貼り付け
られている。この場合のセラミック材料としては、やは
り低融点ガラスが用いられ、接着剤を用いずに融着で貼
り付ける。他の構成は図１と変わらない。FIG. 4 is a partially enlarged view showing the third embodiment of the present invention. The island 1 and the internal leads 3 are attached to a portion formed by two layers of the metal plate 7 and the ceramic thin plate 28. As the ceramic material in this case, glass with a low melting point is also used, which is adhered by fusion without using an adhesive. Other configurations are the same as those in FIG.
【０００８】[0008]
【発明の効果】以上、説明したように本発明はアイラン
ドおよび内部リード裏面に放熱を促進するための金属板
を樹脂シートを介して貼る構造に、さらに樹脂シートと
内部リードの間に硬度の高い非導電性物質であるセラミ
ック薄板を貼ってあるので、内部リードのボンディング
性を安定させることができる。すなわち、内部リードの
裏面に硬度が高い物質を具備することにより、ボンディ
ングの荷重や超音波の力のロスすることなくボンディン
グすることができ、ボンディングしたワイヤとリードの
接合強度が高く安定した品質を得ることができる。従来
の構造のリードにワイヤボンディングするときに約５０
％の超音波振動パワーでワイヤ接合が可能であり、した
がって過剰な超音波振動によるワイヤのボンディングネ
ック部の破断不良が低減化される。As described above, the present invention has a structure in which a metal plate for promoting heat dissipation is attached to the back surface of the island and the inner lead via the resin sheet, and the hardness between the resin sheet and the inner lead is high. Since the ceramic thin plate, which is a non-conductive substance, is attached, the bondability of the internal leads can be stabilized. That is, by providing a material having a high hardness on the back surface of the internal lead, it is possible to perform bonding without loss of bonding load or ultrasonic force, and the bonding strength between the bonded wire and the lead is high and stable quality is obtained. Obtainable. Approximately 50 when wire-bonding to the lead of conventional structure
%, The wire can be bonded with ultrasonic vibration power, and therefore, the breakage failure of the bonding neck portion of the wire due to the excessive ultrasonic vibration is reduced.
【０００９】第２の実施例によれば、上記効果に加えて
半導体素子から発生する熱が金属板まで伝導する際の障
壁が少なく、第１の実施例より高い熱伝導性が得られ
る。また、広い面積を有するアイランドをセラミック薄
板に固着すると、その熱伝導率の違いからくる内部応力
の差で剥離が起こる場合が想定されるが、この実施例で
はその不具合を回避することができる。また、第３の実
施例によれば、リードの裏面には樹脂シートが全く存在
しないため、ボンディングの荷重や超音波の力は全く損
なわれず、安定したワイヤ接合品質が得られる。According to the second embodiment, in addition to the above effects, there are few barriers when the heat generated from the semiconductor element is conducted to the metal plate, and a higher thermal conductivity than that of the first embodiment can be obtained. Further, when an island having a large area is fixed to the ceramic thin plate, peeling may occur due to the difference in internal stress due to the difference in thermal conductivity, but this problem can be avoided in this embodiment. Further, according to the third embodiment, since the resin sheet does not exist on the back surface of the lead at all, the bonding load and the ultrasonic wave force are not impaired at all, and stable wire bonding quality can be obtained.
【図１】本発明による半導体装置の実施例を示す平面図
および断面で示した側面図である。1A and 1B are a plan view and a side view showing a cross section showing an embodiment of a semiconductor device according to the present invention.
【図２】図１（ｂ）の部分拡大図である。FIG. 2 is a partially enlarged view of FIG. 1 (b).
【図３】本発明による半導体装置の第２の実施例を示す
部分拡大図である。FIG. 3 is a partial enlarged view showing a second embodiment of the semiconductor device according to the present invention.
【図４】本発明による半導体装置の第３の実施例を示す
部分拡大図である。FIG. 4 is a partial enlarged view showing a third embodiment of the semiconductor device according to the present invention.
【図５】従来の半導体装置の一例を示す平面図および断
面で示した側面図である。5A and 5B are a plan view and a cross-sectional side view showing an example of a conventional semiconductor device.
【図６】図５（ｂ）の部分拡大図である。FIG. 6 is a partially enlarged view of FIG. 5 (b).
１…アイランド ２…リードフレーム ３…内部リード ４…半導体素子 ５…ワイヤ ６…樹脂シート ７…金属板 ８，１８，２８…セラミック薄板 DESCRIPTION OF SYMBOLS 1 ... Island 2 ... Lead frame 3 ... Internal lead 4 ... Semiconductor element 5 ... Wire 6 ... Resin sheet 7 ... Metal plate 8, 18, 28 ... Ceramic thin plate
Claims (3)
ドの周囲に配置された内部リードを有するリードフレー
ムを含む樹脂封止形半導体装置において、 前記アイランドと前記内部リードの先端部分を、セラミ
ック薄板と非導電性の樹脂シートと熱伝導率の高い金属
板をこの順番で形成した３層構造部に搭載したことを特
徴とする半導体装置。1. A resin-sealed semiconductor device including an element mounting island and a lead frame having internal leads arranged around the island, wherein the island and the tip of the internal lead are not connected to a ceramic thin plate. A semiconductor device comprising a conductive resin sheet and a metal plate having a high thermal conductivity, which are mounted on a three-layer structure formed in this order.
ドの周囲に配置された内部リードを有するリードフレー
ムを含む樹脂封止形半導体装置において、 前記アイランド裏面は樹脂シートと金属板との２層構造
部に貼り付けられ、前記内部リードの先端部分は前記２
層構造部の上に搭載したセラミック薄板の上に貼付した
ことを特徴とする半導体装置。2. A resin-sealed semiconductor device including an element mounting island and a lead frame having internal leads arranged around the island, wherein the back surface of the island has a two-layer structure portion of a resin sheet and a metal plate. Affixed to the inner lead of the inner lead
A semiconductor device characterized by being stuck on a ceramic thin plate mounted on a layer structure part.
ドの周囲に配置された内部リードを有するリードフレー
ムを含む樹脂封止形半導体装置において、 前記アイランドと前記内部リードの先端部分の裏面に、
セラミック薄板と熱伝導率の高い金属板をこの順番に形
成した２層構造部に貼り付けたことを特徴とする半導体
装置。3. A resin-sealed semiconductor device including an element mounting island and a lead frame having an internal lead arranged around the island, wherein the island and the back surface of the tip portion of the internal lead are:
A semiconductor device characterized in that a ceramic thin plate and a metal plate having a high thermal conductivity are attached to a two-layer structure formed in this order.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7542892A JP2833916B2 (en) | 1992-02-26 | 1992-02-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7542892A JP2833916B2 (en) | 1992-02-26 | 1992-02-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05243476A true JPH05243476A (en) | 1993-09-21 |
| JP2833916B2 JP2833916B2 (en) | 1998-12-09 |
Family
ID=13575936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7542892A Expired - Fee Related JP2833916B2 (en) | 1992-02-26 | 1992-02-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2833916B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008181926A (en) * | 2007-01-23 | 2008-08-07 | Rohm Co Ltd | Resin-sealed electronic component |
| WO2012137439A1 (en) | 2011-04-05 | 2012-10-11 | パナソニック株式会社 | Encapsulated semiconductor device and method for producing same |
| JPWO2015145752A1 (en) * | 2014-03-28 | 2017-04-13 | 三菱電機株式会社 | Semiconductor module and drive device mounted with semiconductor module |
-
1992
- 1992-02-26 JP JP7542892A patent/JP2833916B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008181926A (en) * | 2007-01-23 | 2008-08-07 | Rohm Co Ltd | Resin-sealed electronic component |
| WO2012137439A1 (en) | 2011-04-05 | 2012-10-11 | パナソニック株式会社 | Encapsulated semiconductor device and method for producing same |
| US9030003B2 (en) | 2011-04-05 | 2015-05-12 | Panasonic Intellectual Property Management Co., Ltd. | Encapsulated semiconductor device and method for manufacturing the same |
| US9240369B2 (en) | 2011-04-05 | 2016-01-19 | Panasonic Intellectual Property Management Co., Ltd. | Encapsulated semiconductor device and method for manufacturing the same |
| JPWO2015145752A1 (en) * | 2014-03-28 | 2017-04-13 | 三菱電機株式会社 | Semiconductor module and drive device mounted with semiconductor module |
| US10373896B2 (en) | 2014-03-28 | 2019-08-06 | Mitsubishi Electric Corporation | Semiconductor module and drive device equipped with semiconductor module |
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| Publication number | Publication date |
|---|---|
| JP2833916B2 (en) | 1998-12-09 |
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