JPH05233213A - Serial/parallel conversion circuit - Google Patents

Abstract

PURPOSE:To provide a serial/parallel (S/P) conversion circuit capable of easily executing rapid processing without considering of a margin due to a clock delay or the like, matching the timing of data changes and easily processing parallel data as a S/P conversion circuit for converting serial data into parallel data. CONSTITUTION:The S/P conversion circuit for converting serial data into n-bit parallel data is provided with a shift register 1 having plural n-bit parallel output for inputting serial data, n D-flip flops (FFs) 21 to 23 for inputting a shift clock from the register 1 as a trigger signal and plural selectors 31 to 33 for inputting the outputs of the D-FFs 21 to 23 and respective parallel outputs from the register 1 as each two inputs and selectively outputting either one of the two inputs to apply the selected input to each of the D-FFs 21 to 23 as a data input. The selectors 31 to 33 select the outputs of the register 1 at the rate of once to n shift clocks to convert the outputs of the D-FFs 21 to 23 and output the converted results in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial / parallel conversion circuit for converting serial data into parallel data.

[0002]

2. Description of the Related Art FIG. 1 shows the configuration of a conventional serial-parallel conversion circuit. The bit serial data D _i is input to the shift register 1 which is a 3-bit serial input / parallel output, using the clock CLK as a shift clock. The 3-bit parallel output is given to the data terminals of D-flip-flops (FF) 21, 22, 23. The clock CLK is also input to the 1/3 frequency dividing circuit 3, and its frequency division output is given to the trigger terminal of the flip-flop. Therefore, the contents of the flip-flops 21,22,23 change at a rate of once every three clocks CLK, and by using this as conversion data D ₀₁ , D ₀₂ , D ₀₃ , the desired serial / parallel conversion can be performed. You can do it.

FIG. 2 shows another conventional circuit.
The paths are clocked out of phase with input clocks CLK1, CLK2, CLK3.
TA D_iLatched in three D-flip-flops 21,22,23
D-flip-flop 2
Output D of 1,22,23₀₁, D₀₂, D ₀₃And the converted data
Then it is taken out.

[0004]

Although the circuits shown in FIGS. 1 and 2 are capable of performing serial-parallel conversion for the time being, the circuit shown in FIG. 1 has a 1/3 frequency divider circuit 3 for the timing of the clock CLK.
Since the output is delayed, it is necessary to design the circuit in view of the margin, which hinders the speedup.

The circuit of FIG. 2 has three clocks CLK1 and CL.
It is necessary to create K2 and CLK3 by separate circuits, and it is necessary to consider the variation in the operation of each clock generation circuit, which is also an obstacle to speeding up. FIG. 3 shows a time chart of the circuit of FIG. The three parallelized data (a, b, c) (d, e, f) have different changing timings. Therefore, D-flip-flops 21,22,23
The timing of fetching these 3-bit parallel data in the subsequent stage is also a design problem.

The present invention has been made in order to solve such a problem, and it is not necessary to consider a margin due to a clock delay or the like, speeding up is easy, and data change timing is uniform. Therefore, it is an object of the present invention to provide a serial-parallel conversion circuit in which parallel data can be easily handled.

[0007]

SUMMARY OF THE INVENTION A serial-parallel conversion circuit according to the present invention is a serial-parallel conversion circuit for converting serial data into n-bit parallel data, and shifting serial input n-bit parallel output to which serial data should be input. A register, n D-flip-flops that use the shift clock of the shift register as a trigger signal, the output of each D-flip-flop, and each parallel output of the shift register as two inputs,
A selector for selectively outputting either one of the inputs as a data input of each D-flip-flop, the selector selecting the output of the shift register once every n times of the shift clock. It is characterized in that the output of the D-flip-flop is a conversion parallel output.

[0008]

The contents of the shift register are taken into the D-flip-flops all at once every n shift clocks.
The same data is repeatedly input during the remaining n-1 shots.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described with reference to the drawings showing its embodiments.
Will be described in detail. FIG. 4 is a block diagram of the circuit of the present invention. Strange
Bit serial data D to be converted _iIs serial input / 3 bi
Input to the shift register 1 for parallel output.
Soft clock CLK is given. Shift register 1
The 3-bit parallel output of is connected to each input of selectors 31, 32 and 33.
Is becoming The outputs of the selectors 31, 32 and 33 are D-flip flips.
Ropp 21,22,23 are given to the respective data input terminals.
, Each Q output is the other input of the selector 31, 32, 33.
It

The shift clock CLK is applied to the trigger terminals of D-flip-flops 21, 22, 23. The shift clock CLK is input to the ternary counter 4,
The output of the bit is input to the NAND gate 5. The output of the NAND gate 5 is sent to the selectors 31, 32 and 33 and the selection control signal S
, The selectors 31, 32, 33 input the input on the shift register 1 side when the selection control signal S is "1",
When it is "0", the input on the D-flip-flops 21, 22, 23 side is selected and output.

Next, the operation of this circuit will be described with reference to the time chart of FIG. Serial data is W, X, Y, Z,
When A, B, C, D, E, and F are input, they are sequentially taken into the shift register 1 by the shift clock CLK, but the parallel output of the shift register 1 is now (Z, Y, X), the ternary counter 4
If the output of "00" is "00", the selection control signal S of the output of the NAND gate 5 becomes "1" and this (Z, Y, X) is selected by the selectors 33, 32, 31 and the next shift clock CLK. P
Are taken into the D-flip-flops 23, 22, 21 at the timing of. As a result, the output becomes (Z, Y, X).

The contents of the shift register 1 are sequentially changed by the shift clock CLK P and the subsequent Q and R. When the shift clocks CLK P and Q are input, the output of the ternary counter 4 becomes "01" and "10" and the selection control signal S becomes
It becomes "0". Then, at the next shift clock CLK R, the output of the ternary counter 4 becomes "00", and the selection control signal S becomes
Although it becomes "1", at the timing of the shift clock CLK Q, R, the Q output of the D-flip-flops 21, 22, 23 is taken in as it is, and the contents do not change. Then, (C, B, A) is taken into the D-flip-flops 23, 22, 21 at the timing of the next shift clock CLK S.

[0013]

According to the present invention as described above, only one clock generation circuit is required. Further, the selection control signal S is delayed from the shift clock CLK by the ternary counter 4 and the NAND gate 5. Since the D-flip-flops 21, 22, 23 are loaded by the next shift clock CLK, it is not necessary to take a margin for this delay. Furthermore, since the outputs of the D-flip-flops 21, 22, 23 change at the same timing,
The data determination timing in the subsequent circuit can also be set arbitrarily.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional serial-parallel conversion circuit.

FIG. 2 is a block diagram of a conventional serial-parallel conversion circuit.

FIG. 3 is a time chart of the circuit of FIG.

FIG. 4 is a block diagram of a circuit of the present invention.

FIG. 5 is a time chart of the circuit of the present invention.

[Explanation of symbols]

 1 shift register 21,22,23 D-flip-flop 31,32,33 selector 4 ternary counter 5 NAND gate

Claims (1)

[Claims] 1. A serial-to-parallel conversion circuit for converting serial data into n-bit parallel data, wherein a serial-input n-bit parallel-output shift register (1) to which serial data should be input.
And n D-flip-flops (21, 22, 23) using the shift clock of the shift register (1) as a trigger signal
And the output of each D-flip-flop (21,22,23) and each parallel output of the shift register (1) are two inputs, and one of the inputs is each D-flip-flop (21,22,2).
And a selector (31, 32, 33) for selectively outputting to be given as the data input of 3), and the selector (32, 32, 33)
Is for selecting the output of the shift register (1) once every n times of the shift clock, and the output of the D-flip-flop (21, 22, 23) is a conversion parallel output. A serial-parallel conversion circuit characterized by the above.