JPH052391A - Signal processor - Google Patents

Abstract

PURPOSE:To remove a noise due to old data without clearing the contents of a memory even when delay operation is switched. CONSTITUTION:The signal processor has a DSP 30, a control circuit 31, RAMs 32 and 34, and a selector 33, reads and writes data to be delayed out of and in a specific memory area on a FIFO basis, and delays the data by the time of the number of steps. If the number of delay steps or a signal which is inputted is changed halfway in the operation, data which are read out are ignored until a new delay time is elapsed and rewriting to a specific value (0) is carried out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device for performing delay processing or filter processing on a voice signal or a tone signal by a program operation.

[0002]

2. Description of the Related Art A digital signal processor (DSP) has been put into practical use as a device for performing delay processing and filter processing such as high frequency cut on time series signals such as audio signals. This device quantizes a time-series analog signal at each sampling timing, and programs a digitized signal by a high-speed microprocessor. That is, when performing delay processing, a memory area for sampling timing corresponding to the delay time is set, and data is stored in the FI.
This is done by reading and writing data with FO (first in first out). When processing a musical tone signal or the like, sampling is performed at a sampling frequency of about 40 kHz in order to maintain the sound quality. Therefore, 40,000 data storage areas are required to obtain the delay time of about 1 second. As such a device, there is a reverberation sound adding device described in JP-B-62-55158.

Different reverberation characteristics and filter characteristics can be realized by rewriting the control program and coefficient data of the DSP, but when the control program and coefficient data are rewritten while the DSP is continuously operating, the program before rewriting If the data processed by and written in the RAM remains as it is, the data is read at the beginning of a new process, which causes noise. Therefore, in such a case, conventionally, at the same time as rewriting the processing program, the processing for clearing all the delay RAMs is performed.

As described above, the operation of rewriting the control program and the coefficient data during the operation of the DSP is frequently performed in the recent electronic musical instruments because the tone generation channels are randomly assigned. Random assignment allows multiple tones to be pronounced simultaneously with different tones, and does not specify the channel that produces each tone, searches for an empty channel each time a KON signal is received, and turns on the key for that channel. This is a technology that sends tone color signals together with signals and key codes. This makes it possible to effectively use the pronunciation channels.

[0005]

However, in order to obtain a long delay time or to obtain a complicated filter characteristic as described above, it is necessary to store a lot of data, and the DSP has to be stored. Although a large-capacity RAM is connected, in the above-mentioned conventional method, the control program and coefficient data are frequently rewritten, and it is necessary to clear the entire area of the RAM each time, so this processing takes a very long time. However, there is a disadvantage that real-time signal processing becomes difficult.

An object of the present invention is to provide a signal processing device which does not clear data even if the processing program is changed and does not generate noise.

[0007]

According to the present invention, there is provided delay means for delaying an input signal by a predetermined time and outputting the signal, setting means for setting the delay time of the delay means, and the setting means is the delay means. When the setting of the delay time is changed, a means for rewriting the output of the delay means to a specific value after the change until the changed new delay time elapses is provided.

[0008]

In the signal processing apparatus of the present invention, the delay means and the setting means for setting the delay time of the delay means are provided, and when the setting means changes the setting of the delay time of the delay means, a new delay is set. Until the time passes, the output of the delay means is rewritten to a specific value. The delay means is, for example,
It is configured by means for reading / writing data in the area of RAM by FIFO. The setting means is composed of means for determining the number of stages of the memory area. When the setting of the delay time is changed, a new signal input immediately after that is not read until the delay time elapses, so the signal read before that is the signal at the old setting. Therefore, while this signal is being output, the output is changed to that output and a specific value is output. The specific value may be data (0, FF _H, etc.) expressing the state where there is no signal.

The signal processing apparatus of the present invention includes, for example, program storage means for storing a plurality of types of programs for executing a plurality of stages of delay operations for an input signal,
A delay time storage unit that stores a delay time at each stage for each of the plurality of types of programs; a plurality of signal storage units that stores signals that are separately set and delayed for each of the plurality of stages of delay operation; Selecting means for selecting one of the types of programs, and when the selection of the program is changed by the selecting means, at each step after the change, the step is performed until the delay time of the changed new program elapses. And means for rewriting the output of the signal storage means corresponding to the above into a specific value. The signal processing device configured as described above executes a delay operation in a plurality of stages by a program. The multi-stage delay operation is a case where, for example, an FIR filter or an IIR filter is realized by a DSP. In this case, the delay time corresponding to each step is stored corresponding to the program (delay time storage means), and when the program is selected, the output signal is output until the delay time elapses at each step. Rewrite to a predetermined value. by this,
Noise caused by reading old data in each step can be eliminated, and the time required for rewriting the program can be shortened.

[0010]

1 is a block diagram of an electronic musical instrument equipped with a signal processing apparatus according to an embodiment of the present invention. This electronic musical instrument can generate a plurality of musical tones at the same time by operating the keyboard 15, and each musical tone can be given different effects such as delay and filtering. The operation of the entire electronic musical instrument is the CPU 10.
Controlled by. ROM1 to CPU10 via bus 11
2, RAM 13, keyboard interface 14, panel interface 16, tone synthesis circuit 18 and effect imparting circuit 19 are connected. The keyboard 15 is connected to the keyboard interface. Further, the panel interface 16 is connected to each key and display of the operation panel 17 of the electronic musical instrument. The ROM 12 stores an operation program shown by a flowchart described later. R
A register area for storing data generated by operating the keyboard 15 and the panel 17 is set in the AM 13. Data such as a key code and velocity data is generated by operating the keyboard 15, and this data is transmitted to the CPU 10 via the keyboard interface 14.

The panel 17 includes a tone color selection switch and an effect selection switch. The tone synthesis circuit 18 is 8
It has 16 sound generation channels, and forms a tone signal based on the key-on signal and key code transmitted from the CPU 10. When the key-on is detected, the CPU 10 searches for a non-operating channel among the sound generation channels and instructs the channel to form a tone signal corresponding to the key-on. Therefore, which tone generation channel is in charge of forming a musical tone of which tone color is decided at random. The effect applying circuits 19 are provided in the same number as the tone generation channels, and can apply different effects to each of the formed musical tone signals. The musical tone signal to which the effect is applied is input to the sound system 20, amplified, and then output from the speaker 21.

FIG. 2 shows the FI realized by the effect applying circuit 19.
It is a figure which shows the example of an R filter.

This filter outputs an input musical tone signal t
It is delayed by a four-stage shift register of 1d to t4d, and outputs are taken out from the respective delay stages and combined by an adder. As a result, a finite number of reverberant sounds such as early reflected sounds can be added. In an actual electronic musical instrument, if such a fixed circuit is configured, it cannot be used for other effects, so such a filter characteristic is realized by a program using a DSP.

FIG. 3 shows an example in which the FIR filter of FIG. 2 is realized by a micro program. The operation of this program is as follows. The value of the input port INP is loaded (LD) into the accumulator Acc (step 0). A
Write the value of cc to the T1W address of the external RAM (MW:
Step 1). External R to internal register IW2 in DSP
Read and write the contents of T1R address of AM (MR:
Step 2). In steps 3 to 5, as in step 2, the contents of the T2R address of the external RAM are written to the internal register IW3, the contents of the T3R address of the external RAM are written to the internal register IW4, and the contents of the T4R address of the external RAM are written to the internal register. Write to IW5.

Here, in the table shown in FIG. 4, the write address T1 of the read addresses T1R, T2R, T3R, T4R is written.
It is a table that stores the number of shifts from W. The table of FIG. 4 is always stored in the microprogram as shown in FIG. According to this table, the read address T1R is a position shifted from the write address T1W by 3120 areas. That is, the data written in the external RAM is read out only after 3120 DAC cycles have elapsed, and the data is written in the following 21367 DAC cycles (T2
R), 36519 DAC cycle (T3R), 5949
It is read when 5 DAC cycles (T4R) have elapsed.

Next, in step 6 in FIG. 3, the internal register IW2 and the coefficient K1 are multiplied and loaded into Acc (ML). In step 7, the internal register IW3 is multiplied by the coefficient K2 and added to the current contents of Acc (MA).
In steps 8 and 9, as in step 7, the contents of the internal registers IW4 and IW5 at each stage are multiplied by the coefficients K3 and K4 and integrated. That is, the output of the shift register of each step is added up by this operation. K1
K4 corresponds to the impulse response. Finally, in step 10, the content of the accumulator Acc is output to the output port OUT. The above operation is repeatedly executed every 1 DAC cycle. In this case, the external RAM
Write address T1W and read address T
1R, T2R, T3R, T4R is constant every time, but 1
When the DAC cycle, that is, when the microprogram makes one cycle, all the data is shifted by one address, and one reference point for calculating the address is shifted. As a result, the address is relatively shifted (see FIG. 5).
reference).

By the way, when a microprogram is rewritten as shown in FIG. 3 in a DSP in which another microprogram is operating, the DSP addresses the data input from the tone synthesis circuit in step 1 of the first DAC cycle. Write to T1W.

Next, in step 2, the data of the address T1R will be read, but since the data stored in the previous microprogram has been written in the data of T1R at that time, it is completely different when the data is output. It will output the data of and cause noise. Further, even if the address is shifted by one in the next DAC cycle, the same is true. Data of a new program is read from the read address T1R as shown in FIG.
After the DAC cycle. Until then, the newly input data is sent to the delay cycle only and is not output, so the output in the read step should be 0 (data corresponding to 0). Therefore, D in FIG.
Until the number of AC cycles has elapsed, 0 is output regardless of the read data.

FIG. 6 is a block diagram of one channel of the effect imparting circuit 19 which realizes such an operation. DSP
A control circuit 31, a selector 33, and a RAM 34 are connected to 30. The register area of FIG. 5 is set in the RAM 34. A RAM 32 is connected to the control circuit 31. The RAM 32 stores the delay cycle number data of FIG. In addition, the microprogram of FIG. 3 is DSP3.
0 is loaded into the program memory. The tone signal WAVEIN input from the tone synthesis circuit 18 is a DSP3 signal.
At 0, various processing (for example, processing shown by the microprogram in FIG. 3) is performed. As a result, various effects are added to the musical tone signal and output as WAVEOUT. The DSP 30 reads / writes data from / to the RAM 34, but until the timing at which correct data is actually output when a new control program is started, the selector 33 changes the data read from the RAM 34 to 0. To the DSP 30.

FIG. 7 is a detailed diagram of the control circuit 31.
The control circuit 31 includes a memory control circuit 40, a counter 41,
AND gate 42, maximum value detection circuit 43, inverter 4
4, a comparator 45 and a NAND gate 46.
When the microprogram of the DSP 30 is changed, the DSP 30 outputs the CHANGE signal. This signal is given to the counter 41 and resets the count value. The counter value is compared by the comparator 45, and when the count value is smaller than the value given from the memory control circuit and the DSP requests the RAM 34 for reading, TH = for the selector 33 in FIG. Outputs 0. TH represents through, RA when TH = 1
It indicates that the value of M34 is directly input to the DSP 30. Therefore, when TH = 0, 0 is input to the DSP 30 regardless of the value output from the RAM 34.

In this way, the data in the RAM 34 will be input to the DSP 30 from the step having the shorter delay cycle. The counter 41 is configured to count up to the maximum value that can be set as a delay step,
When the maximum value detection circuit 43 detects the maximum value, it automatically stops. The signal input as the clock of this counter is S synchronized with the DAC cycle.
This is the YNC signal.

8 to 10 are flowcharts showing the operation of the electronic musical instrument. FIG. 8 shows the main routine. First, when the power switch is turned on, the initialization operation (n1) is executed. This operation is an operation such as register reset. After that, a key scan (n2) and a panel scan (n8) are performed, and if there is a key event and a panel event, the corresponding operations are executed. When there is a key event, the operations of n4 to n7 are executed according to the determination of n3. First, at n4, data indicating whether the event is a key-on event or a key-off event is stored in the key event register KEV, the key code is stored in the key code register KC, and the initial touch data is stored in the initial touch register IT. Next, if it is a key-on event, key-on processing (n6: FIG. 9) is executed, and if it is a key-off event, key-off processing (n7:
10) is executed. If there is a panel event, n
The operations of n10 to n14 are executed according to the judgment of 9. n10,
At n11, it is determined whether or not it is a switch event for designating the tone colors of the upper and lower keyboards. If it is an upper keyboard tone color designation event, the set tone color number is set in the UTC register (n14). If it is a lower keyboard tone color designation event, the set tone color number is set in the LTC register (n).
13). If it is another panel event, the corresponding operation is executed (n12).

FIG. 9 is a flow chart showing the key-on processing operation. When the key is turned on, the tone generation channel for producing the tone of the key on is searched (n20). If there is a vacant channel, sound generation processing is executed on that channel.
If there are no free channels, truncate (n2
Perform 2). The truncate process is a process of forcibly muting a musical tone having the lowest pronunciation level among all the musical tones produced at that time, and letting that channel be in charge of producing the musical tone based on this new key-on.
At n23, it is determined whether the key code of the turned-on key is higher than KSP. KSP is the highest tone key code of the lower keyboard, and if it is larger than this, it is the key-on event of the upper keyboard, and if it is less than this, it is the key-on event of the lower keyboard. In the case of the upper keyboard, UTC is set in the tone color register TC (n24), and in the case of the lower keyboard TC is set to LTC (n25). Microprogram corresponding to the set tone color number TC, effect imparting circuit 19
Of the microprogram delay cycle number data while transferring to the DSP of the corresponding channel of
Transfer to AM32 (n26). By this operation, it is possible to apply a unique effect to each timbre while adopting the random assign method. Data such as IT, KC, and TC are output to the corresponding channels of the tone synthesis circuit 18 to start the synthesis of tone signals (n27).

FIG. 10 is a flowchart showing the key-off process. When the key is turned off, it is searched whether or not there is a channel producing the tone of the key code (n3).
0).

If there is, a key-off signal is output to that tone generation channel to stop the synthesis of the tone signal (n31). In the case of a truncate or attenuated tone, there is a tone that has already been muted even if the key is turned on, so the determination of n30 is performed.

In this way, in the method of randomly assigning tone generation channels, it is not known what effect imparting function was assigned immediately before to the effect imparting circuit of that channel, so that a new tone signal is output. Output 0 until it becomes.

In this embodiment, the effect imparting circuit 19 has a configuration in which a DSP is provided in parallel for each tone generation channel, but one DSP may perform the time division processing.
Further, such processing can be applied not only to an electronic musical instrument played in real time but also to an automatic performance device such as a sequencer. Further, the effect imparted by the effect imparting circuit 19 is not limited to the effect of the FIR filter, and
The same can be applied to other algorithms such as filters.

Further, in the present embodiment, a counter for counting the number of delay steps and a RAM for storing the number of delay steps
Although the above is externally attached to the DSP 30, all the circuits (functions) may be incorporated in the DSP.

[0029]

As described above, according to the signal processing apparatus of the present invention, the delay time is changed while the delay processing is being performed, and when the input signal is changed, a new delay time elapses. Until then, the read signal is ignored and rewritten to a predetermined value. As a result, even if the effect to be given by the effect assigning circuit, which is randomly assigned, is switched, the old signal will not be read out as it is and cause no noise. Further, since it is not necessary to clear all the memories that execute the delay processing, there is an advantage that the processing speed is significantly improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an electronic musical instrument incorporating a signal processing device according to an embodiment of the present invention,

FIG. 2 is an FIR realized by an effect applying circuit of the electronic musical instrument.
Diagram showing the concept of filters,

FIG. 3 is a diagram showing a microprogram executed by a DSP of the effect imparting circuit;

FIG. 4 is a diagram showing a table in which the number of delay steps processed by the microprogram is stored.

FIG. 5 is a diagram for explaining an address shift method executed by the DSP.

FIG. 6 is a block diagram of the effect imparting circuit,

FIG. 7 is a detailed block diagram of a control circuit of the effect imparting circuit,

FIG. 8 is a flowchart showing the operation of the electronic musical instrument,

FIG. 9 is a flowchart showing the operation of the electronic musical instrument,

FIG. 10 is a flowchart showing an operation of the electronic musical instrument.

[Explanation of symbols]

30-DSP, 31-control circuit, 32- (RAM storing delay step number), 33-selector, 34- (delay data storage area is set) RAM.

Claims (1)

Claim: What is claimed is: 1. A delay means for delaying an input signal by a predetermined time and outputting the delayed signal, a setting means for setting the delay time of the delay means, and a delay time of the delay means for the setting means. When the setting of is changed, after the change, until the changed new delay time elapses, a means for rewriting the output of the delay means to a specific value is provided.