JPH05235025A - Manufacture of mos transistor - Google Patents

Abstract

PURPOSE:To provide the method for manufacture of a MOS transistor with which the heavy metal coming into a substrate in a source-drain forming process can be gettering-treated without deterioration of element characteristics. CONSTITUTION:A gate insulating film 12 is formed on the surface of a semiconductor substrate 1. Conductive films 10, 9 and 8 are deposited successively, a resist 7 is provided, processed in the same pattern and a gate electrode G and a protective film 8, which covers the gate electrode G, are formed. A gettering site 6 is formed on the inside part 1b of the substrate on both sides of the gate electrode G by implanting the prescribed ions using the protective layer 8 as a mask. The prescribed ions are implanted using the protective layer 8 as a mask, the implanted ions are activated by conducting a heat treatment, and source and drain regions 13 and 14 are formed on the substrate surface 1a on both sides of the gate electrode G.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOS transistor, and more particularly to a method of gettering heavy metal or the like in a semiconductor substrate to reduce the junction leakage current of the MOS transistor.

[0002]

2. Description of the Related Art Generally, when a MOS transistor is formed in a semiconductor substrate, an element isolation process for partitioning the surface of the semiconductor substrate into devices, a gate formation process for forming a gate insulating film and a gate electrode, and a source for forming a source / drain region are formed. The drain formation process and the like are sequentially performed. Then, in the middle of these manufacturing steps, a method of forming a getter site on the surface of the substrate or inside the substrate, and gettering heavy metal ions and the like entering into the semiconductor substrate is adopted (mainly after completion of the element. This is to reduce the junction leak current in the source / drain region.).

For example, as shown in FIG. 4, a method of forming the getter site 105 by an IG (intrinsic gettering) process or the like is known. Further, as shown in FIG. 5, a method of forming a getter site 106 after the element isolation step and before the gate formation step is also known. In this case, after removing the SiN film 103, ¹¹ B ⁺ ( ³¹ P ^{+ in the} case of an N-type substrate) is injected with high energy, and the inside 101 b of the substrate is removed.
A getter site 106 having a medium impurity concentration (between the substrate concentration and the concentration of the source / drain region) is formed on the substrate.

[0004]

However, the gettering site 106 exhibits a gettering ability at the time of being activated by a high temperature treatment (such as thermal oxidation), but the gettering ability decreases after being activated. I'm afraid. In the above conventional method, since the getter sites 105 and 106 are formed in a relatively early process step including high temperature treatment,
There is a problem that it is difficult to getter the heavy metal and the like that enter the substrate 1 in a later step, particularly a source / drain formation step. Therefore, the junction leak current in the source / drain region cannot be effectively reduced.

For example, SiO ₂ (CV
LDD by forming a sidewall of (by D method)
When forming a (lightly doped drain) structure,
At the time of etching the sidewall, 10 from the surface
Alkali metals such as Na, K, Ca, Mg, C in the area of 00Å
Heavy metals such as u and Cr, carbon C, etc., from several 10 ppm to several 100
It is known to be in the order of ppm. Even when the source / drain regions are formed by ion implantation, it is estimated that the same level of contamination will enter from the ion implanter.

Here, when high energy implantation is performed after the gate electrode formation step and before the source / drain formation step to form a getter site inside the substrate, the implanted ions penetrate to deteriorate the gate insulating film. There is.
Also, due to knock-on of the gate electrode constituent material (tungsten, polysilicon, etc.), contamination occurs under the gate electrode, and secondary defects caused by arriving ions occur, resulting in deterioration of device characteristics.

Therefore, an object of the present invention is a MOS capable of gettering a heavy metal or the like that enters the substrate in the source / drain forming step without deteriorating the device characteristics.
It is to provide a method for manufacturing a transistor.

[0008]

In order to achieve the above object, a method of manufacturing a MOS transistor according to the present invention comprises forming a gate insulating film on the surface of a semiconductor substrate, and then forming a conductive film and an insulating film on the gate insulating film. In order, the conductive film and the insulating film are processed into the same pattern to form a gate electrode and a protective layer covering the gate electrode, and predetermined ions are implanted using the protective layer as a mask. A step of forming getter sites inside the substrate on both sides of the gate electrode, implanting predetermined ions using the protective layer as a mask, and further performing a heat treatment to activate the implanted ions, The method is characterized by including a step of forming source / drain regions on the surfaces of the substrates on both sides.

[0009]

Since the getter sites are formed by performing ion implantation using the protective layer as a mask, the implanted ions do not deteriorate the gate insulating film. Also,
The knock-on of the gate electrode constituent material does not cause contamination under the gate electrode or secondary defects caused by arriving ions. Therefore, deterioration of element characteristics is prevented.

Further, the getter sites getter the heavy metals and the like that enter the substrate during the heat treatment for forming the source / drain regions. In addition, the getter site is activated by heat treatment and functions as a buried layer that suppresses the extension of the depletion layer in the source / drain region after the element is completed. Therefore, the junction leak current in the source / drain region is effectively reduced.

[0011]

The method for manufacturing a MOS transistor of the present invention will be described in detail below with reference to embodiments.

First, as shown in FIG. 1A, a SiN film (not shown) is formed on the surface 1a of a P-type silicon substrate (P-type well) 1 as a mask for selective oxidation in the same manner as shown in FIG. (No)
After forming a field oxide film 2 having a thickness of 6000Å, ¹¹ B ⁺ ( ³¹ P ^{+ in the} case of an N-type substrate) is injected from above to form a field inversion prevention layer 5 on the surface of the element isolation region. Then, a field oxide film 2 having a thickness of 6000Å is formed. The ion implantation dose of the field inversion prevention layer 5 is set to 1 × 10 ¹⁴ cm ^-2 . The implantation energy is set in the range of 30 to 100 keV. The field inversion prevention layer 5 is activated and functions as a buried layer after the element is completed. That is, the spread of the depletion layer at the end of the source / drain region is suppressed, and the junction leak current is reduced. Next, as shown in FIG. 1B, after forming a gate insulating film 12 having a thickness of 150Å on the surface 1a of the substrate 1, a conductive film having a thickness of 1 is formed on the gate insulating film 12 by the CVD method.
A 5 nm polysilicon film 10 and a 20 nm thick WSi film 9 are sequentially deposited. Further, an HTO (high temperature oxide) film 8 having a thickness of 70 to 500 nm is deposited as an insulating film by the CVD method. The resist 7 is provided to a thickness of 1.1 μm, and the WSi film 9, the polysilicon film 10 and the HTO are formed.
The film 8 is processed into the same pattern. As a result, the above W
The Si film 9 and the polysilicon film 10 form the gate electrode G, and the HTO film 8 forms the gate electrode G.
A protective layer (for the sake of simplicity, represented by the same numeral as the HTO film 8) is formed to cover the. Then, using the resist 7, the HTO film 8 and the gate electrode G as a mask, boron ions ¹¹ B ⁺ are implanted at an implantation energy in the range of 200 to 500 keV, and getter sites 6 are formed in the substrate interior 1b on both sides of the gate electrode G. Form. The actual implantation energy is set based on FIGS. 2 and 3 so that the getter site 6 is formed at a predetermined depth. Figure 2
Shows the relationship between the implantation energy and the depth in the silicon substrate when ion implantation is performed without providing a mask, and FIG. 3 shows the implantation energy and the HTO film 8 necessary to block the implanted ions.
Shows the relationship with the thickness of. As can be seen from FIGS. 2 and 3, the depth of the getter site 6 can be adjusted by changing the thickness of the HTO film 8. Further, phosphorus ions ³¹ P ⁺ are implanted from above under the conditions of implantation energy of 60 keV and dose of 3 × 10 ¹⁴ cm ^-2 , and the LDD layer 13 is deposited on the substrate surface 1a on both sides of the gate electrode G.
To form. Since the getter site 6 is formed by using the HTO film 8 as a mask, the implanted ions are not included in the gate insulating film 12.
Can be prevented, and the gate insulating film G can be prevented from being deteriorated. Further, the knock-on of the gate electrode constituent material does not cause contamination under the gate electrode G or secondary defects caused by arriving ions. Therefore, deterioration of element characteristics can be prevented. Next, as shown in FIG. 3C, after removing the resist 7, an LTO (low temperature oxide) film having a thickness of 3000Å is deposited on the substrate 1 by the CVD method.
The LTO film is etched back to form sidewalls 11 on both sides of the HTO film 8 and the gate electrode G. Next, using the HTO film 8, the gate electrode G and the sidewall 11 as a mask, arsenic ions As ⁺ are implanted with energy 6
Implantation is performed under the conditions of 0 keV and a dose amount of 4 × 10 ¹⁵ cm ^-2 , and then heat treatment for activating the implanted ions (900 ° C., 30
Minutes). As a result, the source / drain regions 14 are formed in the portions of the LDD layer 13 on both sides of the sidewall 11.

According to this manufacturing process, the sidewall 1
1 from the dry etcher at the time of forming 1, LDD layer 1
3. When the source / drain regions 14 are formed, contaminations such as heavy metals come into the silicon substrate 1 from the ion implanter, and these heavy metals and the like can be gettered to the getter site 6 by the heat treatment in the process. Moreover, after the heat treatment, the getter site 6 is activated and acts as a buried layer for suppressing the extension of the depletion layer of the source / drain region 14. Therefore, the junction leak current of the source / drain region 14 can be effectively reduced.

Although this embodiment has been described with respect to the case of manufacturing a P-channel type MOS transistor, the present invention can of course be applied to the case of manufacturing an N-channel type MOS transistor.

[0015]

As is clear from the above, the M of the present invention
In the method for manufacturing the OS transistor, the protective layer covering the gate electrode is formed, and the getter site is formed inside the substrate by performing ion implantation using the protective layer as a mask.
It is possible to prevent the implanted ions from penetrating the gate insulating film and prevent the gate insulating film from being deteriorated. In addition, the knock-on of the gate electrode constituent material does not cause contamination under the gate electrode G or a secondary defect caused by arriving ions, and therefore deterioration of device characteristics can be prevented.

When the heat treatment for activating the source / drain regions is performed, the getter sites getter the heavy metal or the like. Moreover, after the device is completed, the gettering layer functions as a buried layer that suppresses the extension of the depletion layer in the source / drain regions. Therefore, the junction leak current in the source / drain region can be effectively reduced.

[Brief description of drawings]

FIG. 1 is a process chart illustrating a method for manufacturing a MOS transistor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between implantation energy and a depth of implanted ions in a silicon substrate.

FIG. 3 is a diagram showing a relationship between implantation energy and the thickness of an HTO film required to block implanted ions.

FIG. 4 is a diagram illustrating a conventional getter site forming method.

FIG. 5 is a diagram illustrating a conventional getter site forming method.

[Explanation of symbols]

1 P-type silicon substrate 1a Substrate surface 1b Inside substrate 2 Field oxide film 5,6 Getter site 7 Resist 8 HTO film 9 WSi film 10 Polysilicon film 11 Sidewall 12 Gate insulating film 13 LDD
Layer 14 Source drain region

Claims (1)

[Claims] 1. A step of forming a gate insulating film on a surface of a semiconductor substrate and then sequentially depositing a conductive film and an insulating film on the gate insulating film, and processing the conductive film and the insulating film into the same pattern, Forming a gate electrode and a protective layer covering the gate electrode; implanting predetermined ions using the protective layer as a mask to form getter sites inside the substrate on both sides of the gate electrode; A MOS transistor including a step of implanting predetermined ions using the layer as a mask, and further performing a heat treatment for activating the implanted ions to form source / drain regions on the substrate surface on both sides of the gate electrode. Manufacturing method.