JPH0522629A - Processor for video signal - Google Patents

Abstract

PURPOSE:To enable even the two-dimensional processing with a video signal processor. CONSTITUTION:The input video signals are supplied to an S/P converter 30 to undergo the S/P conversion for each picture element number N of a unit processing block. The data equivalent to a fixed scanning period (1H in this instance) are stored in an input shift register 12 in regard of those input video signals undergone the S/P conversion. Then, all data are transferred to a memory 14 from the register 12. The horizontal and vertical arithmetic operations are applied to the data stored in both memories 14 and 18 for each bit through a processor array part 16. The horizontal arithmetic operation is carried out for each line, and the vertical arithmetic operation is carried out among the same bits to each other after the horizontal operation is complete. These arithmetic operations are carried out under the SIMD control. The final processing data is converted into the serial data by a P/S converter 32 through the memory 18 and an output shift register 20. Thus the video signals undergone the image processing are available.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processor used as a suitable programmable processor when digitally processing a video signal of a television or the like, and more particularly to a video signal capable of two-dimensional processing. Regarding the processor.

[0002]

2. Description of the Related Art As a programmable processor used when digitally processing a video signal (image signal) such as a television signal, a 1-bit ALU (arithmetic.
VRA for the processor array unit using the logical operation circuit)
A video signal processor incorporated in the M is known (for example, "JIM CHILDERS, et al" SVP: SERIAL V
IDEO PROCESSSOR "IEEE 1990 CUSTOM INTEGRATED CIRCUI
Processor disclosed in TS CONFERENCE 17.3, etc.).

FIG. 7 shows an example of a main part of the video signal processor 10.

An n-bit, for example 8-bit input video signal (digital signal) is introduced to the input shift register 12.

The input shift register 12 can shift at least each bit of input data (an input video signal, the same applies hereinafter) simultaneously and sequentially in the right direction (corresponding to the line direction), and the number of stages is at least that of an image. There are H pixels (for example, 1024 stages) in one horizontal scanning period. Then, the input data for one horizontal scanning period is accumulated by sequentially performing shift processing for one horizontal scanning period of the image with a clock matched to the data rate of the input data.

Input data for one horizontal scanning period accumulated in the input shift register 12 is simultaneously transferred to the memory 14 (memory A) every horizontal scanning period. Therefore, the memory write operation occurs simultaneously in each stage of the input shift register 12, and among the memory cells corresponding to each stage of the memory 14, the memory cell addressed by the program is simultaneously input in one write operation. Data is written.

The data written in the memory 14 is stored together with the data written in the same manner in the past, the calculation result in the processor array section 16 which will be described later, and the data written in the memory 14 again. The data written in the memory 14 is read out as needed and used for arithmetic / arithmetic processing in the processor array unit 16 described later.

Like the input shift register 12, the memory 14 has memory cells arranged laterally by the number corresponding to the number of pixels in the horizontal scanning period, but there is no particular condition in the vertical direction. As described above, in the memory 14, it is necessary to temporarily store the intermediate result of the calculation result in addition to the data of the input shift register 12, so the number of memory cells in the vertical direction is about 3n to 4n. There are many cases.

The processor array section 16 provided in the lower stage of the memory 14 has the memory 14 existing in the upper stage and the lower stage.
And the memory 18 (memory B), the respective data is read out in accordance with the processing program, the necessary arithmetic operation or logical operation is performed, and the result is again memory cell of the memory 14 or 18 addressed by the processing program. Written in. However, the final result is written in the lower memory 18.

Arithmetic / operation processing can be performed only on data existing in the same column, and the processing result is also written in the memory cells in the same column.

In the processor array section 18, one processor element corresponds to each memory cell column (the column 28 is shown as a representative thereof) as shown by hatching. As shown in FIG. 8, the processor element is composed of a 1-bit ALU (arithmetic logic operation unit), and there is only one in the column direction. However, as many processor elements as the number of stages (number of pixels) of the input shift register 12 are arranged in the row direction.

The processor array section 16 is controlled by the program control section 22 at an operating speed different from the input / output speed. And the control is what is called SIMD control (SIMD
Control: Single Instruction stream Multi Data strea
m), and all the processor elements work together by one processing program.

The processor element is a 1-bit ALU
Therefore, this processor element is decomposed into bit processes, that is, processed in units of 1 bit.

The memory 18 in the lower stage is provided as needed, and like the memory 14, memory cells are arranged in the horizontal direction by the same number as the number of pixels in one horizontal scanning period.
The memory 18 stores intermediate results of arithmetic operations in the processor array unit 16 and final results thereof. Therefore, the data is not directly written from the input shift register 12.

The data stored in the memory 18 is simultaneously transferred to each stage of the output shift register 20 every horizontal scanning period. The output shift register 20 has the same configuration as the input shift register 12, and sequentially shifts data to the right to output n-bit data (image-processed video signal).

[0016]

In this conventional configuration, as apparent from the configuration of FIG. 7, the processor array section 16 is also provided.
Since only the data in the memory 14 or 18 on the same column to which the processor element belongs can be processed by, the image processing is performed in the vertical direction on the screen.

In other words, this conventional configuration is suitable for signal processing in units of horizontal scanning period, only calculation with pixels in the vertical direction is possible, and is not suitable for other signal processing forms. It is composed.

For example, filtering is easy to handle because it can be processed in units of horizontal scanning periods, but it is also limited to vertical filtering. This is because, in the case of the filtering process in the vertical direction, when a certain pixel on the screen is focused, the process is performed by considering only the upper and lower neighboring pixels.

On the other hand, when filtering in the horizontal direction, it is necessary to consider the left and right neighboring pixels, but in the configuration shown in FIG. This is because the data of is not accessible.

Therefore, for example, in the case of the two-dimensional DCT (discrete cosine transform) processing well known in the video signal processing technology, for example, as shown in FIG.
In many cases, a two-dimensional block having a total of 64 pixels of 8 pixels in the vertical direction (that is, 8 lines) is subjected to image processing as a unit processing block. In such a case, since it is necessary to sequentially access and process the addresses in which the horizontal and vertical data are stored, this two-dimensional processing is impossible with the configuration shown in FIG.

Therefore, the present invention solves such a conventional problem and proposes a processor for SIMD control, which is a video signal processor capable of two-dimensional processing.

[0022]

In order to solve the above problems, according to the present invention, an input shift register capable of accumulating an input video signal for a constant scanning period and data from the input shift register in parallel for each constant scanning period. A memory for receiving data, a processor array unit for performing processing such that the data stored in the memory is read out and operated as needed, and written in the memory again under SIMD control; In a video signal processor composed of output shift registers that receive data from the memory in parallel for each period, serial / parallel conversion of the input video signal into serial / parallel conversion for each number of pixels in the line direction forming a unit processing block A converter is installed in front of the input shift register,
It is characterized in that two-dimensional processing is performed using an input video signal subjected to parallel conversion.

[0023]

As shown in FIG. 1, the input video signal is supplied to the serial / parallel converter 30 and serial / parallel converted for each number N of pixels in the line direction forming the unit processing block. As for the input video signal subjected to serial / parallel conversion, data for a certain scanning period (1H in this example) is accumulated in the input shift register 12. When the accumulation of 1H of input data is completed, all the accumulated data is transferred from the input shift register 12 to the memory 14.

Here, the input data is the serial / parallel converter 3
Since serial / parallel conversion is performed with 0, the data (in the case of 8 bits, D1 to D8) in the unit areas B1 to B8 forming the two-dimensional processing block as shown in FIG. Of the line data storage areas MA1 to MA8 provided in the memory 14, the data is transferred and stored in the memory cells in the same column.

The data stored in the memory 14 or the data on the same column stored in the memory 18 provided in the lower stage of the processor array section 16 is supplied to the processor array section 16 as occasion demands, and the horizontal direction and Vertical arithmetic / arithmetic processing is performed bit by bit.

The arithmetic / calculation processing in the horizontal direction is performed in the unit area B1.
The same bit Di (i = 1 to 1) is executed every B8, and the arithmetic / arithmetic processing in the vertical direction is completed in the horizontal direction.
8) Performed by each other.

The calculation result is written in the memory 14 or 18 again. This arithmetic / arithmetic processing is performed under SIMD control. The final processed data is stored in the memory 18. The data accumulated in the memory 18 is transferred to the output shift register 20, and this is further transferred to the parallel / serial converter 3.
At 2, the video signal is converted into serial data and the image-processed video signal is obtained.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a case where an example of a video signal processor according to the present invention is applied to the above-mentioned two-dimensional filtering processing will be described in detail with reference to FIG.

The input video signal is supplied to the serial / parallel converter 30 and serial / parallel converted for each number N (N is an integer) of pixels in the line direction which form the unit processing block. When the number of input bits n is 8 and (8 pixels × 8 lines = 64 pixels) is a unit block in the two-dimensional processing as shown in FIG. 9, each input bit (bit 0 to bit 7) corresponds to 8 pixels (N = 8) as a unit, serial / parallel conversion processing is performed.

The input data subjected to the serial / parallel conversion processing is supplied to the input shift register 12 and the input data for 1H is accumulated. As the input shift register 12, the number of stages H of which is reduced to 1 / N is used. However, since the data subjected to the parallel conversion processing is handled in the vertical direction, the number of stages is N times that in the case of FIG. 7. Therefore, although the shift register has a vertically long shape, the total number of stages is the same as the conventional one.

FIG. 2 shows a specific example of the serial / parallel converter 30 and the input shift register 12, both of which are constructed by connecting 1-bit storage elements 36 in cascade. The case where a flip-flop (FF) is used is shown. The serial / parallel converted input data (8 bits) is sequentially shifted by one pixel in the horizontal direction,
This is repeated for 1H.

When the accumulation of 1H of input data is completed,
All the data accumulated from the input shift register 12 is transferred to the memory 14. Therefore, the input shift register 1
In each of the two stages, each flip-flop 36 is connected to the vertical memory cell column of the memory 14 immediately below it.

Here, the input data is the serial / parallel converter 3
Since the serial / parallel conversion is performed with 0, the unit areas B1 to B8 forming the two-dimensional processing block 28 as shown in FIG.
The data (D1 to D8 in the case of 8 bits) is stored in the memory cells arranged on the same column in the line data storage areas MA1 to MA8 provided in the memory 14 as shown in FIG. It will be transferred and stored.

That is, the pixel data D1 to D8 (eight pixels) that are arranged in the horizontal direction at the stage of input data are
When stored in the memory 14, the pixel data D1 to D8
Is stored vertically converted. In other words, the data array of the two-dimensional processing block 28, which was configured by arranging 8 pixels in the horizontal direction and 8 pixels in the vertical direction,
As shown in FIG. 4, the data array is stored in a state where the data array is changed so that one pixel is arranged in the horizontal direction and 64 pixels is arranged in the vertical direction.

Since the storage areas MA1 to MA8 can be designated (hence, their addresses are designated), the storage areas can be designated in any order. For example, the area designation opposite to the case of FIG. 4 is possible.

The number of memory cells is selected to be 3 to 4 times the total number of stages of the input shift register 12. This is because the memory 14 stores the previous data from the input shift register 12, and also stores the data of the previous line,
This is to secure an area in which arithmetic / calculation processing results, which will be described later, can be stored.

The processor array section 16 has the same structure as that shown in FIG. The memory 18 provided in the lower stage of the processor array unit 16 (the configuration of this memory is not an absolute condition, but provided as necessary) and the memory 14 arranged in the upper stage are located on the same column respectively. The data in the memory cells or the data in the memory cells located on the same column and stored in the upper memory 14 are supplied to the processor array section 16 as occasion demands, and arithmetic / operation in the horizontal and vertical directions is performed. The processing is performed bit by bit.

The arithmetic and calculation processing in the horizontal direction is performed in the unit area B1.
Is performed for each B8 to B8, and the processing result is stored in the same or different memory area located on the same column of the memory 14 or 18. The arithmetic / operation processing in the vertical direction is the same bit Di (i = 1
It is performed between the data of 8). Then, the processing result is stored in the memory area of the same column of the memory 18.

Such arithmetic / arithmetic processing is performed under SIMD control. The control program is supplied from the program control unit 22 to the memories 14 and 18 and the processor array unit 16.

The data stored in the memory 18 is transferred to the output shift register 20, which is further converted into serial data by the parallel / serial converter 32 to obtain a video signal after image processing. For example, a two-dimensional DCT-processed video signal can be obtained.

As described above, in the embodiment shown in FIG. 1, not only the input shift register 12, but also the memories 14 and 18, the processor array section 16, and the output shift register 20 are all 1 / N of the conventional width. However, since the processing was devised so that the data of the two-dimensional processing block would fit in the same vertical single cell row of the memories 14 and 18, not only the one-dimensional processing in the horizontal and vertical directions but also the two-dimensional processing was performed. Can be extended to.

FIG. 5 shows another embodiment of the present invention. Figure 1
In the configuration shown in (1), since the serial / parallel converter 30 parallelizes the number of pixels in the horizontal direction of the two-dimensional processing block, the number of connections from the input shift register 12 to the memory 14 is increased N times as compared with the conventional case. Therefore, as shown in FIG. 2, since the vertical direction (vertical direction) connection (the connection line is not shown) between the flip-flops 36 in each stage and the memory cells of the memory 14 is N times, the wiring is It is also possible to prevent integration. FIG. 5 is an example for improving this.

In the embodiment shown in FIG. 5, in order to reduce the number of connecting lines between the input shift register 12 and the memory 14, a group of elements (referred to as a memory section 14 ') functioning as a part of the memory in the input shift register 12. ) Is incorporated. Therefore, the memory 14 is divided into two parts. The same applies to the memory 18, part of which is incorporated in the output shift register 20 and the memory unit 1
It is 8 '.

FIG. 6 shows a specific example of the flip-flop 28 which constitutes the input shift register 12.
Between each of the columns, the memory cells 38 like the shaded area are arranged. The memory cell 38 is an N-bit configuration memory cell.

With this structure, writing to the memory 14 is always performed via the memory section 14 '. That is, if writing is performed only in the memory cell 38 placed adjacent to the flip-flop 36,
Problems with the connection from the input shift register 12 to the memory 14 no longer occur.

Here, N memory cells are required for processing a block of N horizontal pixels. this is,
This can be realized by maintaining the physical width of the 1-bit cell and making it vertically long. Alternatively, a 1-bit memory cell may be used if it is used so as to satisfy the condition that it is always moved to another address by the processing program for one horizontal scanning period.

Since the connection between the memory 18 and the output shift register 20 is made in the same manner, its explanation is omitted.

[0048]

As described above, according to the present invention, an input video signal is once subjected to serial / parallel conversion processing, and arithmetic / arithmetic processing is performed based on the serial / parallel conversion output data.

According to this, not only the conventional one-dimensional processing in the horizontal direction and the vertical direction but also the two-dimensional processing can be easily realized without increasing the number of circuit elements. Therefore, the present invention is suitable for application to a video signal processor that performs two-dimensional DCT processing or the like that requires two-dimensional processing as described above.

[Brief description of drawings]

FIG. 1 is a system diagram of essential parts showing an example of a video signal processor according to the present invention.

FIG. 2 is a connection diagram showing a specific example of a serial / parallel converter and an input shift register.

FIG. 3 is an explanatory diagram of line data for explaining two-dimensional processing.

FIG. 4 is an explanatory diagram illustrating a memory storage state for describing two-dimensional processing.

FIG. 5 is a system diagram of a main part of a video signal processor showing another example of the present invention.

FIG. 6 is a connection diagram showing the relationship between the serial / parallel converter, the input shift register, and the memory section in FIG.

FIG. 7 is a system diagram showing an example of a conventional video signal processor.

FIG. 8 is a diagram of a processor element.

FIG. 9 is an explanatory diagram of two-dimensional processing.

[Explanation of symbols]

 10 video signal processor 12 input shift register 14, 18 memory 14 'memory unit 16 processor array unit 20 output shift register 22 program control unit 30 serial / parallel converter 32 parallel / serial converter 36 flip-flop 38 memory cell

Claims (1)

Claim: What is claimed is: 1. An input shift register capable of accumulating an input video signal for a constant scanning period, a memory for receiving data from the input shift register in parallel for each constant scanning period, and as occasion demands. The data stored in the memory is read out, calculated, and then written in the memory again.
In a video signal processor composed of a processor array section that is operated under IMD control and an output shift register that receives data from the memory in parallel at regular scan intervals, a line direction that constitutes a unit processing block. Serial-parallel conversion of the input video signal for each number of pixels in
A video signal processor characterized in that a parallel converter is provided in front of the input shift register, and two-dimensional processing is performed by using the serial-parallel converted input video signal.