JPH05225799A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To detect a latently defective memory cell having a low data holding ability in the short time. CONSTITUTION:A holding current controller 4 provided with a bipolar transistor Q2 turning off the power unit within an ordinary operating power supply voltage range and turning on in the power unit outside of the region is provided. Sufficient data holding current is supplied to each memory cell MC similarly with a conventional example and when the controller is operated at the outside of the range of the ordinary operating power supply voltage and the data holding current supplied to each memory cell is reduced when the controller is operated at the outside of the range, the defective memory cell is latently detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a memory cell including a bipolar transistor and a circuit for supplying a data hold current to the memory cell.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor memory device of this type, as shown in FIG. 3, a plurality of memory cells MC arranged in a matrix in a row direction and a column direction and a plurality of memory cells MC for selecting these memory cells in units of rows. Memory cell array 1 having the word lines WT1 to WT2 and a plurality of first bipolar transistors Q1 provided corresponding to each row of the memory cell array 1 and supplying a data hold current to each memory cell of the corresponding row. And a hold current supply circuit 2 having a resistor R1 and a base of each first bipolar transistor Q1 of the hold current supply circuit 2 are supplied with a bias voltage VB stabilized against power supply voltage fluctuations and temperature fluctuations. Bias circuit 3 for controlling the data hold current to each memory cell MC to a predetermined value, and within the normal operating power supply voltage range. It has been a play constitute a predetermined function in the source.

Normally, the data holding capacity of the memory cell MC due to radiation or the like greatly changes depending on the magnitude of the data hold current. Therefore, in the semiconductor memory device, this data hold current is sufficient so as not to destroy the contents of the memory cell. It is a value with a margin.

[0004]

In this conventional semiconductor memory device, since the data hold current is designed with a sufficient margin, the memory cell M is defective due to manufacturing defects.
Even if a part of C does not have sufficient characteristics and causes data destruction due to radiation when used for a long time, it is possible to detect these potentially defective memory cells in a short-time screening test. It was difficult.

An object of the present invention is to provide a semiconductor memory device capable of detecting a potentially defective memory cell having a low data retention capacity in a short time.

[0006]

A semiconductor memory device according to the present invention includes a memory cell array having a plurality of memory cells arranged in a matrix in a row direction and a column direction, and a memory cell array corresponding to each row of the memory cell array. A hold current supply circuit including a plurality of first bipolar transistors for supplying a data hold current to each memory cell of the corresponding row and a resistor, and a bias for the base of each first bipolar transistor of the hold current supply circuit. A semiconductor memory device having a bias circuit for supplying a voltage to control a data hold current to each of the memory cells to a predetermined value and performing a predetermined function with a power supply within a normal operating power supply voltage range. In the power supply within the operating power supply voltage range, the hold current supply circuit operates so as to perform the predetermined function. A data hold current is supplied to each memory cell of the cell array, and a power supply outside the normal operating power supply voltage range supplies a smaller data hold current to each memory cell of the memory cell array when the power supply is within the normal operating power supply voltage range. A hold current control circuit for supply is provided.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment differs from the conventional semiconductor memory device shown in FIG. 3 in that the emitter and collector hold current supply circuit 2 has a first power supply voltage receiving end (VE).
E) and a bias voltage (VB) power receiving terminal respectively corresponding to the second bipolar transistor Q2 and the power supply within the normal operating power supply range, the second bipolar transistor Q2 is turned off, and is outside the normal operating power supply voltage range. The second power supply includes a second resistor R2 for turning on the second bipolar transistor Q2 and a plurality of diodes D1, and a power supply within a normal operating power supply voltage range holds a hold current so as to perform a predetermined function similar to the conventional one. A data hold current is supplied from the supply circuit 2 to each memory cell MC of the memory cell array 1, and a power supply outside the normal operating power supply voltage range supplies a data hold current smaller than that of the power supply within the normal operating power supply voltage range. The holding current control circuit 4 for supplying each memory cell MC is provided.

With this structure, the bipolar transistor Q2 is operated within the normal operating power supply voltage range.
Is turned off and a sufficient data hold current is supplied to each memory cell MC as in the conventional example, so that data writing and reading can be performed with sufficient safety. Further, in the case of performing a screening test for defective memory cells, the bipolar transistor Q is set by setting the power supply voltage to a power supply voltage larger than the normal operating power supply voltage range.
2 is turned on, the base potential of the bipolar transistor Q1 decreases, and the data hold current decreases. If a normal memory cell test is performed in this state, a normal memory cell MC has a sufficient margin, and data can be retained for a short time so that operation failure does not occur, but the memory cell has poor characteristics and is potentially defective. In this case, the data cannot be held, resulting in a malfunction, and these can be selected.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, the hold current control circuit 4a is used.
Is connected at one end to a second power supply voltage receiving end (VEE) of the hold current supply circuit 2 and a third resistor R3 for supplying the first power supply voltage VEE to the first power supply voltage receiving end, an emitter and A second bipolar transistor Q2 whose collector is connected to the first power supply voltage receiving end and the second power supply voltage supply terminal (VSS) respectively, and a second bipolar transistor Q2 for a power supply within a normal operating power supply voltage range. Q
2 is turned off, and a power supply outside the normal operating power supply voltage range is provided with a second resistor and a plurality of diodes for turning on the second bipolar transistor Q2.

If the power supply voltage is made sufficiently high during the screening test for defective memory cells, the bipolar transistor Q2
Is turned on, the voltage drop across the resistor R3 increases, and the current flowing through the resistor R1 decreases. The subsequent operation is similar to that of the first embodiment. The present embodiment has the advantage that the rate of decrease of the hold current with respect to the increase of the power supply voltage can be changed relatively gently by setting the value of the resistor R3.

[0014]

As described above, according to the present invention, a power supply outside the normal operating power supply voltage range is supplied to reduce the data hold current, and a memory cell selection test is performed, whereby the conventional selection is performed. There is an effect that a potentially defective memory cell having a low data retention capability that is difficult to detect in a test can be easily detected in a short time test without using a dedicated terminal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of a conventional semiconductor memory device.

[Explanation of symbols]

 1 memory cell array 2 hold current supply circuit 3 bias circuit 4, 4a hold current control circuit D1 diode MC memory cell Q1, Q2 bipolar transistor R1 to R3 resistance WT1 to WTn word line

Claims (3)

[Claims] 1. A memory cell array including a plurality of memory cells arranged in a matrix in a row direction and a column direction, and data hold in each memory cell of a corresponding row provided corresponding to each row of the memory cell array. A hold current supply circuit having a plurality of first bipolar transistors for supplying current and a resistor, and a bias voltage is supplied to the base of each first bipolar transistor of the hold current supply circuit to supply data to the memory cells. A semiconductor memory device having a bias circuit for controlling a hold current to a predetermined value and performing a predetermined function with a power supply within a normal operating power supply voltage range. A data hold voltage is applied from the hold current supply circuit to each memory cell of the memory cell array so as to fulfill the function. And a hold current control circuit that supplies a data hold current to each memory cell of the memory cell array that is smaller than that of the power supply within the normal operating power supply voltage range when the power supply is outside the normal operating power supply voltage range. A semiconductor memory device characterized by the above. 2. A second bipolar transistor in which a hold current control circuit connects an emitter and a collector to a first power supply voltage receiving end and a bias voltage receiving end of the hold current supply circuit, respectively, and a normal operating power supply. A power supply in a voltage range includes a circuit having a second resistor for turning off the second bipolar transistor, and a power supply in a normal operation power supply voltage range for turning on the second bipolar transistor and a plurality of diodes. The semiconductor memory device according to claim 1, which has been written. 3. The hold current control circuit has a third resistor, one end of which is connected to a first power supply voltage receiving end of the hold current supply circuit, and which supplies a first power supply voltage to the first power supply voltage receiving end. A second bipolar transistor having an emitter and a collector connected to the first power supply voltage receiving end and the second power supply voltage supply terminal, respectively, and the second bipolar transistor for a power supply within a normal operating power supply voltage range. 2. The semiconductor memory device according to claim 1, comprising a circuit including a second resistor for turning off the transistor and turning on the second bipolar transistor when the power supply is outside the normal operating power supply voltage range, and a plurality of diodes. ..