JPH05210617A - Bus extending device - Google Patents

Abstract

PURPOSE:To improve the transfer efficiency of data by shortening the length of a single bus cycle of an extending bus. CONSTITUTION:This device is provided with data buffers 11, 12 and error registers 13, 14 corresponding to each of input/output controllers connected through an extending bus 9 to an I/O processor 10, and in the case the data are written to a main memory from the input/output controller, when the proprietary of the extending bus is obtained, write data are stored in a data buffer corresponding to the input/output controller and the proprietary of the extending bus is released, and the proprietary of a basic bus is obtained, the write data stored in the data buffer is written in a main memory, and when an error is generated while a write operation is being executed to the main memory, information relating to its error is stored in an error register, and when no effective write data is present on the data buffer, its error information is sensed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus expansion device for logically connecting a basic bus and an expansion bus in a computer system.

[0002]

2. Description of the Related Art In a computer system, a conventional bus expansion device for logically connecting a basic bus and an expansion bus is a main bus in which an input / output control device connected to the expansion bus is connected to the basic bus. When writing data to the memory, the operation ends when the write data is being written to the main memory via the bus expansion device in order to obtain information (error information) about the error that occurred during data transfer. Waiting for you to release the ownership of the expansion bus.

[0003]

As described above, the conventional bus expansion device holds error information inside the device,
Moreover, since it does not have the function of notifying it, when the input / output control device connected to the expansion bus writes data to the main memory connected to the basic bus, the basic bus and expansion bus are Get the error information via
It is necessary to release the ownership of the expansion bus after the completion of writing the data to the main memory. Therefore, one bus cycle of the expansion bus becomes long, so that the data transfer efficiency is significantly lowered. have.

[0004]

A bus expansion device of the present invention is a bus connected to a main memory and a central processing unit via a basic bus and connected to at least one input / output control device via an expansion bus. An expansion device, which is an I / O processor for controlling the operation of the input / output control device and one for each of the input / output control devices, which is used when writing data to the main memory A data buffer provided, and an error register for storing information relating to an error that occurs when writing data to the main memory and provided for each of the input / output control devices. Information regarding the error is transmitted to the I / O.
It can be sensed by the processor.

[0005]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an embodiment of FIG. 1 connected to a main memory and a central processing unit via a basic bus and controlling input / output via an expansion bus. It is a block diagram which shows the state connected to the apparatus.

In FIG. 2, the bus expansion unit 3 includes a main memory 4 and a central processing unit (CP) via a basic bus 8.
U) 5 and is logically connected to the two I / O controllers 1 and 2 via the expansion bus 9. The input / output control devices 1 and 2 are connected to the input / output devices 6 and 7, respectively.

As shown in FIG. 1, the bus expansion device 3 has data buffers 11 and 12 corresponding to the input / output control devices 1 and 2, respectively.
Reference numerals 1 and 12 are used when the corresponding input / output control devices 1 and 2 write data to the main memory 4, and are fixedly assigned as buffers for storing write data. It is connected to the expansion bus 9.

The data buffers 11 and 12, that is, the error registers 13 and 14 provided corresponding to the input / output control devices 1 and 2, respectively, are the basic bus 8
And a register connected to the I / O processor 10 for storing information (error information) relating to an error that occurs when the bus expansion device 3 writes the data in the data buffer 11 or 12 to the main memory 4. Is.

The I / O processor 10 is connected to the error registers 13 and 14 and the expansion bus 9 and controls the input / output control devices 1 and 2.

Next, regarding the operation of the bus expansion device 3 configured as described above, the input / output control device 1 causes the main memory 4 to operate.
A case will be described as an example where a write operation is performed with respect to.

When the input / output control device 1 acquires the ownership of the expansion bus 9, it outputs the write data on the expansion bus 9 according to the protocol of the expansion bus 9. Accordingly, the bus expansion device 3 stores the write data on the expansion bus 9 in the data buffer 11 according to the protocol of the expansion bus 9. When the write data is stored in the data buffer 11, the input / output control device 1 releases the ownership of the expansion bus 9.

At the same time, when the bus expansion device 3 acquires the ownership of the basic bus 8 and obtains its ownership, the write data stored in the data buffer 11 according to the protocol of the basic bus 8 is transferred onto the basic bus 8. Output to.

If an error occurs while the bus expansion device 3 is writing to the main memory 4, information about the error (error information) is stored in the error register 13.

When the I / O controller 1 notifies the end of DMA to the I / O processor 10 via the expansion bus 9, I / O processor 10
The O-processor 10 waits until there is no valid write data in the data buffer 11 and recognizes the end of DMA, and the error information held by the input / output control device 1 and the error information stored by the error register 13 are recognized. Sense. As a result, the input / output control device 1 to the main memory 4
It is possible to obtain comprehensive error information when transferring data to and from.

[0016]

As described above, the bus expansion device of the present invention is provided with a data buffer and an error register corresponding to each of the input / output control devices connected to the I / O processor via the expansion bus. When writing data to the main memory from the I / O controller, when the ownership of the expansion bus is acquired, the write data is stored in the corresponding data buffer to release the ownership of the expansion bus, and the ownership of the basic bus When the right is acquired, the write data stored in the data buffer is written to the main memory, and when an error occurs during the write operation to the main memory, the information about the error is displayed. Store it in the error register and sense the error information when there is no valid write data in the data buffer. And allows to reduce the length of one bus cycle of expansion bus, there is an effect that it is possible to improve the data transfer efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a state in which the embodiment of FIG. 1 is connected to a main memory and a central processing unit via a basic bus and connected to an input / output control device via an expansion bus.

[Explanation of symbols]

 1 Input / output control device 2 Input / output control device 3 Bus expansion device 4 Main memory 5 Central processing unit (CPU) 6 Input / output device 7 Input / output device 8 Basic bus 9 Expansion bus 10 I / O processor 11 Data buffer 12 Data buffer 13 Error register 14 Error register

Claims (2)

[Claims] 1. A main memory and a central processing unit are connected via a basic bus, and at least one is connected via an expansion bus.
A bus expansion device connected to one input / output control device, the I / O processor controlling the operation of the input / output control device, and the input / output used when writing data to the main memory. One data buffer is provided for each controller, and information about an error that occurs when writing data to the main memory is stored, and one data buffer is provided for each input / output controller. A bus expansion device comprising: an error register provided for each unit. 2. A main memory and a central processing unit are connected via a basic bus, and at least one is connected via an expansion bus.
A bus expansion device connected to one input / output control device, the I / O processor controlling the operation of the input / output control device, and the input / output used when writing data to the main memory. One data buffer is provided for each controller, and information about an error that occurs when writing data to the main memory is stored, and one data buffer is provided for each input / output controller. A bus expansion device, comprising: an error register provided for each of the units so that information regarding the error can be sensed by the I / O processor.