JPH05206809A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To change driving performance in accordance with load capacity to be driven. CONSTITUTION:An output buffer circuit is constituted of the parallel circuit of a first circuit block to be controlled by a control signal CTRL1 and a second circuit block to be controlled by the control signal CTRL2. When the load capacity to be driven is large, both CRTLI and CRTL2 are made '1', and load is driven by two circuit clocks. When the load is small, either one side of CRTL1 or CRTL2 is made '0', and the load is driven by one circuit block.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram of a conventional output buffer circuit of this type. As shown in the figure, in the conventional output buffer circuit, the output data OD is the inverter IV,
And a p-channel MOS transistor (hereinafter referred to as pMO
CMOS composed of Sp) Qp1 and n-channel MOS transistor (hereinafter referred to as nMOS) Qn1
It is output from the output terminal Out via the inverter.

In the circuit of FIG. 4, when the output data OD is "1", pMOSQp1 is on and nMO is
SQn1 is turned off, and "1" is output from the output terminal Out. When the output data OD is "0", pMOSQp1 is off and nMOSQn is
When 1 is turned on, “0” is output from the output terminal Out.

[0004]

A semiconductor integrated circuit having the above-mentioned output buffer circuit is mounted on a printed circuit board together with other semiconductor integrated circuits. In this case, the wiring to be driven by the output buffer circuit, the LSI, and the number thereof are different depending on each product, so that a large difference occurs in the load capacity carried by the output buffer circuit.

However, in the conventional output buffer circuit,
The drive capability of both pMOSQp1 and nMOSQn1 is W /
Since it was fixed to a fixed value determined by the L value, it was not possible to cope with the change in the capacity. That is, when the load capacity to be driven by the output buffer circuit is too large, a situation in which the output buffer circuit cannot be driven occurs or a large transmission time delay occurs. Further, when the load capacity is small, vibration occurs at the time of rising and falling operations, and large spurious is generated. In addition, it consumes an unnecessarily large current.

Therefore, it is an object of the present invention to prevent a large transmission delay time from occurring even when the load capacitance to be driven changes, and to avoid spurious emission and unnecessary current consumption. It is to provide an output buffer circuit that can perform.

[0007]

The output buffer circuit of the present invention comprises a plurality of drive circuits connected in parallel, and at least some of the drive circuits are either in a drive state or a non-drive state according to a control signal. It is designed so that you can select the state.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. As shown in the figure, in this embodiment, the output data OD is input and the control signal C from the microcomputer is input.
Inverters IV1 and NA controlled by TRL1
ND gate ND1, NOR gate NR1, pMOSQp
1 and a first circuit block composed of nMOSQn1 and an output data OD are inputted and controlled by a control signal CTRL2 from a microcomputer, an inverter IV2, a NAND gate ND2, a NOR gate NR.
2, a second circuit block composed of pMOSQp2 and nMOSQn2 is connected in parallel to the output terminal.

The circuit of this embodiment is used as follows. When the load capacity to be driven is large, the control signal CT
Both RL1 and CTRL2 are set to "1". In this case, if the output data OD is "1", pMOSQp1 and pMOSQp2 are on, and nMOSQn1 and nMOS are
Qn2 turns off and "1" is output to the output terminal Out. If the output data OD is "0", p
MOSQp1 and pMOSQp2 are off, nMOS
Qn1 and nMOS Qn2 are turned on and output terminal O
“0” is output to ut.

When the load capacity to be driven is small, the microcomputer instructs the control signal CTRL1 to be "1" and the control signal CTRL2 to be "0". In this case, Qp2 and Qn2 of the second circuit block are always off regardless of the value of the output data OD. On the other hand, in the first circuit block, Qp1 or Qn1 is turned on according to "1" or "0" of the output data OD and outputs "1" or "0" to the output terminal Out.

In this embodiment, the first circuit block and the second circuit block
The driving capability can be switched in three steps by making a difference in the load driving capability between the circuit block of FIG.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. This embodiment has a first configuration similar to that of the circuit of FIG.
No. to which the circuit block No., the output data OD, and the control signal CTRL * (* indicates an overline) are input.
An R gate NR and a second circuit block composed of an nMOS Qn2 having a gate connected to the output terminal of the NOR gate NR are connected in parallel to the output terminal Out.

In this embodiment, "1" is given to the control signal CTRL * under the condition that the load capacitance is small. In this case, the second circuit block is cut off, and the load is driven only by the first circuit block.

When the load capacity is large, the control signal CTRL * is set to "0". Accordingly, when the output data is "0", the load can be driven by Qn1 and Qn2. In this embodiment, even if the load increases,
It is used effectively under circuit conditions where it is not necessary to accelerate the rise time of the signal, but only the fall time.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention. This embodiment is different from the embodiment of FIG. 1 in that the first circuit block is always in the drive state (active state), and only the second circuit block can be selected between the drive state and the non-drive state. It is a thing.

[0016]

As described above, according to the present invention, the output buffer circuit is composed of a plurality of output circuit blocks connected in parallel to the output terminals, and at least a part of the output circuit blocks is in the drive state or the non-drive state. Since it is possible to select the state, the present invention makes it possible to configure an output buffer having an appropriate capacity according to the load capacity to be driven. Therefore,
According to the present invention, it is possible to prevent inconveniences such as an excessive signal transmission delay time due to load capacitance and generation of spurious due to oscillating current.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional example.

[Explanation of symbols]

CTRL1, CTRL2, CTRL * Control signal OD Output data Out Output terminal

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H03K 19/0175

Claims (1)

[Claims] 1. A configuration in which a plurality of output transistors to which output data is input are connected in parallel to an output terminal, and some of the plurality of output transistors can select a cutoff state by a control signal. Output buffer circuit.