JPH05206383A - Semiconductor wafer and method for inspecting the same - Google Patents

Abstract

PURPOSE:To provide a semiconductor wafer which easily allows easy inspection and measurement of the electric characteristic of an IC which is densely mounted and an inspection method thereof. CONSTITUTION:Electrode pads 7A are formed around the IC surface of a section 6A surrounded by dicing lines 3, 3A and 4, 4A on a semiconductor wafer whereupon the IC is formed by the prescribed arrangement. Test pads 8 are formed in response to the pads 7A on an area sandwiched by the two dicing lines 3, 3A and 4, 4A on the opposite side of the IC forming plane, a test pin is permitted to make contact with the pads so as to inspect and measure the electric characteristics. Since the test pads can be formed by the same dimensions and the pitch of the IC electrode pads of the conventional technique, the inspection and measurement of the IC are easily performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer having a large number of semiconductor integrated circuits formed on its surface and a method for inspecting various electrical characteristics of each semiconductor integrated circuit.

[0002]

2. Description of the Related Art A conventional semiconductor wafer and its inspection method will be described with reference to FIGS. FIG. 3 is a plan view showing the outline of the entire semiconductor wafer of the prior art, and FIG. 4 is an enlarged plan view showing the outline of one section of the semiconductor wafer shown in FIG.

In FIG. 3, reference numeral 1 generally indicates a semiconductor wafer. On the surface of the semiconductor wafer 1, a large number of semiconductor integrated circuits (hereinafter simply referred to as “IC”) 2 are formed in a predetermined arrangement. Reference numeral 3 indicates a horizontal dicing line, reference numeral 4 indicates a vertical dicing line, and reference numeral 5 indicates an orientation flat.

An enlarged section 6 surrounded by these dicing lines 3 and 4 is shown in FIG. This one
Around the one section 6, a plurality of electrode pads 7 are formed in a predetermined array.

Conventionally, the general dimensions of these electrode pads 7 are such that one side W is at least 100 μm and the pitch P is 150.
It is about μm. In order to inspect the electrical characteristics of the IC 2 formed in the section 6 as described above, a test pin (not shown) is brought into contact with these electrode pads 7 for measurement.

At present, however, the number of pins in ICs such as gate arrays and LCD drivers is increasing, so that the electrode pads are becoming smaller, more numerous, and narrower in pitch.

[0007]

As the size of electrode pads is further reduced, the number of electrode pads is further increased, and the pitch is narrowed, the contact area of the test pins becomes small, which makes it difficult to align them. As one method for solving this problem, a method is proposed in which a test pad is drawn out from the electrode pad 7 on the passivation film of the IC 2 and formed, and a test pin is brought into contact with such a test pad for measurement. Has been done. However, there is a strong possibility that this method may damage the IC surface through the test pad.
The present invention seeks to eliminate such drawbacks.

[0008]

Therefore, according to the present invention,
Corresponding to the plurality of electrode pads formed in a predetermined array for each section, the test pads are arranged in a predetermined array on the side opposite to the IC formation surface of each of the electrode pads across the dicing line. A test pin was formed and contacted with a test pin to test the electrical characteristics of the IC in each section.

[0009]

Therefore, since the area of the test pad that contacts the test pin can be increased, it becomes easy to align the electrode pad with the test pin regardless of the size and pitch of the electrode pad in the section. Since the test pad is outside the IC formation surface and the inspection is performed outside the IC formation surface, the IC formation surface is not damaged even if the test pin is brought into contact with the test pad.

[0010]

Embodiments of the present invention will be described below with reference to FIGS. 1 and 2. 1 is a plan view showing the outline of the whole semiconductor wafer of the present invention corresponding to FIG.
FIG. 5 is an enlarged plan view showing an outline of one section of the semiconductor wafer shown in FIG. 1 corresponding to FIG. 4.

In the present invention, as shown in FIG. 1, a semiconductor wafer 1A is provided in parallel with the horizontal dicing line 3 and the vertical dicing line 4, respectively, and further, a horizontal dicing line 3A and a vertical dicing line 4A. Assuming that, the IC 2A was formed in the section 6A surrounded by these dicing lines.

Such a section 6A is shown enlarged in FIG. Electrode pads 7A having a small area and a small pitch are formed around the IC formation surface of the section 6A, and the test pads 8 are formed in correspondence with the electrode pads 7A.
Were formed in a zigzag pattern on the surface of the semiconductor wafer 1A on the side opposite to the IC formation surface and between the two dicing lines 3, 3A and 4, 4A. Reference numeral 9 indicates a conductive wire that connects each electrode pad 7A and each test pad 8.

In this embodiment, the length L ₁ of one side of the section 6A is about 10 mm, the distance L ₂ between _two dicing lines is about 300 μm, and the length W of one side of the test pad 8 is about 100 μm. Their pitch P is about 150 m
m could be formed.

Therefore, the test pads 8 can be formed in a sufficiently large area, and their pitches are also sufficient, so that the test pins can be aligned with the test pads 8 and the test pins can be brought into contact with each other to be electrically connected. Various characteristics can be inspected and measured.

After completion of inspection and measurement, this semiconductor wafer 1
Individual IC chips can be obtained by dicing A along the dicing lines 3, 3A and 4, 4A.

[0016]

As is apparent from the above description, since the area of the test pad that contacts the test pin can be increased, the test can be performed with each electrode pad regardless of the size and pitch of the electrode pad in the section. Since the alignment with the pin becomes easy, and the test pad exists outside the IC formation surface and is inspected outside, the IC formation surface is damaged even if the test pin is brought into contact with the test pad. Therefore, there is an excellent effect that the product yield is improved.

[Brief description of drawings]

FIG. 1 is a plan view showing a general outline of a semiconductor wafer of the present invention.

FIG. 2 is an enlarged plan view showing an outline of one section of the semiconductor wafer shown in FIG.

FIG. 3 is a plan view showing an overview of a conventional semiconductor wafer.

FIG. 4 is an enlarged plan view showing an outline of one section of the semiconductor wafer shown in FIG.

[Explanation of symbols]

 1A Semiconductor wafer 2A IC 3 Dicing line 3A Dicing line 4 Dicing line 4A Dicing line 6A Section 7A Electrode pad 8 Test pad

Continued Front Page (72) Keiko Togawa 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (2)

[Claims] 1. A semiconductor wafer in which the same semiconductor integrated circuit is formed in a section of a predetermined array, for each electrode corresponding to a plurality of electrode pads formed in a predetermined array for each section. A semiconductor wafer, characterized in that test pads are formed in a predetermined array between adjacent dicing lines on the side opposite to the semiconductor integrated circuit formation surface of the pads. 2. A method of inspecting a semiconductor integrated circuit according to claim 1, wherein a test pin is brought into contact with the test pad of the semiconductor wafer to inspect electrical characteristics of the semiconductor integrated circuit in each section.