JPH0519789A - Voice encoding device - Google Patents

Abstract

PURPOSE:To facilitate addressing in voice reproduction and enable natural voice reproduction by compressing no-voice sections of a voice signal into frames which have constant length regardless of the length of the no-voice sections. CONSTITUTION:A no-voice detection part 1 detects the no-voice parts from the voice signal S1 and a no-voice counter 2 counts the number of the detected frames. A voice encoding part 4 encodes the voice to be encoded in the voice signal S1. Namely, the voice encoding part 4 encodes the voice parts as they are and compresses the no-voice parts to output data together with the counted value of the no-voice counter 2, so that they are recorded in a memory 5 for code storage. When it is judged that the no-voice part is longer than the specific memory 5 for code storage, and an address generator 3 stops advancing the address from the point of time. Then when the voice part of the voice signal S1 is inputted, the advance of the address is restarted and the encoded voice signal is stored in the memory 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speech coder, and more particularly to a speech coder which focuses on coding a silent portion.

[0002]

2. Description of the Related Art Conventionally, in the case of encoding a voice signal, special processing has been performed for processing a silent portion in order to encode with high efficiency.

[0003] For example, when encoding a silent section with no voice, one of them is a so-called adaptive method in which encoding is performed at a low bit rate with a small number of encoding bits per unit time. This is as follows, for example. That is, as shown in the timing chart of FIG. 5, it is assumed that n frames to n + 7 frames of the voice code sequentially input with the elapse of time t are sequentially encoded from the low memory address to the high memory address. n
There is a silent section from the +3 frame to the n + 5 frame. Therefore, by encoding these sections at a low bit rate, compared with the encoding of the normal voice part,
The compression rate is 1 / k.

On the other hand, there is also known run-length coding in which a silent section without voice is not coded at all.
This is as follows. That is, as shown in the time chart of FIG. 6, in the speech waveform W input with the elapse of the time t, only the n + 1 section and the n + 3 section having a certain threshold value TH or more are coded, as shown in FIG. The n sections and the n + 2 sections below the threshold TH are not targeted for encoding at all. Then, as shown in FIG.
This is a method in which only the n + 1 section and the n + 3 section having voice are connected and encoded.

The conventional speech coding apparatus has improved coding efficiency by any of the above methods.

[0006]

In the case of the first method of encoding the silent section at a bit rate lower than that of the speech section,
The memory amount per unit time in the voice section and the silent section is different. Therefore, if special reproduction such as skipping is performed at the time of decoding, the address skip amount per unit time varies depending on whether the encoded data is voice or not. Therefore, when calculating the addressing at the time of skip, it is necessary to read the memory contents once. As a result, there is a problem that the circuit scale increases and the calculation time also increases.

On the other hand, in the case of the second method in which the silent section is not coded at all, the data of the silent section is completely lost. For this reason, when the decoded voice is played back, the played sound becomes a playback sound in which a silent section is missing. For this reason, there is a problem in that the sound at the time of recording cannot be faithfully reproduced, resulting in an unnatural reproduced sound.

As described above, the conventional speech coding has a problem that the processing becomes complicated at the time of decoding the speech and the reproduced sound becomes unnatural.

The present invention has been made in view of the above,
The purpose is to facilitate addressing at the time of voice reproduction and enable natural voice reproduction.

[0010]

A first speech coding apparatus according to the present invention comprises a silence detecting means for detecting a silent portion of an input speech signal and outputting a silence detecting signal, and a clock outputting the silence detecting signal. A silence counter that counts the number and outputs a counter value, and a voiced part of the input voice signal when the silence detection signal is not output is used as an encoded voice signal, and a silence code is generated during the output of the silence detection signal. The encoding means, the memory for storing the encoded voice signal and the silence code from the encoding means and the counter value from the silence counter means, and when the counter value exceeds a predetermined reference value, Address generation means for stopping the stepping of the address of the memory and stepping up the address when the counter value does not exceed the reference value.

A second speech coding apparatus according to the present invention is the speech coding apparatus according to the first apparatus, wherein the address generating means stops the stepping of the address of the memory when the counter value exceeds the reference value. In addition, it is configured to have a function of returning the address to the address at the output start time of the silence detection signal.

A third voice encoding apparatus of the present invention is the first or second apparatus, wherein the address generating means is
The addressing is configured so that the frame length of the silent portion and the frame length of the voiced portion are equal.

[0013]

The silent part of the input voice signal is detected by the silent detecting means. When it is determined that the silent portion is longer than the predetermined length, the silent code from the encoding means is stored in the memory. However, from this time, the address generating means stops the stepping of the address. After that, when the voice part of the input voice means is input, the stepping of the address is restarted. Then, the audio part is stored in the memory as an encoded audio signal.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a speech coder according to an embodiment of the present invention. As shown in FIG. 1, the silence detector 1 detects a silence from the audio signal S1. The number of detected frames is counted by the silence counter 2. The audio encoding unit 4 encodes the audio to be encoded in the audio signal S1. That is, the voice encoding unit 4
The voice part is encoded as it is, the silent part is compressed, and data is output together with the count value from the silent counter 2. The data from the voice encoding unit 4 is recorded in the code storage memory 5. The memory address Am used for this recording is generated by the address generator 3 based on the count signal from the silence counter 2.

FIG. 2 is a block diagram showing an example of the silence detector 1 of FIG. As shown in FIG. 2, the detector 11 detects the input audio signal S1. As the detection method in this case, methods such as absolute value detection and square detection are used.
The signal detected by the detector 11 is the low-pass filter 12
After being smoothed by, the comparator 13 compares it with a fixed threshold value θ1. Then, the silence detection signal S2 is output for the section of the signal smaller than the fixed threshold θ1.

FIG. 3 is a block diagram showing an example of the silence counter 2 of FIG. As shown in FIG. 3, the silence counter 2 counts by the clock C1k1 and is synchronously reset by the silence detection signal S2. Counter value θn
Is output from the silence counter 2.

FIG. 4 is a block diagram showing an example of the address generator 3 of FIG. As shown in FIG.
Is the counter value θn from the silence counter 2 and the fixed threshold value θ.
2 is compared and the result is output. The logic gate 36 is
The NAND logic of this comparison result and the clock Clk2 is taken and a strobe signal is given to the address register 32.
The increment unit 33 inputs the output data of the address register 32 and outputs the data obtained by adding 1 to the data as the memory address Am. The subtractor 34 inputs the output data of the address register 32 and outputs a value obtained by subtracting the data D from the data as the memory address Am. The switch 35 is based on the output from the comparator 31,
Data of either the output of the increment unit 33 or the output of the subtractor 34 is switched and output, and given to the address register 32.

The output of the comparator 31 is the code storage memory 5
It is also used as a write signal WR for.

The operation of the above-described structure will be described with reference to the timing chart of FIG. By the way, FIG. 7A shows an input voice waveform W,
(B) is a silence detection signal by the silence detector 1, (c) is a counter value of the silence counter 2, and (d) is an address generator 3.
The write signal WR which is the output of the comparator 31 in
(E) shows the count value of the address register 32 of the address generator 3, and (f) shows the strobe signal of the address register 32, respectively.

First, it is assumed that the audio signal S1 is input and the audio waveform W exceeds the fixed threshold value θ1. in this case,
The silence detector 1 does not detect silence. Therefore, the voice encoding unit 4 encodes the voice signal S1 and writes it into the code storage memory 5 as encoded data. At this time, the output data of the increment unit 33 is given to the address register 32 through the switch 35. Therefore, the address is sequentially incremented based on the clock CLK2, and the coded data is sequentially written in the code storage memory 5. At this time, the count value of the silent counter 2 remains “0” and does not advance.

On the other hand, the voice signal S1 is input and the voice waveform W is set to a fixed threshold value θ1 or less. In this case, the silence detector 1
Outputs a silence detection signal S2 as shown in FIG. 7 (b). As a result, the silent counter 2 is displayed in the same figure (c).
, The clock CLK1 starts counting,
The counter value θn is output. When the counter value θn reaches the fixed threshold value θ2, it is determined that encoding and compression should be performed. This judgment is performed by the comparator 31. As a result, as shown in FIG. 7D, the write signal WR and the switching signal CH are sent from the comparator 31, and the switching device 35 is switched. When the switch 35 is switched, as shown in FIG. 7E, the address register 32 is set to the address (k−D) obtained by subtracting the data D from the current address k by the subtractor 34. On the other hand, as shown in FIG. 7F, the clock C supplied to the logic gate 36
1K2 is masked. Therefore, the address register 3
2 will keep the address (k-D). Incidentally, the subtraction data D here is set to data corresponding to the fixed threshold value θ2 set in the comparator 31. on the other hand,
The counter value θn from the address generator 3 is a fixed threshold value θ2.
It is assumed that the write signal WR indicating that the value exceeds the limit is output. At this time, the voice encoding unit 4 writes a silence mark in the code storage memory 5 instead of the encoded data of the voice signal S1. The address register 32 holds the address (k−D) as long as the silent section continues. Silence counter 2
Keeps counting silent periods. Next, the audio signal S1
When the voice waveform W of the sound exceeds the fixed threshold θ1, the silence detector 1
The silence detection signal S2 from is lost. As a result, the silent counter 2 stops the counting operation while keeping the count value n at that time, and is then synchronously reset to return the counter value n to "0". Prior to this, the voice encoding unit 4 records the count value n of the silence counter 2 in the code storage memory 5. As a result, as shown in FIG. 9, the code storage memory 5 records the encoded data of the voice encoding unit 4 up to the state of (a), but the count value θn of the silence counter 2 becomes the fixed threshold θ2. When it reaches, it is judged as silence, and at this time, as shown in (b), a silence mark is recorded in the memory address where the address is returned by the data D, and thereafter the address is not advanced and the next voice section starts. Then, n, which is the counter value θn of the silent counter 2, is recorded.

By returning to the voice section and the counter value θn returning to “0”, the counter value θn is fixed to the fixed threshold value θ.
It becomes smaller than 2. Therefore, the write signal WR disappears, and the switching unit 35 also moves from the subtractor 34 to the increment unit 33
Switch to the side. As a result, the address register 32 is
Again, the address (k-D) is synchronized with the clock Clk2.
Then, the increment operation is started from (k-D + 1). As a result, the voice signal S1 encoded by the voice encoder 4 is sequentially written in the code storage memory 5.

The voice coded data written in the code storage memory 5 as described above is as shown in FIG.
The silence mark and the number of frames in the silent section are recorded in the silent data format in the silent section, and the encoded audio data is recorded in the audio data format in the audio section.

In order to reproduce the coded voice data recorded in the above format, the coded voice data may be reproduced as it is while advancing the address of the code storage memory 5 in the voice data format section. On the other hand, in the silent data format section, it is only necessary to detect the silent frame by the silent mark, stop the address of the code storage memory 5 in that section, and continue to reproduce the silent data. At the same time, the number of silent section frames is counted, and when the count value becomes full, the address of the code storage memory 5 may be advanced without stopping. If it is desired to skip the silent section, it is sufficient to proceed without stopping the address of the code storage memory 5. As shown in FIG. 10, if the data size is the same in the silent data format and the audio data format, it is not necessary to switch the address control between the silent part and the audio part.

When the silent data format and the audio data format have the same data size, addressing is facilitated, and special reproduction such as high-speed search, fast-forward, and rewind is realized without reading the contents of the data. You can

According to the above configuration, the silent section is compressed into one frame regardless of the length of the continuous silent section. Therefore, the longer the silent section, the higher the data compression rate. Now, it is assumed that the ratio between the voice section and the silent section is 1: u. A comparison will be made with the case where the silent part is compressed to 1 / k with respect to the voice part by using the compression method as shown in FIG. The compression rate α1 that can be realized by the method as shown in FIG. 5 is α1 = (1 + u) / {1 + u (1 / k)} = (1 + u) · k / (k + u), and the compression rate α2 in the method of this embodiment is α2 = (1 + u) / 2. If u> k, then α1 <α2, and in the present embodiment, the longer the silent section,
Higher data compression rate. Further, there is an advantage that it is not necessary to expand the silent section even when skipping the silent section.

FIG. 8 shows a configuration example of the address generator 3. The difference between the configuration of FIG. 8 and the configuration of FIG. 4 is that the subtractor 34 and the switch 35 are omitted, and the configuration is simple. When the silent section is discriminated, the silent counter 2 has already advanced the count to the fixed threshold θ2. However, in this example, the address of the address register 32 is not returned but is simply stopped. As a result, silent data is recorded in the code storage memory 5 only for the frames corresponding to the fixed threshold value θ2, which is also disadvantageous in terms of compression rate. However, there are advantages that the circuit configuration is simple and the cost is low.

In the above embodiment, each component is shown as an individual circuit configuration. However, the same function can be realized by using a microcomputer or digital signal processor controlled by software. Further, the counter and the like can be realized by an analog circuit such as an integrator instead of the digital count. Further, in the above-described embodiment, in order to give the address value to the address register 32, the switch 35 switches the output values of the two circuits of the subtractor 34 and the incrementer 33. However, the increment unit 3
3 and the subtractor 34 may be configured by a common arithmetic unit, and the arithmetic value may be switched by a switching signal to the switching unit 35.

It should be noted that the voice encoding device 4 is a PCM.
Various encoding methods such as (pulse code modulation), ADM (adaptive delta modulation), ADPCM (adaptive differential pulse code modulation), and APC-AB (adaptive predictive coding-adaptive bit allocation) are applicable. . The voice signal S1 input to the voice encoding unit 4 may be an analog signal or a digital signal.

As the code storage memory 5, not only a semiconductor memory but also a magnetic disk or a magnetic tape may be used, and any medium capable of recording data can be applied. Also, if a real-time recording is not required, a slightly slower memory can be applied.

Further, the silence counter 2 is operated by the voice signal S1.
Is reset when the magnitude exceeds the fixed threshold θ1, but the silent counter 2 may be reset when the time over the fixed threshold θ1 exceeds a certain time. The silence counter 2 is not limited to the up counter, but may be the down counter.

[0033]

As described above, according to the embodiment of the present invention, the silent section of the audio signal is compressed into a frame of a constant length regardless of its length, so that the silent section is long. It is possible to increase the compression rate in the case of continuing, and the data handling during playback is easy and the circuit configuration is simple, and the silence counter will not judge that there is no silence unless it continues for a certain period of time or more. As a result, the quality of the reproduced voice can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a speech coder according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a silence detecting section in FIG.

FIG. 3 is a block diagram showing an example of the silence counter of FIG.

FIG. 4 is a block diagram showing an example of an address generator 3 of FIG.

FIG. 5 is a timing chart showing an example of a conventional audio encoding method.

FIG. 6 is a timing chart showing another example of a conventional audio encoding system.

FIG. 7 is a timing chart for explaining the operation of the circuits of FIGS.

FIG. 8 is a partial block diagram of a speech coder according to another embodiment of the present invention.

FIG. 9 is an explanatory diagram of a recorded state of a silent section in the code storage memory.

FIG. 10 is an explanatory diagram of a recording format in a code storage memory.

[Explanation of symbols]

1 silence detector 2 silence counter 3 address generator 4 Speech coding unit 5 Code storage memory 11 detector 12 Low-pass filter 13 Comparator 31 Comparator 32 address register 33 increment unit 34 Subtractor 35 switch 36 logic gates

Claims (3)

[Claims] 1. A silence detecting means for detecting a silence portion of an input voice signal and outputting a silence detection signal; a silence counter for counting the number of clocks during the silence detection signal output and outputting a counter value; The voiced part of the input voice signal when the detection signal is not output is a coded voice signal, and a silence code is generated during the output of the silence detection signal, a coding means, and a coded voice from the coding means. A memory for storing a signal, a silence code, and a counter value from the silence counter means; and when the counter value exceeds a predetermined reference value, the stepping of the address of the memory is stopped, and the counter value is the A voice encoding device, comprising: address generating means for incrementing the address when the reference value is not exceeded. 2. When the counter value exceeds the reference value, the address generating means not only stops the stepping of the address of the memory, but also sets the address to the address at the time of starting the output of the silence detection signal. 3. The device of claim 2, configured as having a rewind function. 3. The apparatus according to claim 1, wherein the address generating means performs addressing so that a frame length of a silent portion and a frame length of a voiced portion become equal to each other.