JPH05197652A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To enable sufficient control to communication between processors with large capacity by improving efficiency for communication control by securing a buffer at the transmitting destination while referring to the empty buffer information area of a common memory part in the case of transmission. CONSTITUTION:A common memory 1b is provided with a reception enable processor register area and an empty buffer information area to be used as common resources. Respective microprocessors 1d-1g register it on the reception enable processor register area of the common memory 1b whether data can be received from the other processor or not. Further, it is registered on the empty buffer information area of the common memory 1b whether each buffer of the own device is empty or not. In the case of transmission, the processor at the transmitting destination is selected by the respective processors 1d-1g while referring to the reception enable processor register area. Then, the buffer at the transmitting destination is secured while referring to the empty buffer information area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control unit for controlling communication between a plurality of processing devices and an inter-processing device communication control system using the configuration thereof.

[0002]

2. Description of the Related Art Conventionally, as disclosed in Japanese Patent Application Laid-Open No. 57-6933, there is an invention regarding a processing method of a communication control device when an abnormal state occurs in communication between processing devices. In the above-mentioned conventional technology, a processor status register is installed for each processor connected to the communication controller, and the processor status register stores whether or not an abnormality has occurred between the processor and the processor, When a data transfer command is issued, whether the start process or the data transfer process is executed is controlled by the value of the register. This prior art does not consider the control efficiency in the normal state of inter-processor communication.

Further, conventionally, when communication is performed between a plurality of processing devices, a processing device of a transmission source inquires of a plurality of other processing devices as to whether or not reception is possible, and processing that enables reception. Sending to the device.

[0004]

In the above-mentioned prior art, since the processing device of the transmission source inquires of a plurality of other processing devices whether or not reception is possible, the number of processing devices increases. In addition, when the number of terminals connected to the processing device increases and the processing device has a large capacity, there is a problem that the inquiry becomes complicated and the processing capacity decreases.

An object of the present invention is to provide a multiprocessor system capable of improving the efficiency of inter-processor communication control and sufficiently controlling large-capacity inter-processor communication.

[0006]

In order to achieve the above object, a plurality of processors for controlling communication, a transmission line for connecting the processors, and a terminal or another relay device corresponding to each of the plurality of processors are provided. In a multiprocessor system having a processing device connected to a node for sending and receiving data, and a plurality of buffers for storing data corresponding to each processor and each processing device, a common processor capable of reading and writing from each processor Has a memory section,
The common memory unit has a free buffer information area corresponding to each of the plurality of buffers, the free buffer information area indicating whether each buffer is free or not, and the processor is one of the buffers provided corresponding to the processor. By registering whether each buffer is free or not in the free buffer information area, and referring to the free buffer information area during transmission,
It has means for securing a buffer at the destination.

The common memory unit has a receivable processing device registration area for each processing device, which indicates whether or not the processing device can receive data from another processing device. The destination processing device is selected by registering in the receivable processing device registration area whether data from another processing device can be received or not, and referring to the receivable processing device registration area at the time of transmission. Can have means.

The common memory unit further has a receivable processing device registration area for copying the receivable processing device registration area, and one receivable processing device registration area is for registering a receiving side processor. The other receivable processing device registration area for duplication is used for rewriting of the transmitting side processor at the time of transmission, and the processor refers to the duplication receivable processing device registration area at the time of transmission and Select the processor,
It is possible to have means for rewriting the receivable processing device registration area for duplication so that it cannot be received. At the time of transmission, the processor refers to the receivable processing unit registration area for duplication, and if all the receivable processing apparatus registration areas for duplication are unreceivable, the reception side processing for registration of the receiving side processor is performed. It has means for instructing to copy the contents of the device registration area.

[0009]

Each processor registers whether or not it is possible to receive data from another processing device in the receivable processing device registration area of the common memory unit, and registers in the free buffer information area of the common memory unit. Register whether each buffer of its own device is empty or not in the corresponding place.

At the time of transmission, each processor selects the transmission destination processing device by referring to the receivable processing device registration area for duplication, and secures the transmission destination buffer by referring to the empty buffer information area. Then, the receivable processing device registration area for duplication can be rewritten as unreceivable.

Further, when the processor refers to the receivable processing unit registration area for duplication, if all the receivable processing unit registration areas for duplication are unreceivable, the receiving processor for registration of the receiving side processor Instruct to copy the contents of the processable device registration area.

[0012]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the configuration of the present invention, and 1a shows an inter-processor communication control section (hereinafter simply referred to as a control section). The multiprocessor system shown in this embodiment can be used, for example, in a central processing system of a digital exchange. In the control unit 1a, the common memory 1b
(CM) and multiple microprocessors (PC1d, 1e, 1
f, 1g) are connected by a common bus 1c. The common memory CM1b can be read and written by each microprocessor. The common memory CM1b has a receivable processing device registration register R used as a common resource.
It may have an EW and an empty buffer information register BRF. When the common memory CM1b is a RAM or the like, a receivable processing device registration area and an empty buffer information area may be provided. Each register will be described later. Each microprocessor has a corresponding processing device (SP1h,
1i, 1j, 1k) are connected one by one or two or more. That is, each microprocessor connected to each processing unit controls communication on the bus. In addition, each microprocessor can have a buffer for temporarily storing data for data transfer, a register for transmission, a register for reception, and a transfer end display register. Controls communication via the common bus. Further, the buffer may be provided outside each microprocessor or inside the processing device, instead of inside each microprocessor. The buffer can read and write data transmitted and received from the processing device and has a plurality of areas. The microprocessor can instruct the buffer to send or receive to the bus. A bus arbiter for controlling the bus is connected to the common bus 1c. When transmitting data on the bus, each microprocessor starts transmission after obtaining permission from the bus arbiter that controls communication on the bus. The common memory CM1b may be included in the bus arbiter. In addition, terminals such as a telephone, a FAX, a data terminal, and other relay devices and exchanges are connected to each processing device via a line, and the processing device performs line control. In this configuration, each processing device can communicate with each other under the control / processing of the corresponding microprocessor, and can refer to or rewrite the register in the corresponding microprocessor.

FIG. 2 shows a procedure of communication control in the control unit having the configuration shown in FIG. As an example of the case where the processing device 1i shown in FIG. 1 transmits and the processing device 1k receives, the procedure of communication control of the microprocessor in the control unit corresponding to each processing device will be described with reference to FIG. explain. Further, the configuration of each register in the processing device for transmission and reception and the configuration of the register in the common memory CM will be described with reference to FIGS. 3 to 6.

In FIG. 2, the leftmost portion shows the processing operation of the microprocessor 1e (hereinafter referred to as the transmission microprocessor) corresponding to the transmission processing device 1i, the middle portion shows the register on the common memory CM, The right part shows the processing operation of the microprocessor 1g (hereinafter referred to as the reception microprocessor) corresponding to the reception processing device 1k.

The microprocessor has a receiving register and a buffer. This configuration is shown in FIG.
It is shown in (b), FIG. 3 (c) and FIG. 4 (a).

FIG. 3B shows an example of the structure of the reception control word RCW. In FIG. 3B, a reception control word (RCW) of 1 word is provided in a specific area of the memory in the microprocessor in correspondence with the reception buffer, and the processing device sets the reception source memory start address RMA in the reception control word RCW to Set the start address of the receive buffer. The start address of each area of the reception buffer is set in advance in the reception source memory start address RMA. RFLG indicates whether the reception buffer area specified by the reception source memory start address RMA is empty (buffer empty = 0) or blocked (buffer blocked = 1). When the buffer is empty, the microprocessor Is set to 0 and rewritten to 1 when data is transferred.

FIG. 3C shows a configuration example of the reception buffer. The microprocessor uses the transmission source processor subsystem number SPN as reception control information when receiving data.
After writing the destination processor subsystem number DPN and the transfer word number WC at the head of the reception buffer, RFLG of the reception control word RCW is rewritten to 1. The processing device refers to this reception control word RCW to detect the arrival of data.

FIG. 4A shows the transfer end display register TEF.
Shows the configuration of. In FIG. 4A, the transfer end display register TEF allocates 1 bit to each area of the reception buffer in the microprocessor, and indicates whether the buffer area is ready for reception processing (or receiving) or reception completion. It is a register shown. The receiving process in this case is
After the transfer data is received by the receiving microprocessor from the destination microprocessor, the data is transferred to the processing device or is sent to the line. The area of the reception buffer corresponds to the reception control word RCW shown in FIG. When the data transfer end state is reached, the processing device sets the corresponding bit to 0,
When transfer processing is possible, the reception microprocessor sets 1 in the reception supplement processing.

The registers on the common memory CM are shown in FIG.
And shown in FIG.

FIG. 6 shows the structure of the receivable processing device registration register REW on the common memory CM. Common memory C
The receivable processing device registration register REW on M corresponds to each microprocessor, and which microprocessor corresponds to the microprocessor is set in advance in accordance with the bit position of the register. If it is receivable, the receiving microprocessor sets the bit to 1 at the position corresponding to the own device of the receivable processing device registration register REW. The receivable state means a state in which the microprocessor and the processing device are activated and communication is possible. In FIG. 6, the receivable processing device registration register REW
Reference numeral 1 is dedicated to registration from the receiving microprocessor, and the receivable processing device registration register REW2 is a duplicate of the receivable processing device registration register REW1 and is dedicated to access from the transmitting microprocessor. In the initial state, all the bits of the receivable processing device registration register REW1 and the receivable processing device registration register REW2 are set to 0, and the corresponding bits are set to 1 by registration from the reception microprocessor. FIG. 6 shows an example in which two reception processing devices corresponding to 2 bits from the right of the receivable processing device registration register REW1 are registered. Receivable processing device registration register REW
When all the bits of 2 are 0, the contents of the receivable processor registration register REW1 are copied to the receivable processor registration register REW2 by the transmission process by the access from the transmission microprocessor. After that, in the transmission processing, the receivable processing device registration register REW2 is used to search for a bit that is 1, and after selecting the reception processing device, the bit corresponding to the selected reception processing device is updated to 0. A method of using the two receivable processing device registration registers REW will be described later.

FIG. 4B shows a configuration example of the empty buffer information register BRF on the common memory CM. The empty buffer information register BRF is a register indicating whether the buffer of the reception processing device is empty or in a closed state in correspondence with the buffer of the reception processing device. Is used to write 1 to the bit corresponding to the buffer.

First, the processing operation of the receiving microprocessor will be described.

In FIG. 2, the receiving microprocessor registers in the receivable processor registration register REW on the common memory CM to use as a common resource when the apparatus starts up and becomes its own receivable processor. , Register that it is a receivable processing device. Next, the receiving microprocessor confirms the transfer end display register TEF in the microprocessor as a process for searching for a free buffer. The reception microprocessor searches the transfer end display register TEF, and reads out the reception control word RCW indicating the start address of the reception buffer area corresponding to the bit for which the transfer processing end is set to 0. The receiving microprocessor sets the bit of the transfer end display register TEF to 1 to indicate that the transfer is possible. Further, the corresponding bit of the empty buffer information register BRF on the common memory CM indicates that it is an empty buffer.

As described above, each of the microprocessors periodically executes the empty buffer supplementing process until the start of reception from the transmitting process.

Next, the processing operation of the transmission microprocessor will be described.

The microprocessor has transmission registers and buffers. The structure of this register is shown in FIG.

FIG. 3A shows an example of the structure of the transmission request display word and the transmission request control word in the transmission buffer. A 1-word transmission request display word (SRW) is provided in a specific area of a memory unit in the microprocessor, and when a communication request occurs, the processing device sets the presence / absence of a transmission request for each bit in the word. Further, a transmission request control word (SCW) is provided corresponding to the bit of the transmission request display word (SRW). here,
Source processor subsystem number (processor SP
N), the source memory start address (SMA), the destination processor subsystem number (DPN) and the transfer word number (WC) are provided, and the control device writes the control information when there is a transmission. Destination processor subsystem number DPN
Has a portion of DFLG indicating whether or not the destination is specified. If there is a designation, 0 is set, and if there is no designation, 1 is set. If specified, it is transmitted based on the destination processor subsystem number DPN. If not specified, the destination processor can be arbitrarily selected. The number of transfer words (WC) indicates how many transfer data are in word units. In the example of FIG. 3A, there are two transmission requests on the transmission request display word (1
, There is a request, and 0: no request), and the control information is set in the transmission request control words # 0 and # 1, respectively. If it is not necessary to specify the destination when performing the load balancing process (the destination may be transmitted to any subsystem), the DFL of the destination processor subsystem number DPN
Set G to 1. (When DFLG = 0, the designation of the destination processor subsystem number DPN is valid).

A communication request generated from each processing unit is detected and data transfer is executed on the microprocessor side by the following procedure.

Upon receiving the transmission request from the line side, each processing unit sets the presence or absence of the transmission request in the transmission request display word (SRW) and sets the control information in the transmission request control word (SCW).

Next, the transmission microprocessor reads the transmission request indication word SRW and detects the transmission request. SF
It is assumed that there is a transmission request when LG = 1 and there is no transmission request when SFLG = 0. If there is a request to send,
The transmission microprocessor has a corresponding transmission request control word S
The destination processor subsystem number DPN of the CW and the information of the receivable processing device registration register REW on the common memory CM are read. If there is the destination processor subsystem number DPN, it is determined whether the corresponding processing device is receivable by referring to the receivable processing device registration register REW. Destination processor subsystem number DP
If N is not present, the receivable processing device registration register REW
A receivable processing device is selected by referring to.
After selecting the reception processing device, the transmission microprocessor sets 1 to secure the buffer in the corresponding bit of the empty buffer information register BRF. Then, based on the designation of the transmission source memory start address SMA and the transfer word number WC, data transfer is performed to the secured empty buffer area of the transmission destination. The transmission microprocessor adds the bit number of the empty buffer information register BRF to the transfer data. The receiving microprocessor receives the receiving control word RCW from the bit number.
The area of the receiving buffer is designated by referring to the receiving source memory start address RMA in. Alternatively, the transmission microprocessor directly refers to the reception source memory start address RMA in the reception control word RCW in the reception microprocessor,
You may transfer. When the transfer is completed, the reception microprocessor issues a start instruction to the reception processing device so that the reception microprocessor performs reception processing. The transmission request can be periodically executed in the transmission process until the data arrival notification by the reception process is returned.

In the reception processing, when the reception microprocessor activates the reception processing device for the reception processing, the reception microprocessor transfers the data in the buffer to the corresponding processing device, or Send it to the line as it is. After the transfer is completed, the processing device sets the corresponding bit of the transfer end display register TEF to 0. Further, the receiving microprocessor, after notifying the transmitting microprocessor of the arrival of the data, returns to the above-mentioned periodical empty buffer supplement processing, and again confirms the transfer end display register TEF.

Upon receipt of the data arrival notification from the receiving microprocessor, the transmission processing notifies the processing device of the completion of transmission and then returns to the transmission request detection processing described above.

As described above, by performing the transmission processing and the reception processing independently in each microprocessor, the processing in each microprocessor can be performed in parallel and efficient communication can be performed. For example, the transmission process can be performed at the same time during the reception periodic free buffer supplement process.

The above is the operation of the inter-processor communication control in the present embodiment. Below, the processing operation for realizing the even allocation of the processor communication of the present embodiment will be described by changing the bit of the register used. This will be described in detail with reference to FIG.

FIG. 5 shows the procedure for selecting the receiving microprocessor in the communication control processing operation. In FIG. 5, REW1 and REW2 are the receivable processing device registration registers REW shown on the common memory CM in FIG. 2, each having a bit corresponding to each reception processing device, and the receivable processing device being processed by the reception microprocessor. 1, the unreceivable processing device is displayed as 0. In FIG. 5, when the microprocessor can receive the signal, it sets 1 in the corresponding bit of the receivable processor registration register REW1. Receivable processing device registration register R
When EW2 is all 0 and there is an instruction by the transmission request from the transmission microprocessor, the receivable processor registration register REW1 is stored in the receivable processor registration register REW1.
Copy the contents of. When the transmitting microprocessor accesses the receivable processing device registration register REW2, it uses a T & S instruction (Test and Set) for exclusive processing. That is, while one transmitting microprocessor is accessing the receivable processing device registration register REW2 and transferring data, access from other transmitting microprocessors is excluded. The transmitting microprocessor sets the receivable processing device registration register REW2 to 0 after the data transfer is completed. The receivable processor registration register REW2 is opened to allow access to the receivable processor registration register REW2 for transmission processing by another transmitting microprocessor. In addition, the receivable processing device registration register REW
When all the bits of 2 become 0 again, if there is an instruction by the transmission request from the transmission microprocessor, the contents of the receivable processor registration register REW1 are copied to the receivable processor registration register REW2. Since the receivable processing device registration register REW1 can be accessed, the reception microprocessor can set a bit when its own device starts up and becomes receivable.

By performing these processes by the respective transmitting microprocessors, the respective microprocessors can perform the processes in parallel, and a system guaranteeing exclusivity can be constructed.

Further, after the reception processing device is registered, the reception enable processing device registration register RE by the transmission microprocessor is set.
For access to W2, if the destination is not decided, it has the property of searching sequentially from the smallest number (0th bit) of REW2 and updating the first detected bit of 1 state to 0 state. Let As a result, the transmission microprocessor sequentially selects the registered reception processing devices from the one corresponding to the smallest number (0th bit) of the receivable processing device registration register REW2.

Further, in this embodiment, by providing the receivable processing device registration register REW2, the following effects can be obtained. The data of the initially registered reception processing device (reception enable processing device registration register REW1) is copied to the reception enable processing device registration register REW2 by transmission processing, and all the registered reception processing devices are used (reception Re-registration of the reception processing device is prevented from being performed until all the bits of the processable device registration register REW2 become 0). If the receivable processing device registration register REW2 is not provided, the registered contents of the receivable processing device registration register REW1 are updated by the registration request of the reception processing device, and therefore the above processing is performed with respect to the receivable processing device registration register REW1. If this is done, the reception processing device corresponding to the bit closer to the youngest bit (0th bit) is preferentially selected, and equality is not guaranteed in the reception processing device selection. In the present embodiment, the series of processes described above avoids concentration of the selection of the reception processing devices and guarantees the uniformity in the selection of the reception processing devices.

In this series of processing, the empty buffer is
It is also effective when assigned to the transmitting microprocessor. In the empty buffer information register BRF shown in FIG. 2, a register dedicated register and a select dedicated register are used, and the access from the transmitting microprocessor is performed by T & S, so that double selection of empty buffers and concentration of selection to one empty buffer are concentrated. Can be avoided, and efficient communication processing can be performed.

That is, by using the present invention, the control unit can efficiently distribute the load and can improve the efficiency of communication between the processing devices.

As described above, according to the present embodiment, it is possible to perform parallel processing and guarantee exclusivity and equality when a plurality of transmission microprocessors select a reception processing device and an empty buffer. This makes it possible to improve communication efficiency.

[0043]

According to the present embodiment, in a multiprocessor system, it is possible to improve the efficiency of communication control between processing devices and perform sufficient control for communication between large-capacity processing devices.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an inter-processor communication control unit that is an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an embodiment of a communication control procedure between processing devices according to the present invention.

FIG. 3 is an explanatory diagram showing an example of a configuration of a register used in inter-processor communication control according to the present invention.

FIG. 4 is an explanatory diagram showing an example of a configuration of a register used in inter-processor communication control according to the present invention.

FIG. 5 is an explanatory diagram showing an example of receiving processor selection according to the present invention.

FIG. 6 is an explanatory diagram showing an example of the configuration of a register used in inter-processor communication control according to the present invention.

[Explanation of symbols]

1a ... Inter-processor communication control device, 1b ... Common memory, 1
c ... Bus, 1d / 1e / 1f / 1g ... Microprocessor, 1h / 1i / 1j / 1k ... Processor.

Claims (4)

[Claims] 1. A plurality of processors that control communication, a transmission line that connects the processors, and a processing device that corresponds to each of the plurality of processors and that is connected to a terminal or another relay device to transmit and receive data. In a multiprocessor system having a plurality of buffers for storing data corresponding to each processor and processing device, each processor has a common memory unit that can be read from and written to, and the common memory unit is Each of the plurality of buffers has a free buffer information area indicating whether the buffer is free or not, and the processor has a free buffer information area in the buffer provided corresponding to the processor. Register whether the buffer is empty or not, and refer to the empty buffer information area when sending Multiprocessor system characterized in that it has a means for securing a buffer. 2. The common memory unit according to claim 1, having a receivable processing device registration area for each processing device, which indicates whether or not the processing device can receive data from another processing device. However, the processor registers whether or not it is possible to receive data from other processing devices in the receivable processing device registration area, and at the time of transmission, by referring to the receivable processing device registration area, A multiprocessor system having means for selecting a preprocessor. 3. The common memory unit according to claim 2, further comprising a receivable processing device registration area for copying the receivable processing device registration area, wherein the receivable processing device registration area 1 is provided on the receiving side. It is used for registering the processor, and the other receivable processor registration area for duplication is used for rewriting of the sending processor at the time of transmission, and the processor refers to the receivable processor registration area for duplication at the time of transmission. Then, the multiprocessor system is provided with a means for selecting a destination processing device and rewriting the receivable processing device registration area for duplication to unreceivable. 4. The processor according to claim 3, wherein the processor refers to the receivable processing device registration area for copying at the time of transmission, and if all the receivable processing apparatus registration areas for copying are unreceivable, the receiving side A multiprocessor system having means for instructing to copy the contents of the receivable processor registration area for registering the processor.