JPH05197448A - Mother board for non-stop type computer - Google Patents

Abstract

PURPOSE:To exchange a substrate without stopping a device at the time of the occurrence of a fault at any substrate, in a non-stop type computer. CONSTITUTION:At the time of the occurrence of the fault at any substrate, the substrate at which the fault occurs is separated from a bus 5 by using a bus connection control signal 6, so that the disconnection of a power source attained. The pertinent substrate can be completely separated from the device, so that the exchange of the substrate can be attained while the device is being operated. And also, at the time of restoring the substrate, the substrate can be restored without stopping the device by the reverse procedure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motherboard used in a non-stop computer in which a plurality of boards are connected to each other by a motherboard.

[0002]

2. Description of the Related Art A conventional motherboard is simply a conductor connecting between connectors 104 connected to a motherboard 101 via a bus 105 as shown in FIG.

[0003]

In the conventional motherboard 401 described above, as an example, as shown in FIG.
04, bus 405, first CPU board 410, second C
PU board 411, first memory board 412, second memory board 413, first I / O board 414, second I / O
When the first I / O board 414 in the computer device 400 combined with the board 415 is duplicated, the device 400 itself is duplicated and continues to operate. However, since the board is directly connected to the bus 405 of the motherboard 401, in order to replace the failed first I / O board 414, the bus 405 connected to the motherboard of all the boards should be replaced. There was no choice but to disable or turn off the power once.

An object of the present invention is to provide a motherboard for a non-stop computer in which the power supply of a board connected to a connector can be turned on and off from any board mounted on the motherboard. is there.

[0005]

In order to achieve the above object, in a motherboard of a non-stop computer according to the present invention, a motherboard for use in a computer in which a plurality of boards are connected to each other by a motherboard is used. It has a built-in 3-state buffer and relay on its side, and it is possible to control the 3-state state of the buffer and the power on / off of the board connected to the connector from any board mounted on the motherboard. It was done.

Further, when a failure occurs in any of the boards, the bus connection control signal is used to disconnect the failed board from the bus to disconnect the power supply.

At the time of restoration, the board is connected to the bus by using the bus connection control signal.

[0008]

In the motherboard of the non-stop computer according to the present invention, a 3-state buffer and a relay are built in the motherboard, and the 3-state state of the buffer and the power-on of the board connected to the motherboard are turned on and off. You can control the off from any board mounted on the motherboard.

[0009]

The present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing a motherboard of a non-stop computer according to an embodiment of the present invention.

In FIG. 1, a bus 5 passing through the mother board 1 passes through a CPU side bus connection control mechanism 2 and a connector 4
The CPU board is connected through the connector 4.

Similarly, the bus 5 is connected to the connector 4 through the bus connection control mechanism 3, and the peripheral device boards are connected through these connectors 4.

Further, the bus connection control line 6 output from the CPU side bus connection control mechanism 2 includes the respective bus connection control mechanisms 3,
And a CPU side bus connection mechanism of another system.

FIG. 3 is a block diagram showing the CPU side bus connection control mechanism 2. A data signal 218 from the CPU,
The output signal 215 from the CPU and the bus control signal 214 from the CPU pass through the 3-state buffer 203, respectively, the data signal 225 to the bus and the output signal 22 to the bus.
3 and the bus connection control signal 222 to the bus connection control mechanism and the CPU side bus connection control mechanism of the other system.

At this time, the data signal 218 from the CPU
In the buffer for receiving, the input side is an input control line 217 from the CPU, and the output side is an OR gate 20 for controlling the output.
The output control signal 219 from the CPU is connected via the circuit 5.

The input signal 224 from the bus is connected to the input signal 216 to the CPU via the buffer 204. At this time, of the input signals 224 from the bus, the signal that needs to be pulled up is connected to the + 5V power source via the pull-up resistor 202.

The bus connection control signal 222 is roughly divided into an output permission signal and a power supply control signal. Output enable signal 2
10 and the power supply control signal 211 are bus connection control signals output from the bus connection control mechanism of the other system.

Output permission signal 210 and power supply control signal 211
Are pulled up by pull-up resistors 202 and connected to NOT gates 201, respectively.

An internal bus output permission signal 212 and an internal power supply control signal 213 are output from each NOT gate 201, and the internal bus output permission signal 212 receives an output signal 215 from the CPU and a bus connection control signal 214 from the CPU 3. The state buffer 203 is connected to the OR gate 205 that controls the output of the data signal 218 from the CPU, and the internal power supply control signal 213 is connected to the control coil of the relay 206. However, the relay 206 is of a type in which the contact is opened when the internal power supply control signal 213 is "H".

The power supply 226 from the motherboard is the relay 2
06 is connected to one contact and the other contact is CP
The power supply 221 to U is connected.

FIG. 3 is a block diagram of the bus connection control mechanism.

The data signal 318 from the board and the output signal 315 from the board are each a 3-state buffer 303.
Through, to a data signal 325 to the bus and an output signal 323 to the bus, respectively.

At this time, in the buffer for receiving the data signal 318 from the substrate, the input control line 317 from the substrate on the input side and the output control signal from the substrate via the OR gate 305 for controlling the output on the output side. 319 is connected.

The input signal 324 from the bus is connected to the input signal 316 to the board via the buffer 304. At this time, among the input signals 324 from the bus, the signal that needs to be pulled up is the pull-up resistor 3 to the + 5V power source.
02 is connected.

The 1-system output permission signal 310 and the 1-system power supply control signal 311 are bus connection control signals output from the 1-system bus connection control mechanism, and are the 2-system output permission signal 330.
The power supply control signal 331 for the second system is a bus connection control signal output from the second system bus connection control mechanism.

The output permission signal 310 of the 1st system, the power supply control signal 311 of the 1st system, the output permission signal 330 of the 2nd system, and the power supply control signal 331 of the 2nd system are pulled up by the pull-up resistor 302, and the NAND gate 301. Connected to each.

An internal bus output enable signal 312 and an internal power supply control signal 313 are output from each NAND gate 301, and the internal bus output enable signal 312 receives the output signal 315 from the substrate, a 3-state buffer 303, and data from the substrate. OR gate 3 controlling the output of signal 318
05, the internal power supply control signal 313 is connected to the relay 3
06 control coil. However, relay 30
Reference numeral 6 is a type in which the contacts are opened when the internal power supply control signal 313 is "H".

The power supply 326 from the motherboard is the relay 3
06 is connected to one contact, and the power supply 321 to the substrate is connected to the other contact.

The description of the motherboard of FIG. 1 will be given below with reference to FIG.
This is performed using FIGS. 3 and 4.

When the board connected to the motherboard main body 1 causes some error during operation and it is unavoidable to replace it, the CPU connected to the motherboard which detects this failure is The connection control line 6 is used to disconnect the board in which the error occurred from the bus 5. At this time, the output permission signal 31 in the bus connection control line 6 is disconnected.
0 is set to "L" so that the output of the board does not affect the bus 5. Then, the power supply control signal 311 is set to "L" to turn off the power supply to the substrate.

By the above operation, the board in which the error has occurred is disconnected from the bus 5, so that the operation of the other board will not be affected even if the board in which the error occurred is removed while the other board is operating.

When the board is inserted into the mother board, the power supply control signal 31 from the CPU which has inserted the board connection connector from this state and driven the bus connection control signal.
1 is set to "L", and then the output permission signal 310 is set to "L"
By doing so, the board can be inserted into the motherboard while the other board is operating.

Next, the operation of this motherboard will be described with reference to the computer device 500 of FIG. As an example, when the first CPU board 510 detects that the first I / O board 514 has failed, the first CPU board 510 outputs the bus connection control signal 507.
Of the bus connection control mechanism of the first I / O is set to high impedance by using the output permission signal 310 of the first I / O, and then the power supply control signal 311 of the bus connection control signal 507 is used to make the first The power off of the I / O board 514 is instructed.

This completely disconnects the first I / O board 514 from the motherboard bus 505, but operation of the device continues using the second I / O board 515.

After that, the first I / O board 514 is replaced by the maintenance personnel, and when the completion of the replacement is reported to the first CPU board 510 by some means, the first CPU board 510 controls the bus connection. The power supply control signal 311 of the signal 507 is used to connect the first I / O to the connector of the first I / O.
Instruct to turn on the power of the board 514, and the bus connection control signal 5
Using the output enable signal 310 of 07, the first I / O
The high impedance of the buffer of the connector 504 is released, and the connection to the bus of the mother board is performed.

[0035]

As described above, according to the present invention, the connector mounted on the mother board incorporates the buffer, the 3-state buffer and the relay, the state of the 3-state buffer and the board connected to the connector. Since the power on / off can be controlled from one of the boards mounted on the motherboard, in the case of a non-stop computer in which multiple boards are connected to each other by the motherboard, one board may fail. Even if it is necessary to replace the defective substrate, the defective substrate can be replaced without stopping the operation of the apparatus.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a motherboard of a non-stop computer according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional motherboard.

FIG. 3 is a configuration diagram of a bus connection control mechanism on the CPU side.

FIG. 4 is a configuration diagram of a bus connection control mechanism.

FIG. 5 is a configuration diagram showing an all-duplex non-stop computer using a conventional motherboard.

FIG. 6 is a configuration diagram showing an all-duplex non-stop computer using the motherboard of the non-stop computer of the present invention.

[Explanation of symbols]

 1 Motherboard of non-stop computer 2 CPU side bus connection control mechanism 3 Bus connection control mechanism 4 Connector 5 Bus 6 Bus connection control line 101 Conventional motherboard 104 Connector 105 Bus 200 CPU side bus connection control mechanism 201 NOT gate 202 Pull Up resistor 203 3-state buffer 204 Buffer 205 OR gate 206 Relay 210 Output permission signal from other system CPU 211 Power control signal from other system CPU 212 Internal bus output permission signal 213 Internal power control signal 214 Bus connection control from CPU Signal 215 Output signal from CPU 216 Input signal to CPU 217 Input control line from CPU 218 Data signal from CPU 219 Output control signal from CPU 220 GND to CPU board 221 Power to CPU Source 222 Bus connection control signal 223 Output signal to bus 224 Input signal from bus 225 Data signal to bus 226 Power supply from motherboard 300 Bus connection control mechanism 301 NAND gate 302 Pull-up resistor 303 3-state buffer 304 Buffer 305 OR Gate 306 Relay 310 Output permission signal from 1-system CPU 311 Power supply control signal from 1-system CPU 312 Internal bus output permission signal 313 Internal power supply control signal 315 Output signal from board 316 Input signal to board 317 Input control from board Line 318 Data signal from board 319 Output control signal from board 320 GND 321 Power to board 321 Power supply to board 323 Output signal to bus 324 Input signal from bus 325 Data signal to bus 326 Power supply from motherboard 330 Output permission signal from 2 system CPU 331 Power control signal from 2 system CPU 400 All-duplex non-stop computer 401 Conventional motherboard 404 Connector 405 Bus 410 First CPU board 411 Second CPU board 412 First Memory board 413 Second memory board 414 First I / O board 415 Second I / O board 500 Non-stop type computer 501 with all duplexes Motherboard of non-stop type computer 502 CPU bus-side connection control mechanism 503 Bus connection control mechanism 504 Connector 505 Bus 506 Bus connection control signal for 1-system CPU 507 Bus connection control signal for 2-system CPU 510 First CPU board 511 Second CPU board 512 First memory board 513 Second memory board 514 First I / O Substrate 51 The second of I / O board

Claims (3)

[Claims] 1. A mother board for use in a computer, in which a plurality of boards are connected to each other by a mother board, wherein a mother board has a built-in three-state buffer and a relay, and the three-state state of the buffer and its connector. A motherboard for a non-stop computer, characterized in that the power of a connected board can be turned on and off from any board mounted on the motherboard. 2. When a failure occurs in any of the boards,
The motherboard of a non-stop computer according to claim 1, wherein the failed board is disconnected from the bus by using the bus connection control signal to cut off the power supply. 3. The motherboard of a non-stop computer according to claim 1, wherein the board is connected to the bus by using a bus connection control signal at the time of restoration.