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JPH05188395A - Liquid crystal display element - Google Patents

Liquid crystal display element

Info

Publication number
JPH05188395A
JPH05188395A JP443492A JP443492A JPH05188395A JP H05188395 A JPH05188395 A JP H05188395A JP 443492 A JP443492 A JP 443492A JP 443492 A JP443492 A JP 443492A JP H05188395 A JPH05188395 A JP H05188395A
Authority
JP
Japan
Prior art keywords
liquid crystal
pixel
crystal display
thin film
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP443492A
Other languages
Japanese (ja)
Inventor
Yoshihiro Asai
義裕 浅井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP443492A priority Critical patent/JPH05188395A/en
Publication of JPH05188395A publication Critical patent/JPH05188395A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To lower the probability of disconnection and the shorting between scanning lines and signal lines and to improve a yield by disposing two kinds of different picture elements near the respective intersecting points of the scanning lines and the signal lines and applying display signals discretely to these picture elements. CONSTITUTION:The picture element regions consisting of the picture elements A27 constituted of TFTs (thin-film transistors) A22, TFTs A'23 and picture element capacitors A24 and the picture elements B28 constituted of TFTs B 25 and picture element capacitors B26 are formed at the respective intersecting points of the scanning lines 20 and the signal lines 21. The individual picture element capacitors are constituted of respective display picture element electrodes 50, 59, common electrodes and liquid crystal layers clamped by these electrodes. As a result, the common possession of one piece of the scanning line or signal line with the two picture elements is made possible and, therefore, the number of wirings, such as scanning lines and signal lines, and eventually the intersecting parts of the signal lines and the scanning lines are decreased as compared with the ordinary elements.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、薄膜トランジスタ
(Thin Film Transistor,TFT)をスイッチ素子として表
示画素電極アレイを構成した液晶表示素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having a display pixel electrode array using thin film transistors (TFTs) as switch devices.

【0002】[0002]

【従来の技術】近年、液晶を用いた表示素子は、テレビ
表示やグラフィックティスプレイなどを指向した大容量
で高密度のアクティブマトリクス型液晶表示素子の開発
及び実用化が盛んである。この様な液晶表示素子では、
クロストークのない高コントラストの表示が行えるよう
に、各画素の駆動と制御を行う手段として半導体スイッ
チが用いられる。その半導体スイッチとしては、透過型
表示が可能であり大面積化も容易であるなどの理由か
ら、絶縁基板上に形成されたTFTなどが用いられてい
る。
2. Description of the Related Art In recent years, as a display element using a liquid crystal, a large-capacity and high-density active matrix type liquid crystal display element for television display or graphic display has been actively developed and put to practical use. In such a liquid crystal display element,
Semiconductor switches are used as means for driving and controlling each pixel so that high-contrast display without crosstalk can be performed. As the semiconductor switch, a TFT or the like formed on an insulating substrate is used because it can be used for transmissive display and can be easily made large in area.

【0003】図6に、例えば特開昭56-162793 号公報に
記載されている、このような液晶表示素子の概略断面構
造を示す。絶縁基板1上にはTFT2及びTFT2に接
続された透明導電膜からなる表示画素電極3が配列形成
されている。一方、絶縁基板4上には、透明導電膜から
なる対向電極5が全面に形成されている。また絶縁基板
1と絶縁基板4との間には液晶6が挾持されており、さ
らにその周囲を封着剤7で封止した構造となる。
FIG. 6 shows a schematic sectional structure of such a liquid crystal display element described in, for example, Japanese Patent Application Laid-Open No. 56-162793. On the insulating substrate 1, a TFT 2 and a display pixel electrode 3 made of a transparent conductive film connected to the TFT 2 are arrayed. On the other hand, a counter electrode 5 made of a transparent conductive film is formed on the entire surface of the insulating substrate 4. A liquid crystal 6 is sandwiched between the insulating substrate 1 and the insulating substrate 4, and the periphery thereof is further sealed with a sealing agent 7.

【0004】上述のTFT2は、図6に示すように、マ
トリクス状に形成された走査線10と信号線11の各交
点位置に配設され、TFT2のゲートは行ごとに走査線
10に接続され、TFT2のドレインは列ごとに信号線
11に接続され、ソースは表示画素電極3に接続されて
いる。そして、この表示画素電極3と対向電極5及び液
晶6によって画素容量が形成されている。
As shown in FIG. 6, the above-mentioned TFT 2 is arranged at each intersection of scanning lines 10 and signal lines 11 formed in a matrix, and the gates of the TFTs 2 are connected to the scanning lines 10 row by row. , The drains of the TFTs 2 are connected to the signal line 11 for each column, and the sources are connected to the display pixel electrodes 3. A pixel capacitance is formed by the display pixel electrode 3, the counter electrode 5 and the liquid crystal 6.

【0005】また、図8は走査線10と信号線11の交
差部の平面図を示し、図9はその断面図を示す。図に示
すように、走査線10と信号線11とはゲート絶縁膜1
6によって絶縁されている。
FIG. 8 is a plan view of the intersection of the scanning line 10 and the signal line 11, and FIG. 9 is a sectional view thereof. As shown in the figure, the scanning line 10 and the signal line 11 are connected to the gate insulating film 1.
Insulated by 6.

【0006】次に、この液晶表示素子の駆動方法の一例
について説明する。即ち、TFT2のゲートに走査線選
択電圧が印加されている期間(選択期間)に、表示画素
電極3は信号線11と通じて映像信号電位と同電位に設
定され、また、ゲートに走査線非選択電圧が印加されて
いる期間(保持期間)は、表示画素電極3はこの映像信
号電位に保たれる。一方、対向電極5は所定の電位に設
定されており、したがって表示画素電極3と対向電極5
との間に挾持されている液晶6には、映像信号電位と対
向電極電位の差に相当する電圧がかかる。この電圧に応
じて液晶の配列状態が変化することにより光透過率が変
化し、画像表示が行われる。また、液晶を直流駆動する
と、液晶分子が電気分解されて劣化することにより寿命
が短くなるため、一般には交流駆動が用いられている。
一例を挙げると、所定の電位に設定された対向電極電位
に対して、映像信号電位を偶奇フレームで正負対称に設
定する方法が用いられている。
Next, an example of a method of driving the liquid crystal display element will be described. That is, during the period (selection period) in which the scanning line selection voltage is applied to the gate of the TFT 2, the display pixel electrode 3 is set to the same potential as the video signal potential through the signal line 11, and the gate is not scanned line. The display pixel electrode 3 is kept at this video signal potential during the period (holding period) in which the selection voltage is applied. On the other hand, the counter electrode 5 is set to a predetermined potential, and therefore the display pixel electrode 3 and the counter electrode 5 are
A voltage corresponding to the difference between the video signal potential and the counter electrode potential is applied to the liquid crystal 6 held between the two. By changing the alignment state of the liquid crystal according to this voltage, the light transmittance changes, and an image is displayed. Further, when the liquid crystal is driven by direct current, the life is shortened due to electrolysis and deterioration of liquid crystal molecules, so that alternating current drive is generally used.
As an example, a method is used in which the video signal potential is symmetrically set in the even and odd frames with respect to the counter electrode potential set to a predetermined potential.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、この種
の液晶表示素子では、以下のような問題があった。製造
工程中のゴミなどに起因して、走査線10と信号線11
との交差部においてゲート絶縁膜16にピンホールのよ
うな絶縁不良箇所が発生すると、走査線10と信号線1
1が短絡不良を起こし、表示画面には線欠陥としてあら
われてしまう。あるいは、走査線10や信号線11自体
が断線してしまうことも考えられ、これらの配線本数の
多い大画面・高精細デバイスでは歩留まり低下の大きな
要因となっている。
However, this type of liquid crystal display device has the following problems. Due to dust in the manufacturing process, the scanning line 10 and the signal line 11
When a defective insulating portion such as a pinhole occurs in the gate insulating film 16 at the intersection with the scanning line 10 and the signal line 1,
1 causes a short circuit defect, and appears as a line defect on the display screen. Alternatively, the scanning lines 10 and the signal lines 11 themselves may be broken, which is a major factor of yield reduction in a large-screen / high-definition device having many wirings.

【0008】[0008]

【課題を解決するための手段】この発明は、上述の課題
を解決するために、複数本の信号線と走査線をマトリク
ス状に交差させ、これらの交点付近に薄膜トランジスタ
及びこれに接続される表示画素電極を配した画素領域を
有する液晶表示素子において、この画素領域は周期的に
繰り返されて配置された複数の異なる画素より形成され
ると共に、これらの画素の個々には個別の表示信号が書
き込まれる液晶表示素子を用いる。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention crosses a plurality of signal lines and scanning lines in a matrix form, and a thin film transistor and a display connected to the thin film transistor near these intersections. In a liquid crystal display device having a pixel area in which pixel electrodes are arranged, this pixel area is formed by a plurality of different pixels which are periodically repeated and individual display signals are written to each of these pixels. A liquid crystal display element is used.

【0009】さらに具体的には、画素領域は複数の第1
の表示画素電極及び複数の第2の表示画素電極より形成
されるとともに、信号線と第1の表示画素電極間に接続
された第1の薄膜トランジスタと、信号線と第2の表示
画素電極間に直列に接続された第2の薄膜トランジスタ
及び第3の薄膜トランジスタとを有し、第1の薄膜トラ
ンジスタ及び第2の薄膜トランジスタのゲートは共通の
走査線に接続され、第3の薄膜トランジスタのゲートは
異なる走査線に接続されると共に、この2本の走査線が
同時に選択される期間と、共通の走査線のみが選択され
る期間とが周期的に繰り返される液晶表示素子を用い
る。
More specifically, the pixel area includes a plurality of first areas.
A first thin film transistor which is formed of the display pixel electrode and a plurality of second display pixel electrodes and is connected between the signal line and the first display pixel electrode, and between the signal line and the second display pixel electrode. A second thin film transistor and a third thin film transistor connected in series, the gates of the first thin film transistor and the second thin film transistor are connected to a common scan line, and the gate of the third thin film transistor is connected to a different scan line. A liquid crystal display element is used in which, while being connected, a period in which these two scanning lines are simultaneously selected and a period in which only a common scanning line is selected are periodically repeated.

【0010】[0010]

【作用】この発明の液晶表示素子においては、異なる2
本の走査線を選択した場合にのみ信号電圧が書き込まれ
る複数の画素と、それらのうち1本の走査線を選択した
場合に信号電圧が書き込まれる複数の画素を用いて画素
領域が形成され、1本の走査線又は信号線を2画素で共
有することが可能となるため、走査線や信号線などの配
線本数引いては信号線と走査線の交差部を従来のものよ
りも大幅に減少させることができる。
In the liquid crystal display element of the present invention, there are two different
A pixel region is formed using a plurality of pixels to which a signal voltage is written only when one scanning line is selected and a plurality of pixels to which a signal voltage is written when one scanning line is selected from the pixels. Since one scanning line or signal line can be shared by two pixels, the number of wiring lines such as scanning lines and signal lines can be reduced, and the number of intersections between signal lines and scanning lines can be greatly reduced compared to the conventional one. Can be made

【0011】[0011]

【実施例】以下、図面を参照してこの発明を詳細に説明
する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings.

【0012】図1はこの発明の一実施例を示す等価回路
図である。走査線20と信号線21の各交点には、TF
TA 22、TFTA'23及び画素容量A 24により構成
された画素A 27と、TFTB 25及び画素容量B 26
で構成された画素B 28よりなる画素領域が形成されて
いる。個々の画素容量は、それぞれの表示画素電極と共
通電極68及びこれらに挾持された液晶層70より構成
される。
FIG. 1 is an equivalent circuit diagram showing an embodiment of the present invention. At each intersection of the scanning line 20 and the signal line 21, TF
Pixel A 27 composed of TA 22, TFT A ′ 23 and pixel capacitance A 24, TFT B 25 and pixel capacitance B 26
A pixel region is formed by the pixel B 28 configured by the above. Each pixel capacitance is composed of a display pixel electrode, a common electrode 68, and a liquid crystal layer 70 held between them.

【0013】また図2は、各々の画素における平面図を
示す。即ち、画素A においては、TFTA 22のドレイ
ン電極55は信号線21に接続され、ソース電極58は
TFTA'23のドレイン電極63に接続されている。ま
た、TFTA'23のソース電極60は表示画素電極A 5
0に接続されている。TFTA 22のゲート電極56は
走査線20の第n行に接続され、TFTA'23のゲート
電極62は走査線20の第(n−1)行に接続されてい
る。
FIG. 2 shows a plan view of each pixel. That is, in the pixel A, the drain electrode 55 of the TFT A 22 is connected to the signal line 21, and the source electrode 58 is connected to the drain electrode 63 of the TFT A ′ 23. The source electrode 60 of the TFT A'23 is the display pixel electrode A 5
It is connected to 0. The gate electrode 56 of the TFTA 22 is connected to the nth row of the scanning line 20, and the gate electrode 62 of the TFTA ′ 23 is connected to the (n−1) th row of the scanning line 20.

【0014】一方、画素B 28においては、TFTB 2
5のドレイン電極54は信号線21に接続され、ソース
電極51は表示画素電極B 59に接続されている。ま
た、ゲート電極53は走査線20の第n行に接続されて
いる。
On the other hand, in the pixel B 28, the TFT B 2
The drain electrode 54 of No. 5 is connected to the signal line 21, and the source electrode 51 is connected to the display pixel electrode B 59. The gate electrode 53 is connected to the nth row of the scanning line 20.

【0015】図3は、図2の線BB´に沿った断面図を
示す。絶縁基板73上には、ゲート電極53が形成さ
れ、この上にゲート絶縁膜72を介して半導体層52が
形成されている。さらに、半導体層52はオーミック層
64を介してソース電極51及びドレイン電極54の各
々と接続されてTFTB 25が形成されている。さらに
全面に配向膜71が積層されて、アレイ基板74が形成
されている。
FIG. 3 shows a sectional view along the line BB 'of FIG. The gate electrode 53 is formed on the insulating substrate 73, and the semiconductor layer 52 is formed on the gate electrode 53 with the gate insulating film 72 interposed therebetween. Further, the semiconductor layer 52 is connected to each of the source electrode 51 and the drain electrode 54 through the ohmic layer 64 to form the TFTB 25. Further, an alignment film 71 is laminated on the entire surface to form an array substrate 74.

【0016】一方、絶縁基板67上には透明導電層から
なる共通電極68が全面に形成され、さらにこの上に配
向膜69が積層されて、対向基板66が形成されてい
る。そしてアレイ基板74と対向基板66の間には液晶
層70が挾持され、液晶表示装置が形成される。
On the other hand, a common electrode 68 made of a transparent conductive layer is formed on the entire surface of the insulating substrate 67, and an alignment film 69 is further laminated thereon to form a counter substrate 66. Then, the liquid crystal layer 70 is sandwiched between the array substrate 74 and the counter substrate 66 to form a liquid crystal display device.

【0017】次に、本実施例の液晶表示素子の駆動方法
と動作原理を説明する。図5は図1の部分図を示し、図
4は図5に示す各々の画素を駆動するための走査線電圧
と信号線電圧のタイミングチャート図を示す。
Next, the driving method and operating principle of the liquid crystal display element of this embodiment will be described. FIG. 5 shows a partial view of FIG. 1, and FIG. 4 shows a timing chart of a scanning line voltage and a signal line voltage for driving each pixel shown in FIG.

【0018】走査線20には、1フレーム期間(Tf)
に2回走査線選択電圧(以下、Vg,onと称する)が印加
される。一方、信号線21には、中心電圧(Vsig,c )
に対してフレームごとに反転する信号線電圧が印加され
る。また次表1は、この様な駆動方法を用いた場合の各
画素の動作を示す。
The scanning line 20 has one frame period (Tf).
The scanning line selection voltage (hereinafter, referred to as Vg, on) is applied twice. On the other hand, the signal line 21 has a central voltage (Vsig, c)
On the other hand, a signal line voltage that is inverted every frame is applied. Table 1 below shows the operation of each pixel when such a driving method is used.

【0019】[0019]

【表1】 注)破線は、他の画素に与えるべき信号電圧が印加され
ている期間を示す。
[Table 1] Note) The broken line indicates the period during which the signal voltage to be applied to other pixels is applied.

【0020】時刻t1 〜t2 において、走査線20の第
(n−1)行及び第n行にVg,onが印加され、TFTA
(n,m)35とTFTA'(n,m) 37が同時に導通すること
によって画素容量A(n,m)36に信号線電圧V1 が書き込
まれる。また、TFTB(n-1,m)41及びTFTB(n,m)4
3が導通することによって、画素容量B(n-1,m)42と画
素容量B(n,m)44のそれぞれにも同様に信号線電圧V1
が書き込まれる。
From time t 1 to t 2 , Vg, on is applied to the (n-1) th row and the nth row of the scanning line 20, and TFTA
The signal line voltage V1 is written in the pixel capacitance A (n, m) 36 by the simultaneous conduction of the (n, m) 35 and the TFT A '(n, m) 37. In addition, TFTB (n-1, m) 41 and TFTB (n, m) 4
3 becomes conductive, the signal line voltage V1 is similarly applied to each of the pixel capacitance B (n-1, m) 42 and the pixel capacitance B (n, m) 44.
Is written.

【0021】時刻t2 〜t3 になると、走査線20の第
(n−1)行にのみVg,onが印加され、TFTB(n-1,m)
41が導通することによって、画素容量B(n-1,m)42に
書き込まれていた電圧V1 は信号線電圧V3 に書き換え
られる。一方、TFTA(n,m)35及びTFTB(n,m)43
は非導通となり、画素容量A(n,m)36及び画素容量B(n,
m)44はV1 に保持されることにより、画素A(n,m)45
の透過率が決定される。
From time t2 to t3, Vg, on is applied only to the (n-1) th row of the scanning line 20, and TFTB (n-1, m)
The voltage V 1 written in the pixel capacitance B (n-1, m) 42 is rewritten to the signal line voltage V 3 by the conduction of 41. On the other hand, TFTA (n, m) 35 and TFTB (n, m) 43
Becomes non-conductive, and the pixel capacitance A (n, m) 36 and the pixel capacitance B (n, m
m) 44 is held at V 1 so that pixel A (n, m) 45
Is determined.

【0022】時刻t3 〜t4 になると、走査線20の第
n行及び第(n+1)行にVg,onが印加され、TFTA
(n+1,m)38とTFTA'(n+1,m) 40が同時に導通する
ことによって、画素容量A(n+1,m)39に信号線電圧V2
が書き込まれる。また、TFTB(n,m)43が導通するこ
とによって、画素容量B(n,m)44に保持されていたV1
は信号線電圧V2 に書き換えられる。一方、TFTB(n-
1,m)41は非導通となって、画素容量B(n-1,m)42の電
圧はV3 に保持されることにより、画素B(n-1,m)の透過
率が決定される。
At times t3 to t4, Vg, on is applied to the nth row and the (n + 1) th row of the scanning line 20, and TFTA
Since the (n + 1, m) 38 and the TFT A ′ (n + 1, m) 40 are simultaneously conducted, the signal line voltage V 2 is applied to the pixel capacitance A (n + 1, m) 39.
Is written. Further, since the TFT B (n, m) 43 becomes conductive, V 1 held in the pixel capacitance B (n, m) 44
Is rewritten to the signal line voltage V 2 . On the other hand, TFTB (n-
(1, m) 41 is rendered non-conductive, and the voltage of the pixel capacitor B (n-1, m) 42 is held at V 3 to determine the transmittance of the pixel B (n-1, m). It

【0023】時刻t4 〜t5 になると、走査線20の第
n行にのみVg,onが印加され、TFTB(n,m)43が導通
して画素容量B(n,m)44に保持されていたV2 はV4
書き換えられる。一方、TFTA(n+1,m) 38は非導通
となって、画素容量A(n+1,m)39はの電圧はV3 に保持
されることにより、画素A(n+1,m)46の透過率が決定さ
れる。
From time t 4 to t 5 , Vg, on is applied only to the nth row of the scanning line 20, and the TFT B (n, m) 43 becomes conductive and is held in the pixel capacitance B (n, m) 44. The V 2 that has been written is rewritten to V 4 . On the other hand, the TFT A (n + 1, m) 38 becomes non-conductive, and the voltage of the pixel capacitor A (n + 1, m) 39 is held at V 3 , so that the pixel A (n + 1, m) ) 46 transmission is determined.

【0024】時刻t5 で走査線20の第n行が非選択電
圧(Vg,off )になると、TFTB(n,m)43は非導通と
なり、画素容量B(n,m)44はV4 に保持されるため、画
素B(n,m)48の透過率が決定される。
When the nth row of the scanning line 20 becomes the non-selection voltage (Vg, off) at the time t 5 , the TFT B (n, m) 43 becomes non-conductive and the pixel capacitance B (n, m) 44 becomes V 4. Since the pixel B (n, m) 48 is held at, the transmittance of the pixel B (n, m) 48 is determined.

【0025】こうして、図5の各画素の透過率が決定さ
れる。このとき、例えば画素容量B(n,m)44について
は、透過率を決定する電圧V4 が書き込まれる直前に他
の画素の透過率を決定するための電圧V1 とV2 が書き
込まれるが、その期間は非常に短いため、本来の表示に
は悪影響を与えない。これは、他の画素についても同様
である。
Thus, the transmittance of each pixel in FIG. 5 is determined. At this time, for example, in the pixel capacitance B (n, m) 44, the voltages V 1 and V 2 for determining the transmittance of other pixels are written immediately before the voltage V 4 for determining the transmittance is written. , The period is so short that it does not adversely affect the original display. This also applies to other pixels.

【0026】本実施例のアクティブマトリクス型液晶表
示素子においては、異なる2本の走査線を選択した場合
にのみ信号電圧が書き込まれる複数の画素と、それらの
うち1本の走査線を選択した場合に信号電圧が書き込ま
れる複数の画素を用いて画素領域が形成され、1本の信
号線を2画素で共有することが可能となるため、従来の
液晶表示装置の工程を大幅に変更することなく信号線本
数を従来の1/2に低減させることができる。
In the active matrix type liquid crystal display device of this embodiment, a plurality of pixels to which a signal voltage is written only when two different scanning lines are selected and one scanning line among them are selected. Since a pixel region is formed by using a plurality of pixels to which a signal voltage is written in, a single signal line can be shared by two pixels, without significantly changing the process of a conventional liquid crystal display device. The number of signal lines can be reduced to half that of the conventional one.

【0027】[0027]

【発明の効果】本発明の液晶表示装置においては、異な
る2本の走査線を選択した場合にのみ信号電圧が書き込
まれる複数の画素と、それらのうち1本の走査線を選択
した場合に信号電圧が書き込まれる複数の画素を用いて
画素領域が形成され、1本の走査線又は信号線を2画素
で共有することが可能となるため、配線本数を従来のも
のよりも大幅に低減させることができ、ひいては走査線
と信号線との交差部も大幅に低減させることができる。
したがって、配線本数の多い大画面・高精細デバイスで
問題となる信号線断線や信号線・走査線間ショートの確
率を低減させて、歩留まりを大幅に向上させることがで
きる。
According to the liquid crystal display device of the present invention, a plurality of pixels to which a signal voltage is written only when two different scanning lines are selected, and a signal when one scanning line among them are selected. Since a pixel region is formed by using a plurality of pixels to which voltage is written, one scan line or signal line can be shared by two pixels, so that the number of wirings can be significantly reduced as compared with a conventional one. Therefore, the intersection of the scanning line and the signal line can be greatly reduced.
Therefore, the probability of signal line disconnection or short between signal lines and scanning lines, which is a problem in a large-screen / high-definition device having a large number of wirings, can be reduced, and the yield can be significantly improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の液晶表示素子の一実施例を示す等価回
路図である。
FIG. 1 is an equivalent circuit diagram showing an embodiment of a liquid crystal display element of the present invention.

【図2】図1の液晶表示素子の二画素を示す平面図であ
る。
FIG. 2 is a plan view showing two pixels of the liquid crystal display element of FIG.

【図3】図2の線BB´に沿った断面図である。3 is a cross-sectional view taken along the line BB ′ of FIG.

【図4】本発明の液晶表示素子の駆動波形を示すタイミ
ングチャート図である。
FIG. 4 is a timing chart showing driving waveforms of the liquid crystal display element of the present invention.

【図5】図1の液晶表示素子の一部分を示す等価回路図
である。
5 is an equivalent circuit diagram showing a part of the liquid crystal display element of FIG.

【図6】従来の液晶表示素子を示す断面図である。FIG. 6 is a cross-sectional view showing a conventional liquid crystal display element.

【図7】図6の液晶表示素子の一画素の等価回路図であ
る。
7 is an equivalent circuit diagram of one pixel of the liquid crystal display element of FIG.

【図8】図6の液晶表示素子の信号線と走査線の交差部
を示す平面図である。
8 is a plan view showing an intersection of a signal line and a scanning line of the liquid crystal display element of FIG.

【図9】図8の線AA´に沿った断面図である。9 is a cross-sectional view taken along the line AA ′ of FIG.

【符号の説明】[Explanation of symbols]

20…走査線 21…信号線 22…TFTA 23…TFTA' 24…画素容量A 25…TFTB 26…画素容量B 27…画素A 28…画素B 50…表示画素電極A 59…表示画素電極B 20 ... Scanning line 21 ... Signal line 22 ... TFTA 23 ... TFTA '24 ... Pixel capacitance A 25 ... TFTB 26 ... Pixel capacitance B 27 ... Pixel A 28 ... Pixel B 50 ... Display pixel electrode A 59 ... Display pixel electrode B

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 複数本の信号線と走査線をマトリクス状
に交差させ、これらの交点付近に薄膜トランジスタ及び
これに接続される表示画素電極を配した画素領域を有す
る液晶表示装置において、前記画素領域は周期的に繰り
返されて配置された複数の異なる画素より形成されると
共に、前記画素の個々には個別の表示信号が書き込まれ
ることを特徴とする液晶表示素子。
1. A liquid crystal display device having a pixel area in which a plurality of signal lines and scanning lines are crossed in a matrix and a thin film transistor and a display pixel electrode connected to the thin film transistor are arranged in the vicinity of these crossing points. Is formed by a plurality of different pixels which are periodically repeated and arranged, and an individual display signal is written in each of the pixels.
【請求項2】 前記画素領域は複数の第1の表示画素電
極及び複数の第2の表示画素電極より形成されるととも
に、前記信号線と前記第1の表示画素電極間に接続され
た第1の薄膜トランジスタと、前記信号線と前記第2の
表示画素電極間に直列に接続された第2の薄膜トランジ
スタ及び第3の薄膜トランジスタとを有することを特徴
とする請求項1記載の液晶表示素子。
2. The pixel region is formed of a plurality of first display pixel electrodes and a plurality of second display pixel electrodes, and is connected between the signal line and the first display pixel electrode. 2. The liquid crystal display device according to claim 1, further comprising: the thin film transistor, and a second thin film transistor and a third thin film transistor connected in series between the signal line and the second display pixel electrode.
【請求項3】 前記第1の薄膜トランジスタ及び第2の
薄膜トランジスタのゲートは共通の走査線に接続され、
前記第3の薄膜トランジスタのゲートは前記共通の走査
線とは異なる走査線に接続されたことを特徴とする請求
項2記載の液晶表示素子。
3. The gates of the first thin film transistor and the second thin film transistor are connected to a common scan line,
The liquid crystal display element according to claim 2, wherein a gate of the third thin film transistor is connected to a scanning line different from the common scanning line.
【請求項4】 前記2本の走査線が選択される期間と前
記共通の走査線のみが選択される期間とが周期的に繰り
返されることを特徴とする請求項3記載の液晶表示素
子。
4. The liquid crystal display element according to claim 3, wherein a period in which the two scanning lines are selected and a period in which only the common scanning line is selected are periodically repeated.
JP443492A 1992-01-14 1992-01-14 Liquid crystal display element Pending JPH05188395A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP443492A JPH05188395A (en) 1992-01-14 1992-01-14 Liquid crystal display element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP443492A JPH05188395A (en) 1992-01-14 1992-01-14 Liquid crystal display element

Publications (1)

Publication Number Publication Date
JPH05188395A true JPH05188395A (en) 1993-07-30

Family

ID=11584137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP443492A Pending JPH05188395A (en) 1992-01-14 1992-01-14 Liquid crystal display element

Country Status (1)

Country Link
JP (1) JPH05188395A (en)

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