JPH05188118A - Semiconductor integrated circuit and method for changing its function - Google Patents

Abstract

PURPOSE:To completely damage a semiconductor integrated circuit which has been judged to be defective by a device test to easily distinguish it from a good semiconductor integrated circuit. CONSTITUTION:In a semiconductor integrated circuit 1 being activated/ inactivated based on a signal such as a chip selection signal supplied from a specific signal input terminal IPAD, on a signal transmission path supplied from the specific signal input terminal IPAD, a first program circuit 2 for forcing a signal logic value of the path to be an inactivated logic value of the semiconductor integrated circuit 1 selectively depending on whether or not a fuse FUSE1 is to be fused. The semiconductor integrated circuit 1 having an unrepairable defect is completely damaged by the first program circuit 2, whereby the semiconductor integrated circuit 1 can be easily distinguished from a good semiconductor integrated circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for identifying a defect in a semiconductor integrated circuit, and more particularly to a technique effectively applied to a semiconductor integrated circuit having a fuse processing step.

[0002]

2. Description of the Related Art In a device test, a defective semiconductor integrated circuit that cannot be repaired even by redundancy is identified as a good product, and only a good product is packaged in a post process such as assembly. For example, in a device test at the wafer stage, an address is given to each device on the wafer, and the test result of defective / non-defective product is associated with the device by the address information. As an example of a document describing the device test, there are "LSI Handbook", pages 649 to 653, published by Ohmsha, Ltd. on November 30, 1984.

[0003]

However, it may be difficult to distinguish a defective device from a non-defective device by the conventional technique. That is, when associating a defective / non-defective test result with a device by the address information on the wafer, the address has no meaning once dicing is performed, and when a defective device is mixed with a non-defective device, both of them are combined. It is not possible to make a distinction, and it is often necessary to repeat the device test again with the same test item in another step. Moreover, in addition to a defect that does not operate at all as a defect mode, there is also a margin property defect in which an operation margin is below an expected value, and strictness is required for each device test for each process, which is extremely inefficient. ..
In addition, when performing the cause analysis of a defective device, a similar device test had to be performed separately.

An object of the present invention is to provide a semiconductor integrated circuit which is once judged to be defective in a device test and can be easily distinguished from other semiconductor integrated circuits, and a function changing method for making it defective. Especially. further,
It is an object of the present invention to provide a semiconductor integrated circuit and a function changing method therefor, which enables failure cause analysis even if it is once completely made defective.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, in a semiconductor integrated circuit which can be activated / deactivated based on a signal having a meaning as a chip selection signal supplied from a specific signal input terminal, the semiconductor integrated circuit is supplied from the specific signal input terminal. The signal transmission path is provided with a first program circuit for selectively forcing the signal logic value of the path to the deactivation logic value of the semiconductor integrated circuit, and this is used as a means for complete failure of the semiconductor integrated circuit. adopt.

When the semiconductor integrated circuit has an irreparable defect, the state of the first program circuit is changed to change the logic of the signal transmission path regardless of the logic value of the signal supplied from the specific input terminal. The value is forced to a deactivation logic value, and the semiconductor integrated circuit is completely defective.

When the semiconductor integrated circuit is made completely defective by the first program circuit, in order to enable analysis of the cause of the defect, an output logical value is set in the signal transmission path to one or more specific output terminals. A second program circuit for selectively forcing a constant value is provided.

When the semiconductor integrated circuit having the first and second program circuits has an irreparable defect, the state of the first program circuit is changed and the logical value of the signal supplied from the specific input terminal is changed. Regardless of the reason, the logic value of the signal transmission path is forced to a deactivation logic value to completely make the semiconductor integrated circuit defective, and the state of the second program circuit is changed to output the signal code from the output terminal. The function of the semiconductor integrated circuit is changed by the process of making a defective code according to the cause of the defect.

[0011]

According to the above-mentioned means, the semiconductor integrated circuit having the irreparable defect is completely inoperable by the first program circuit, which means that the semiconductor integrated circuit is defective. And can be easily distinguished from each other, eliminating the need to perform duplicate device tests in each process.

Further, the failure cause code which can be output by the second program circuit enables failure cause analysis of a semiconductor integrated circuit which is completely defective and cannot operate.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a typical chip select signal input system as an embodiment of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 1 shown in the figure is, for example, a semiconductor memory or other peripheral device, and is formed on one semiconductor substrate such as single crystal silicon.

In the figure, IPAD is an input pad for a chip select signal, and the semiconductor integrated circuit 1 is activated / inactivated, for example, in a chip selected / non-selected state according to the level of the chip select signal supplied from the pad PAD. Controlled by. In the chip selection state, the operation is performed so that an output according to the signal supplied from the external terminal can be obtained. In the chip non-selected state, an output corresponding to the signal supplied from the external terminal cannot be obtained, and the semiconductor integrated circuit is substantially disabled.

In the signal transmission path of the chip select signal supplied from the input pad IPAD, a first program circuit 2 for selectively forcing a signal logic value of the path to a chip non-selection logic value is arranged. The output is supplied to a timing control circuit (not shown). The timing control circuit determines the logical value of the chip select signal and controls chip selection / non-selection.

The first program circuit 2 is not particularly limited, and the logical value of the output signal is determined by whether or not the fuse FUSE1 is blown by the laser. That is, the fuse F is provided between the source of the P-channel type MOSFET Q1 and the source of the N-channel type MOSFET Q3 which form a CMOS (complementary MOS) inverter.
A USE1 is provided, and a latch circuit composed of a P-channel MOSFET Q2 and a CMOS inverter I2 is arranged at the source of the MOSFET Q1.
A CMOS inverter I3 for waveform shaping or amplification is provided at the output stage of the latch circuit, and a CMOS inverter I1 for waveform shaping or logic matching is provided between the input pad IPAD and the gate electrodes of the MOSFETs Q1 and Q3. Is provided.

In the initial state of the semiconductor integrated circuit 1, for example, before a device test such as a wafer probe test, the fuse FUSE1 is in a non-blown state. When the fuse FUSE1 is not blown, the first program circuit 2 outputs from the CMOS inverter I3 a signal having a level corresponding to the signal level supplied to the input pad IPAD. According to this embodiment, the chip select signal supplied from the input pad IPAD indicates the chip selection by its low level. Therefore, when the chip selection is instructed, the output of the CMOS inverter I3 is set to the low level, and the CMOS inverter I3 is set in the chip non-selection period.
Output is set to high level. On the other hand, fuse FUSE
When 1 is blown, the input node of the CMOS inverter I2 is forced to the high level, and as a result, the output level of the CMOS inverter I3 is fixed to the high level and the semiconductor integrated circuit 1 is fixed to the chip non-selected state.

A device test is performed in the initial state of the semiconductor integrated circuit 1, and if there is no irreparable defect as a result, the fuse FUSE1 is left in the connected state. On the other hand, when it is determined that there is a defect that cannot be repaired even by redundancy, the fuse FUSE is set by the laser.
1 is blown. If there is a circuit for selecting fuse blowing other than the first program circuit 2, the fuse FUSE1 is blown in the same step.

When the fuse FUSE1 is blown, the semiconductor integrated circuit 1 is always in the chip non-selected state regardless of the signal level supplied to the input pad IPAD, and the output according to the input signal cannot be obtained. It is completely damaged by. Therefore, even if the cause of the defect is the defective margin, it does not operate at all. As a result, even if the semiconductor integrated circuit is instructed to select a chip, the semiconductor integrated circuit 1 does not operate as expected, and thus the completely defective semiconductor integrated circuit 1 and other semiconductor integrated circuits can be easily distinguished. As a result, it becomes unnecessary to repeatedly perform strict device tests with the same or similar test items in each process.

Next, a description will be given of an embodiment in which a defect cause analysis can be performed on the semiconductor integrated circuit 1 which has been completely defective by the configuration of FIG. FIG. 2 shows a second program circuit 3 coupled to the output pad OPAD in the semiconductor integrated circuit 1.
An example is shown. The output pad OPAD is an appropriate output terminal for address signals, data or control signals, for example, and is a pair of N-channel MOSFETs Q10 and Q11 connected in series between the power supply terminals Vdd and Vss.
Is coupled to an output circuit configured by. This output circuit is a complementary push-pull circuit, and M
When the signals supplied to the gate electrodes of the OSFETs Q10 and Q11 are both low level, the output impedance is high, and when the signal levels supplied to the gates of the MOSFETs Q10 and Q11 are complementary levels, a high level or a low level is output. ..

The second program circuit 3 has a signal transmission path to the output pad OPAD, for example, the MOSFETQ.
It is arranged in the gate input path of 10, Q11, and the same pad O
The output logical value of the PAD is selectively forced to a constant value, and the fuses FUSE2 to FUSE are not particularly limited.
Depending on whether or not USE5 is cut by laser, pad O
The logical value of the signal output from the PAD is fixedly determined. That is, on the gate side of the MOSFET Q10, the source of the P-channel MOSFET Q4 and the N of the P-channel MOSFET Q4 forming a CMOS (complementary MOS) inverter are connected.
Fuses FUSE2 and FUSE3 are inserted in series between the sources of the channel type MOSFET Q6, and a latch circuit constituted by an N channel type MOSFET Q5 and a CMOS inverter I4 and a P channel type MOS are provided at a coupling node of the fuses FUSE2 and FUSE3.
A FET Q7 and a latch circuit composed of a CMOS inverter I4 are arranged. In addition, MOSFETQ1
On the gate side of 1, fuses FUSE4 and FUSE5 are inserted in series between the sources of a P-channel MOSFET Q8 and an N-channel MOSFET Q9 that form a CMOS (complementary MOS) inverter, and the fuses FUSE4 and FUSE5 are connected in series. The coupling node includes a latch circuit composed of an N-channel MOSFET Q10 and a CMOS inverter I5, a P-channel MOSFET Q11 and a CMOS inverter I5.
And a latch circuit configured by.

In the initial state of the semiconductor integrated circuit 1, for example, before a device test such as a wafer probe test, the fuses FUSE2 to FUSE5 are all in a non-blown state. When the fuses FUSE2 to FUSE5 are not blown, the second program circuit 3 is
A signal having a level corresponding to the gate input logic level of TQ4, Q6 and MOSFETs Q8, Q9 is supplied to MOSFET Q1.
Enables output to the gates of 0 and Q11. Therefore, in this state, the output pad OPAD has the semiconductor integrated circuit 1
The output operation is enabled according to the operation of the internal circuit of. On the other hand, by cutting the fuses FUSE2 to FUSE5 in a predetermined combination, the output pad OPAD is always forced to a predetermined level. That is, the output pad OPAD is fixed at a high level by cutting the fuses FUSE2 and FUSE5, and the fuses FUSE3 and FUSE are fixed.
The output pad OPAD is fixed at a low level by disconnecting 4.

If a device test is performed in the initial state of the semiconductor integrated circuit 1 and there is no irreparable defect as a result, the fuses FUSE2 to FUSE5 are left in the connected state. On the other hand, when it is determined that there is a defect that cannot be repaired even by redundancy, the semiconductor integrated circuit is completely made defective by the first program circuit 2, and further, code information corresponding to the cause of the defect is provided by the second program circuit 3. Is set to. For example, the circuit shown in FIG. 2 has four output terminals OUT1 to OUT1 as shown in FIG.
In the case of being provided corresponding to 4, the corresponding failure cause code is programmed from among 16 different failure causes in accordance with the programming states of the four second program circuits 3. Therefore, the failure analysis of the semiconductor integrated circuit, which has been made completely defective by the first program circuit 2, can be simplified. Further, since the defect cause code programmed by the second program circuit 3 is information itself indicating a defect of the semiconductor integrated circuit 1, it can be naturally used for distinguishing it from a good semiconductor integrated circuit.

FIG. 4 shows another embodiment for making a semiconductor integrated circuit completely defective. That is, in this example, the functions of all the output terminals of the defective semiconductor integrated circuit are stopped. FIG. 4 shows an example of the program circuit 4 coupled to the output pad OPAD in the semiconductor integrated circuit 5. The output pad OPAD is an appropriate output terminal for, for example, an address signal, data, or a control signal, and is an output circuit formed by a pair of N-channel MOSFETs Q20, Q21 connected in series between the power supply terminals Vdd and Vss. Be combined. This output circuit is a complementary push-pull circuit, and MOSFETQ2
When the signals supplied to the gate electrodes of 0 and Q21 are both low level, the output impedance is high and the MOSFET
It outputs a high level or a low level when the signal levels supplied to the gates of Q20 and Q21 are complementary levels.

The program circuit 4 has an output pad OP.
Signal transmission path to AD, for example, the MOSFET Q2
The fuses FUSE6 and FUSE7 are placed in the gate input paths of 0 and Q21 and are not particularly limited, but the fuses FUSE6 and FUSE7 are blown by a laser to force the pad OPAD to a high impedance state at all times. That is, on the gate side of the MOSFET Q20, the fuse FUSE6 is provided between the source of the P-channel type MOSFET Q24 and the source of the N-channel type MOSFET Q26 which form the CMOS (complementary MOS) inverter, and the MOSFET Q2 thereof is provided.
N-channel MOSFET Q25 is used for the source electrode of No. 4
And a latch circuit constituted by the CMOS inverter I6 is arranged. Further, on the gate side of the MOSFET Q21, the source of the P-channel MOSFET Q27 and the N-channel MOSFET Q27 forming a CMOS (complementary MOS) inverter are connected.
A fuse FUSE7 is provided between the source of the channel type MOSFET Q29 and the source electrode of the MOSFET Q27, which has N channel type MOSFETs Q28 and C.
A latch circuit formed by MOS inverter I7 is arranged.

In the initial state of the semiconductor integrated circuit 5, for example, before a device test such as a wafer probe test, the fuses FUSE6 and FUSE7 are both in a non-blown state. In the non-blown state of the fuses FUSE6 and FUSE7, the program circuit 4 sets the MOSFET Q2
4, Q26 and MOSFETs Q27 and Q29 have a signal level corresponding to the gate input logic level of MOSFET Q2.
Enable output to the 0 and Q21 gates. Therefore, in this state, the output pad OPAD has the semiconductor integrated circuit 5
The output operation is enabled according to the operation of the internal circuit of. On the other hand, when both fuses FUSE6 and FUSE7 are cut off, both MOSFETs Q20 and Q21 are cut off, and the output pad OPAD is set to the high output impedance state. Therefore, the same processing is applied to all the output terminals, so that the semiconductor integrated circuit 5 becomes completely defective. This state is discriminated by the fact that the output terminal maintains a high impedance regardless of the test pattern.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes. For example, although the chip select signal is focused on in order to completely make the semiconductor integrated circuit defective in the above-described embodiment, the present invention is not limited to this. For example, it is activated / deactivated by a control signal such as a halt mode or a standby mode. In a semiconductor integrated circuit whose activation can be controlled, a first program circuit may be provided at an input terminal for such a signal to realize complete failure of the semiconductor integrated circuit. Further, the first program circuit and the second program circuit are not limited to the configuration in which the program link such as the fuse is added to the inverter, and may be configured by adding the program link to other logic gates.

In the above description, the case where the invention made by the present inventor is mainly applied to the semiconductor integrated circuit having the fuse blowing step which is the background field of application has been described, but the present invention is not limited thereto. Instead, in a semiconductor integrated circuit that does not have a fuse blowing step, various program circuits can be configured using electric fuses or nonvolatile memory elements.

[0029]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a semiconductor integrated circuit having an irreparable defect can be made completely defective by the first program circuit, which makes it possible to easily distinguish the semiconductor integrated circuit from a non-defective semiconductor integrated circuit. There is an effect that it is not necessary to perform duplicate device tests in which the test items are the same or similar in each process.

Further, the failure cause code which can be output by the second program circuit can enable the failure cause analysis of the semiconductor integrated circuit which has been made completely defective and inoperable, and can be performed by the first program circuit. There is an effect that it can also be used as information for distinguishing between a completely defective semiconductor integrated circuit and other semiconductor integrated circuits.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a first program circuit in a semiconductor integrated circuit according to the present invention.

FIG. 2 is a circuit diagram of an embodiment of a second program circuit in the semiconductor integrated circuit according to the present invention.

FIG. 3 is an explanatory diagram of an example of an output terminal group to which a second program circuit is applied.

FIG. 4 is an explanatory view of another embodiment for making a semiconductor integrated circuit completely defective.

[Explanation of symbols]

 1 Semiconductor Integrated Circuit 2 First Program Circuit IPAD Input Pad FUSE Fuse 3 Second Program Circuit OPAD Output Pad FUSE2 to FUSE5 Fuse OUT1 to OUT4 Output Terminal

Claims (5)

[Claims] 1. A semiconductor integrated circuit which can be activated / deactivated based on a signal supplied from a specific signal input terminal, in a signal transmission path supplied from the specific signal input terminal,
A semiconductor integrated circuit comprising a first program circuit for selectively forcing a signal logic value of the path to a deactivation logic value. 2. A second program circuit for selectively forcing an output logical value to a constant value is provided in a signal transmission path to one or more specific output terminals. The semiconductor integrated circuit according to claim 1. 3. The semiconductor integrated circuit according to claim 1, wherein the logical value of the output signal is determined by whether or not the fuse is blown in the first or second program circuit. 4. The method for changing the function of the semiconductor integrated circuit according to claim 1, wherein when the semiconductor integrated circuit has an irreparable defect, the state of the first program circuit is changed and the identification is performed. A function of a semiconductor integrated circuit characterized by forcing the logic value of the signal transmission path to a deactivation logic value regardless of the logic value of the signal supplied from the input terminal to completely make the semiconductor integrated circuit defective. Modification method. 5. The method for changing the function of the semiconductor integrated circuit according to claim 2, wherein when the semiconductor integrated circuit has an irreparable defect, the state of the first program circuit is changed and the identification is performed. Regardless of the logic value of the signal supplied from the input terminal, the logic value of the signal transmission path is forced to a deactivation logic value to completely make the semiconductor integrated circuit defective and change the state of the second program circuit. The method for changing the function of a conductor integrated circuit according to claim 2, wherein the signal code output from the output terminal is converted into a defective code depending on the cause of the defect.