JPH05174587A - Electrically erasable nonvolatile memory - Google Patents

Abstract

PURPOSE:To remarkably increase the number of rewriting times and a life by applying an intermediate voltage of threshold voltages of writing and erasing states of a sample cell to a gate of a memory cell. CONSTITUTION:Two sample cells 10 are provided. The one is set to a writing state, and the other is set to an erasing state. Their threshold voltages Vwrite, Verase are obtained, their mean voltage Vout is obtained, and the voltage Vout is applied to a gate 32a of a memory 32. A threshold voltage is varied in the memory cell 32 as a time is elapsed. Since the change of the threshold voltage with time is considered by the above-described method, the number of rewriting times can be remarkably increased from 10<6> or less to 10<7> or more as compared with the case for applying a predetermined voltage such as 0V, etc., like the prior art.

Description

Detailed Description of the Invention

[0001]

The present invention relates to, for example, MNOS, MO.
The present invention relates to an electrically erasable non-volatile memory called NOS or the like.

[0002]

2. Description of the Related Art Conventionally, electrically erasable nonvolatile memory cells (E ² PROM, flash EPROM, etc.) using a technique called MNOS, MONOS, etc. have been widely used. In this memory cell, electrons are injected into an electrically insulated thin film or gate electrode (this is called "writing"), or electrons are extracted from the thin film or gate electrode (this is called "erase"). As a result, the threshold voltage of the gate at which the storage element shifts from the off state to the on state rises and falls, and information is recorded by raising and lowering this threshold voltage.

FIG. 4 is a graph showing an example of dependence of threshold voltages of MNOS and MONOS on write time and erase time. As shown in this graph, for example, 1
When writing and erasing for msec, the threshold voltage becomes about + 2V and -2V. On the other hand, when reading information from this memory element, a threshold voltage in a state where electrons are injected (writing state; here, this state is set to '0') and a state where electrons are extracted (erasing state; here, this state) It is discriminated whether it is "0" or "1" by observing the difference (memory window) in the threshold voltage of "1". That is, for example, when an intermediate potential (for example, OV) between the threshold voltages in the above two states is applied to the gate, the threshold voltage becomes + in the state of “0”.
Since it is as high as 2V, the potential OV of the gate is less than the threshold voltage + 2V, so that it is in an off state. In the state of '1', the threshold voltage is as low as -2V. Become. Thus, in the case of voltage detection, by sensing the potential of the read line, or in the case of current detection, the current flowing in the read line is detected, and the contents stored in the storage element are "0" or "1". Is detected.

[0004]

The threshold voltage of the memory cell changes with the lapse of time, and the manner of changing the threshold voltage also differs depending on the number of times of writing and erasing the memory cell. Figure 5 shows MN
A memory cell called an OS has a specified number of times (1 time, 10 ⁵
10 is a graph showing an example of charge retention characteristics after repeating writing and erasing (up to 10 ⁷ times).

As can be seen from this graph, the threshold voltage decreases with the passage of time in the written state, and the threshold voltage rises with the passage of time in the erased state, and the difference between the threshold voltages in these two states decreases. Further, the change state of the threshold voltage varies depending on how many times writing and erasing are performed. Also,
This graph shows the non-discriminating range when the gate potential is OV. If the threshold voltage in the written state or erased state falls within this non-discrimination range, it becomes "0",
The identification of "1" becomes impossible, and therefore the time until it enters the indiscriminate range is the life of this memory. This non-discriminating range changes variously mainly depending on the circuit configuration of the reading system. For example, in the example shown in FIG. 5, when the rewriting is performed 10 ⁷ times, the erased state is about 10 ⁶ seconds (about 11 days) or less. The threshold voltage is in the non-discriminating range and thus this is the life of this memory. Such a change in the threshold voltage is not limited to MNOS, and the same applies to MONOS and the like. In the case of MONOS, as an example,
The life after rewriting ⁷ times is about 10 years.

Here, in the case of an erasable non-volatile memory such as MNOS or MONOS, one of the important characteristics is how much the number of rewritable times can be increased and how long the life can be extended. In view of the above circumstances, it is an object of the present invention to improve the number of rewritable times and the life of a memory cell by devising a read circuit.

[0007]

In the electrically erasable nonvolatile memory of the present invention, a large number of memory cells are written and erased a number of times representative of the number of times of writing and erasing in each of the plurality of memory cells. Based on the threshold voltages of the sample cell and the sample cell in the written state and the threshold voltage of the sample cell in the erased state, an intermediate voltage between these threshold voltages is output and the intermediate voltage is read when the memory cell is read. It is characterized by including a gate voltage control circuit applied to the gate of the cell.

Here, only one sample cell is provided, and at least one of the threshold voltages at the time of writing and erasing to this sample cell is memorized and an intermediate voltage of those threshold voltages is outputted. Alternatively, a plurality of sample cells may be provided and one may be used for the write state and the other for the erase state. In the electrically erasable nonvolatile memory of the present invention,
The gate voltage control circuit determines the difference between the threshold voltage when the memory cell is in the write state and the voltage at the write state side of the voltage range in which it is impossible to distinguish whether the memory cell is in the write state or the erase state. It is preferable that the intermediate voltage is output so that the difference between the voltage at the erased state side of the voltage range and the threshold voltage when the memory cell is in the erased state is substantially equal to each other.

[0009]

The electrically erasable nonvolatile memory of the present invention is
Write to the memory cell, write as many times as erase,
Since a sample cell to be erased is provided and an intermediate voltage between the threshold voltage of the sample cell in the written state and the threshold voltage of the sample cell in the erased state is applied to the gate of the memory cell to perform the reading, for example, FIG.
In the case of rewriting 10 ⁷ times as shown in, the life can be remarkably extended from the conventional 10 ⁶ seconds or less to 10 ⁷ seconds or more.

Further, in obtaining the intermediate voltage, the intermediate voltage is set so that the write state side and the erase state side have substantially equal margins in consideration of the voltage at the boundary of the non-discriminating range determined by the read circuit. If the desired voltage is obtained, the life can be further extended.

[0011]

EXAMPLES Examples of the present invention will be described below.
It should be noted that, here, only the characteristic parts are shown and described, and the circuits and circuits obvious for configuring the nonvolatile memory, such as the erase and write circuits, the booster circuit, and the sense amplifier, are omitted. ing.

FIG. 1 shows a sample cell in a written state (FIG. 1A) and a sample cell in an erased state (see FIG. 1) provided in an electrically erasable nonvolatile memory according to an embodiment of the present invention.
It is a circuit diagram showing (B)) and its peripheral circuits. Figure 1
Elements common to (A) and FIG. 1 (B) are assigned the same numbers in both FIG. 1 (A) and FIG. 1 (B), and will be described simultaneously.

An analog switch 12 is connected to the gate 10a of the sample cell 10 so that the select signal S becomes L level during writing / erasing.
A write / erase voltage V1 is applied to the gate 10a of the. The writing / erasing voltage V1 is, for example, +5 to +12 V when writing, and is -4 to -1 when erasing.
0V is selected. In addition, the drain 10 of the sample cell 10
The analog switch 14 which is switched by the select signal S is also connected to b, and the write / erase voltage V2 is applied to the drain 10b via the input / output line 16 at the time of write / erase. As the write / erase voltage V2, for example, -4V at the time of writing and + 5V at the time of erasing are selected. The source 10c of the sample cell 10 is grounded. In this way, when a large number of memory cells (not shown in FIG. 1) having the same characteristics as the sample cell 10 are written and erased, each of the large number of memory cells is written once on average, Every time erasing is performed, the sample cell 10 shown in FIG. 1A is first erased and then written, and the sample cell 10 shown in FIG. 1B is first written and then erased. ..

When the select signal S is switched to H level,
As a result, the analog switches 12 and 14 are switched, and the drain 10b and the gate 10a are connected via the analog switches 14 and 12. Regarding FIG. 1 (A),
Since the memory cell 10 is programmed, the threshold voltage thereof is a positive voltage such as + 2V. Therefore, by applying the positive voltage V _CC , the threshold voltage V _{wr of the} memory cell 10 at the time of programming is increased. _ite is output.

As for FIG. 1B, memory cell 1
Since 0 is erased, its threshold voltage is
Is a negative voltage, such as -2V, and thus a negative voltage
Pressure V _n Erasing this memory cell 10 by applying
Threshold voltage V_{eras e} Is output. Figure 2
It is the figure which showed an example of the average voltage output circuit. Shown in Figure 1
Each threshold voltage output from each sample cell circuit
V_write , V_erase Configures this average voltage output circuit 20.
Via buffer circuits 21 and 22, respectively
After that, they are transmitted to one end of each of the resistors 23 and 24. Book
In the embodiment, these resistors 23 and 24 have the same resistance.
Has a value and therefore these two resistors 23, 2
Voltage V at the connection point of 4_out Is V_out = (V_write + V_erase ) / 2 (1) This voltage V_out Via the buffer circuit 25
Is output.

FIG. 3 is a nonvolatile memory of an embodiment of the present invention.
FIG. 6 is a circuit diagram showing a read circuit of a memory. Here is the memory
Only the reading of the stored contents of the file will be described. as mentioned above
And each threshold output from each sample cell 10
Voltage, V _write , V_erase Is the average voltage output circuit
V after being averaged and shown in equation (1)_{ou t} Is obtained and read
The select signal S becomes "H level" and the voltage V
_{ou t} Is applied to the gate 32a of the memory cell 32
The analog switch 31 is switched to. At this time,
The memory cell 32 whose contents are to be read
When in the state '0', the memory cell 32 remains in the off state.
That is, when the erased state is "1", the memory cell 32
Is turned on. This is shown via read line 33
Not detected by the sense amplifier.

Here, in the above embodiment, the sample cell 10 is used.
Two are provided, one is in a write state and the other is in an erased state,
Since those threshold voltages V _write and V _erase are obtained to obtain their average voltage V _out and this average voltage V _out is applied to the gate 32a of the memory cell 32, the memory cell 32 of the memory cell 32 is read at the time of reading as in the conventional case. Compared with the case where a constant voltage such as OV is applied to the gate, the change over time of the threshold voltage is taken into consideration, and the life of this nonvolatile memory is significantly extended.

Further, in the above embodiment, the threshold voltages V _write and V _erase of the sample cell are obtained as the average voltage V _out , but instead of _obtaining the simple average voltage, optimization is performed in consideration of the non-discrimination range described above. If you find the applied voltage,
The life can be further extended. Further, in the above embodiment, the two sample cells in the written state and the erased state are provided, but the number of the sample cells does not have to be two, and more sample cells may be provided, or only one sample cell is provided. Alternatively, the write state and the erase state may be alternately created, and at least one of the threshold voltages thereof may be stored and the average voltage may be obtained.

[0019]

As described above, the electrically erasable non-volatile memory of the present invention includes the sample cell and is based on the threshold voltage of the sample cell in the written state and the threshold voltage of the sample cell in the erased state. Since the intermediate voltage of these threshold voltages is output and applied to the gate of the memory cell, the secular change of the threshold voltage of the memory cell is compensated, and the number of rewritable times and the life are greatly extended.

[Brief description of drawings]

FIG. 1 shows a sample cell in a written state provided in an electrically erasable nonvolatile memory according to an embodiment of the present invention (FIG. 1).
FIG. 1A is a circuit diagram showing a sample cell in an erased state (FIG. 1B) and its peripheral circuits.

FIG. 2 is a diagram showing an example of an average voltage output circuit.

FIG. 3 is a circuit diagram showing a read circuit of a nonvolatile memory according to an embodiment of the present invention.

FIG. 4 shows threshold voltages of MNOS and MONOS,
6 is a graph showing an example of the dependence of the writing time and the erasing time.

FIG. 5 is a graph showing an example of charge retention characteristics of a memory cell called MNOS after writing and erasing a specified number of times (1 time, 10 ⁵ to 10 ⁷ times).

[Explanation of symbols]

 10 memory cell 12, 14, 31 analog switch 21, 22, 25 buffer circuit 32 memory cell 16, 33 read line

Claims (2)

[Claims] 1. A plurality of memory cells, write to each of the plurality of memory cells, write a number of times representative of the number of erase times, sample cells to be erased, and threshold voltages of the sample cells in a write state and erase states. A gate voltage control circuit for outputting an intermediate voltage of these threshold voltages based on the threshold voltage of the sample cell and applying the intermediate voltage to the gate of the memory cell when the memory cell is read. An electrically erasable non-volatile memory characterized by: 2. The gate voltage control circuit is capable of discriminating whether the memory cell is in a written state or an erased state, and a voltage at a boundary on the written state side of a voltage range where the memory cell is in a written state and the memory cell is in a written state. And a threshold voltage when the memory cell is in the erased state and a threshold voltage when the memory cell is in the erased state are substantially equal to each other. An electrically erasable non-volatile memory characterized by being output.