JPH05166942A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH05166942A JPH05166942A JP35198791A JP35198791A JPH05166942A JP H05166942 A JPH05166942 A JP H05166942A JP 35198791 A JP35198791 A JP 35198791A JP 35198791 A JP35198791 A JP 35198791A JP H05166942 A JPH05166942 A JP H05166942A
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- interlayer insulating
- layer
- insulating film
- contact hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は半導体装置及びその製
造方法に関し、特に半導体基板上に形成された微細な配
線の接続部及びその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a connection portion of fine wiring formed on a semiconductor substrate and a method of manufacturing the same.
【0002】[0002]
【従来の技術】半導体装置の高集積化に伴い、下層の電
極配線あるいは半導体基板の不純物拡散層からなる下層
導電層と、上層の電極配線からなる上層導電層とを接続
するために、両層を分離する絶縁層(層間絶縁膜)に形
成された柱状の穴(コンタクトホール)はその径の縮
小,深さの増大が進行している。これを解決する手段と
して柱状の接続穴に埋め込まれた接続用導電層(一般に
プラグと呼ばれる)を設ける方式が従来から採用されて
いる。2. Description of the Related Art As semiconductor devices become highly integrated, both layers are formed to connect a lower conductive layer made of a lower electrode wiring or an impurity diffusion layer of a semiconductor substrate to an upper conductive layer made of an upper electrode wiring. The columnar holes (contact holes) formed in the insulating layer (interlayer insulating film) that separates the holes are decreasing in diameter and increasing in depth. As a means for solving this, a method of providing a connection conductive layer (generally called a plug) embedded in a columnar connection hole has been conventionally adopted.
【0003】以下図を用いて説明すると、図2は従来の
半導体装置の配線接続部の断面図である。図において、
1は下地絶縁層上に形成された下層導電層、2はこの下
層導電層1上に形成された層間絶縁層であり、この絶縁
層3上に上層導電層4が形成され、上記下層導電層1と
上層導電層4とは、層間絶縁層2に形成されたコンタク
トホール2a内を充填するタングステン等の接続用導電
層3を介して電気的に結ばれている。Referring to the drawings below, FIG. 2 is a sectional view of a wiring connection portion of a conventional semiconductor device. In the figure,
Reference numeral 1 is a lower conductive layer formed on the underlying insulating layer, 2 is an interlayer insulating layer formed on the lower conductive layer 1, and an upper conductive layer 4 is formed on the insulating layer 3. 1 and the upper conductive layer 4 are electrically connected to each other through a conductive layer 3 for connection such as tungsten filling the contact hole 2a formed in the interlayer insulating layer 2.
【0004】次に製造方法について説明する。まず、下
地絶縁層上に下層導電層1を形成し、次いでこの上に層
間絶縁層2を形成した後、所定の位置に下層導電層1表
面に届くコンタクトホール2aを形成する。このコンタ
クトホール2a内にタングステン等の接続用導電層3を
形成し、その上に上層導電層4を形成する。上記工程に
おいて、接続用導電層3を形成する方法に関し、次の2
方式が一般的に用いられる。Next, the manufacturing method will be described. First, the lower conductive layer 1 is formed on the underlying insulating layer, then the interlayer insulating layer 2 is formed thereon, and then the contact hole 2a reaching the surface of the lower conductive layer 1 is formed at a predetermined position. A conductive layer 3 for connection such as tungsten is formed in the contact hole 2a, and an upper conductive layer 4 is formed thereon. Regarding the method of forming the conductive layer 3 for connection in the above step, the following 2
The method is commonly used.
【0005】1つは、CVD法等を用いてコンタクトホ
ール内を導電層で埋め込み不要な部分をエッチバックし
て除去する方法である。これは図3(a) に示すように、
まずコンタクトホール2aを設けた層間絶縁層2全面に
接続用導電層3となる導電膜30をCVD法等により堆
積させた後、図3(b) に示すように、ドライエッチング
法により選択的にコンタクトホール2a周囲の導電膜3
0を絶縁膜2の表面上から完全に除去し、穴に残った導
電膜を接続用導電層3とするものである。One is a method of filling the inside of the contact hole with a conductive layer and removing unnecessary portions by etching back using the CVD method or the like. This is as shown in Fig. 3 (a).
First, a conductive film 30 to be the conductive layer 3 for connection is deposited on the entire surface of the interlayer insulating layer 2 having the contact holes 2a by a CVD method or the like, and then, as shown in FIG. 3 (b), selectively by a dry etching method. Conductive film 3 around the contact hole 2a
0 is completely removed from the surface of the insulating film 2, and the conductive film left in the holes is used as the conductive layer 3 for connection.
【0006】もう1つは、図4(a) に示すように絶縁層
2に開けられたコンタクトホール2aの底面のみに材質
の異差を利用した選択CVD法により図4(b),(c) のよ
うに順次導電膜を堆積させ、これを接続用導電層3とす
るものである。The other is as shown in FIG. 4 (a), which is shown in FIGS. 4 (b) and 4 (c) by the selective CVD method utilizing the difference in material only on the bottom surface of the contact hole 2a formed in the insulating layer 2. ), A conductive film is sequentially deposited, and this is used as the conductive layer 3 for connection.
【0007】[0007]
【発明が解決しようとする課題】従来の半導体装置及び
その製造方法は以上のように構成されており、層間絶縁
層表面と接続用導電層上端面の高低差は、エッチバック
法の時はドライエッチング量により、また選択成長法の
時はCVD堆積量により決定され、通常、前者は下地段
差,上層導電層の膜厚均一性を考慮してエッチング量が
過剰となり、また後者は層間絶縁層表面への堆積を抑制
するため、堆積量が不十分となるのが一般的である。従
って、図2に示したように、接続用導電層上端面は周囲
の層間絶縁層表面より陥没してしまい、上層導電層をな
す導電膜の被覆性が悪化し、ひいては配線の信頼性の劣
化を招くという問題点があった。The conventional semiconductor device and the manufacturing method thereof are configured as described above, and the difference in height between the surface of the interlayer insulating layer and the upper end surface of the conductive layer for connection is dry when the etchback method is used. It is determined by the amount of etching, and in the case of the selective growth method, by the amount of CVD deposition. Usually, the former is an excessive amount of etching considering the underlying step and the film thickness uniformity of the upper conductive layer, and the latter is the surface of the interlayer insulating layer. In general, the amount of deposition is insufficient in order to suppress the deposition on the surface. Therefore, as shown in FIG. 2, the upper end surface of the conductive layer for connection is depressed from the surface of the surrounding interlayer insulating layer, the coverage of the conductive film forming the upper conductive layer is deteriorated, and the reliability of the wiring is deteriorated. There was a problem of inviting.
【0008】この発明は上記のような問題点を解消する
ためになされたもので、上層導電層をなす導電膜の被覆
性を向上させ、配線の信頼性を向上させることができる
半導体装置及びその製造方法を提供することを目的とす
る。The present invention has been made to solve the above problems, and a semiconductor device capable of improving the coverage of a conductive film forming an upper conductive layer and improving the reliability of wiring, and a semiconductor device thereof. It is intended to provide a manufacturing method.
【0009】[0009]
【課題を解決するための手段】この発明に係る半導体装
置及びその製造方法は、埋込導電層にてコンタクトホー
ルを充填した後、上記埋込導電層の上端面と上記層間絶
縁膜表面とがほぼ面一となるように、上記層間絶縁膜を
選択的に所定量除去するようにしたものである。In a semiconductor device and a method of manufacturing the same according to the present invention, after filling a contact hole with a buried conductive layer, an upper end surface of the buried conductive layer and a surface of the interlayer insulating film are separated from each other. The interlayer insulating film is selectively removed by a predetermined amount so as to be substantially flush.
【0010】[0010]
【作用】この発明においては、埋込導電層にてコンタク
トホールを充填した後、上記層間絶縁膜を選択的に所定
量除去して、上記埋込導電層の上端面と上記層間絶縁膜
表面とがほぼ面一となるようにしたから、層間絶縁膜表
面と埋込導電層の上端面の高低差を微小とするか、若干
量埋込導電層上端面が突出した形状となり、上層導電層
と埋込導電層との被覆性が向上し、配線の信頼性が向上
する。In the present invention, after filling the contact hole with the buried conductive layer, the interlayer insulating film is selectively removed by a predetermined amount to form the upper end surface of the buried conductive layer and the surface of the interlayer insulating film. Are almost flush with each other, the height difference between the surface of the interlayer insulating film and the upper surface of the embedded conductive layer is made small, or the upper surface of the embedded conductive layer is slightly protruded to form the upper conductive layer. The coverage with the embedded conductive layer is improved, and the reliability of the wiring is improved.
【0011】[0011]
【実施例】以下、この発明の一実施例による半導体装置
の製造方法を図について説明する。図1において、図2
と同一符号は同一または相当部分を示し、2aはエッチ
ングされて膜厚が減少した層間絶縁層を示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, FIG.
The same reference numerals denote the same or corresponding portions, and 2a denotes an interlayer insulating layer whose thickness is reduced by etching.
【0012】次に製造方法について説明する。まず、従
来例と同様の方法を用いて、下地絶縁層上にポリシリコ
ンの下層導電層1を形成し、その上に二酸化シリコンの
層間絶縁層2を形成しこれにコンタクトホール2aを開
口した後、図1(a) に示すように、エッチバックあるい
は選択成長を用いてコンタクトホール2a内に接続用導
電層3を形成する。Next, the manufacturing method will be described. First, a lower conductive layer 1 of polysilicon is formed on a base insulating layer, an interlayer insulating layer 2 of silicon dioxide is formed on the underlying insulating layer, and a contact hole 2a is formed in the lower conductive layer 1 by using the same method as in the conventional example. As shown in FIG. 1A, a conductive layer 3 for connection is formed in the contact hole 2a by using etch back or selective growth.
【0013】次いで図1(b) に示すように、絶縁層2の
表面及び接続用導電層3の上端面が露出した状態で、C
HF3 ,CF4 等の反応性ガスを用いたドライエッチン
グ方法により絶縁層2をなす二酸化シリコンだけを所望
量除去し、接続用導電層3のタングステンはほとんど除
去されないよう加工する。この時、接続用導電層3上端
面はエッチングされて層厚が減少した層間絶縁層20表
面より微小量突出している。この状態でスパッタリング
堆積法によりアルミニウム合金を堆積させた後、これを
フォトリソグラフィ法及びドライエッチング法により、
第1図(c) に示すように所望の配線パターンに加工して
上層導電層4とする。Then, as shown in FIG. 1B, with the surface of the insulating layer 2 and the upper end surface of the conductive layer 3 for connection exposed, C
By a dry etching method using a reactive gas such as HF 3 or CF 4 , only a desired amount of silicon dioxide forming the insulating layer 2 is removed, and the connection conductive layer 3 is processed so that the tungsten is hardly removed. At this time, the upper end surface of the conductive layer 3 for connection is slightly protruded from the surface of the interlayer insulating layer 20 whose thickness has been reduced by etching. In this state, after depositing the aluminum alloy by the sputtering deposition method, the aluminum alloy is deposited by the photolithography method and the dry etching method.
As shown in FIG. 1 (c), the upper conductive layer 4 is processed into a desired wiring pattern.
【0014】このように本実施例によれば、コンタクト
ホール2a内に接続用導電層3を形成した後、層間絶縁
層2を所定量エッチバックして接続用導電層3の上端面
を層間絶縁層20の表面より突出させ、この上に上層導
電層4を形成するようにしたから、接続用導電層3と上
層導電層4との接触面積が増大し、接続の良好な多層配
線を得ることができる。また、上層導電層4と接続用導
電層3の露出面との接触面積が増大し、配線の接続抵抗
が低減でき、配線の高性能化を図ることができる。As described above, according to this embodiment, after the connection conductive layer 3 is formed in the contact hole 2a, the interlayer insulating layer 2 is etched back by a predetermined amount to insulate the upper end surface of the connection conductive layer 3 with the interlayer insulation. Since the upper conductive layer 4 is formed so as to project from the surface of the layer 20, the contact area between the conductive layer 3 for connection and the upper conductive layer 4 is increased, and a multi-layer wiring with good connection can be obtained. You can Moreover, the contact area between the upper conductive layer 4 and the exposed surface of the conductive layer 3 for connection is increased, the connection resistance of the wiring can be reduced, and the performance of the wiring can be improved.
【0015】なお上記実施例では接続用導電層が層間絶
縁層よりも突出するまで層間絶縁層を後退させたが、接
続用導電層は必ずしも突出させる必要はなく、接続用導
電層の落ち込み量が微小となった所で絶縁層の後退を中
止するよう加工してもよい。In the above-mentioned embodiment, the interlayer insulating layer is receded until the connecting conductive layer protrudes beyond the interlayer insulating layer. However, the connecting conductive layer does not necessarily have to protrude, and the amount of depression of the connecting conductive layer can be reduced. It may be processed so that the receding of the insulating layer is stopped at a minute position.
【0016】また上記実施例では、下層及び上層導電層
が配線として用いられる場合について説明したが、これ
ら導電層は不純物拡散層等の他の導電層であってもよ
い。In the above embodiment, the case where the lower and upper conductive layers are used as wirings has been described, but these conductive layers may be other conductive layers such as an impurity diffusion layer.
【0017】[0017]
【発明の効果】以上のように、この発明によれば、埋込
導電層にてコンタクトホールを充填した後、上記層間絶
縁膜を選択的に所定量除去して、上記埋込導電層の上端
面と上記層間絶縁膜表面とがほぼ面一となるようにした
ので、層間絶縁膜表面と埋込導電層の上端面の高低差が
微小となるか、若干量埋込導電層上端面が突出した形状
となり、上層導電層と接続用導電層との接触面積が増大
し、上層導電層と埋込導電層との被覆性が向上し、上層
導電層と接続用導電層を低抵抗に接続することができ、
長期に渡る使用や過酷な使用条件においても信頼性の優
れた半導体装置を得ることができるという効果がある。As described above, according to the present invention, after the contact hole is filled with the buried conductive layer, the interlayer insulating film is selectively removed by a predetermined amount, and the upper surface of the buried conductive layer is removed. Since the end face and the surface of the interlayer insulating film are made to be substantially flush with each other, the height difference between the surface of the interlayer insulating film and the upper end surface of the embedded conductive layer becomes small, or the upper end surface of the embedded conductive layer slightly protrudes. The contact area between the upper conductive layer and the conductive layer for connection is increased, the coverage of the upper conductive layer and the buried conductive layer is improved, and the upper conductive layer and the conductive layer for connection are connected with low resistance. It is possible,
There is an effect that it is possible to obtain a highly reliable semiconductor device even under long-term use or severe use conditions.
【図1】この発明の一実施例による半導体装置の製造方
法を示す図。FIG. 1 is a diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
【図2】従来の半導体装置を示す断面構造図。FIG. 2 is a cross-sectional structure diagram showing a conventional semiconductor device.
【図3】従来の半導体装置の製造工程の一部を示す断面
構造図。FIG. 3 is a sectional structural view showing a part of the conventional manufacturing process of a semiconductor device.
【図4】従来の他の方法による半導体装置の製造工程の
一部を示す断面構造図。FIG. 4 is a sectional structural view showing a part of a manufacturing process of a semiconductor device by another conventional method.
1 下層導電層 2 層間絶縁層 2a コンタクトホール 20 層厚が減少した層間絶縁層 3 接続用導電層 4 上層導電層 1 Lower Conductive Layer 2 Interlayer Insulating Layer 2a Contact Hole 20 Interlayer Insulating Layer with Reduced Layer 3 Connection Conductive Layer 4 Upper Conductive Layer
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成4年6月17日[Submission date] June 17, 1992
【手続補正1】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】0003[Name of item to be corrected] 0003
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【0003】以下図を用いて説明すると、図2は従来の
半導体装置の配線接続部の断面図である。図において、
1は下地絶縁層上に形成された下層導電層、2はこの下
層導電層1上に形成された層間絶縁層であり、この層間
絶縁層2上に上層導電層4が形成され、上記下層導電層
1と上層導電層4とは、層間絶縁層2に形成されたコン
タクトホール2a内を充填するタングステン等の接続用
導電層3を介して電気的に結ばれている。Referring to the drawings below, FIG. 2 is a sectional view of a wiring connection portion of a conventional semiconductor device. In the figure,
Reference numeral 1 is a lower conductive layer formed on the underlying insulating layer, 2 is an interlayer insulating layer formed on the lower conductive layer 1, and an upper conductive layer 4 is formed on the interlayer insulating layer 2. The lower conductive layer 1 and the upper conductive layer 4 are electrically connected to each other through a conductive layer 3 for connection such as tungsten filling the contact hole 2a formed in the interlayer insulating layer 2.
【手続補正2】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】0006[Correction target item name] 0006
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【0006】もう1つは、図4(a) に示すように絶縁層
2に開けられたコンタクトホール2aの底面のみに、被
堆積面の材質の異差を利用した選択CVD法により図4
(b),(c) のように順次導電膜を堆積させ、これを接続用
導電層3とするものである。The other is to cover only the bottom surface of the contact hole 2a formed in the insulating layer 2 as shown in FIG. 4 (a).
By the selective CVD method utilizing the difference in the material of the deposition surface, FIG.
As shown in (b) and (c), conductive films are successively deposited to form the conductive layer 3 for connection.
【手続補正3】[Procedure 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】0010[Correction target item name] 0010
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【0010】[0010]
【作用】この発明においては、埋込導電層にてコンタク
トホールを充填した後、上記層間絶縁膜を選択的に所定
量除去して、上記埋込導電層の上端面と上記層間絶縁膜
表面とがほぼ面一となるようにしたから、層間絶縁膜表
面と埋込導電層の上端面の高低差を微小とするか、若干
量埋込導電層上端面が突出した形状となり、上層導電層
の埋込導電層上での被覆性が向上し、配線の信頼性が向
上する。In the present invention, after filling the contact hole with the buried conductive layer, the interlayer insulating film is selectively removed by a predetermined amount to form the upper end surface of the buried conductive layer and the surface of the interlayer insulating film. The upper and lower conductive layers have a shape in which the height difference between the surface of the interlayer insulating film and the upper surface of the buried conductive layer is made small, or the upper surface of the buried conductive layer protrudes slightly.
Improved coverage in the buried conductive layer of, reliability of the wiring is improved.
【手続補正4】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】0011[Correction target item name] 0011
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【0011】[0011]
【実施例】以下、この発明の一実施例による半導体装置
の製造方法を図について説明する。図1において、図2
と同一符号は同一または相当部分を示し、20はエッチ
ングされて膜厚が減少した層間絶縁層を示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, FIG.
The same reference numerals denote the same or corresponding portions, and reference numeral 20 denotes an interlayer insulating layer whose thickness is reduced by etching.
【手続補正5】[Procedure Amendment 5]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】0017[Correction target item name] 0017
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【0017】[0017]
【発明の効果】以上のように、この発明によれば、埋込
導電層にてコンタクトホールを充填した後、上記層間絶
縁膜を選択的に所定量除去して、上記埋込導電層の上端
面と上記層間絶縁膜表面とがほぼ面一となるようにした
ので、層間絶縁膜表面と埋込導電層の上端面の高低差が
微小となるか、若干量埋込導電層上端面が突出した形状
となり、上層導電層と接続用導電層との接触面積が増大
し、上層導電層の埋込導電層上での被覆性が向上し、上
層導電層と接続用導電層を低抵抗に接続することがで
き、長期に渡る使用や過酷な使用条件においても信頼性
の優れた半導体装置を得ることができるという効果があ
る。As described above, according to the present invention, after the contact hole is filled with the buried conductive layer, the interlayer insulating film is selectively removed by a predetermined amount, and the upper surface of the buried conductive layer is removed. Since the end face and the surface of the interlayer insulating film are made to be substantially flush with each other, the height difference between the surface of the interlayer insulating film and the upper end surface of the embedded conductive layer becomes small, or the upper end surface of the embedded conductive layer slightly protrudes. The contact area between the upper conductive layer and the conductive layer for connection is increased , the coverage of the upper conductive layer on the embedded conductive layer is improved, and the upper conductive layer and the conductive layer for connection are connected with low resistance. Therefore, there is an effect that a semiconductor device having excellent reliability can be obtained even under long-term use or severe use conditions.
Claims (2)
された上層導電層と、上記層間絶縁膜に形成されたコン
タクトホールを充填し、上記下層導電層と上層導電層と
を電気的に接続する埋込導電層とを備えた半導体装置に
おいて、 上記埋込導電層の上端面は、上記層間絶縁膜の表面より
も突出していることを特徴とする半導体装置。1. An upper conductive layer formed on the lower conductive layer via an interlayer insulating film and a contact hole formed in the interlayer insulating film are filled to electrically connect the lower conductive layer and the upper conductive layer. A semiconductor device including a buried conductive layer connected to the semiconductor device, wherein the upper end surface of the buried conductive layer projects beyond the surface of the interlayer insulating film.
コンタクトホールを設け、該コンタクトホールを埋込導
電層で充填したのち上記層間絶縁膜上に上層導電層を形
成する工程を有する半導体装置の製造方法において、 上記層間絶縁膜に形成されたコンタクトホール内を埋込
導電層にて充填する工程と、 上記埋込導電層の上端面と上記層間絶縁膜表面とがほぼ
面一となるように、上記層間絶縁膜を選択的に所定量除
去する工程とを含むことを特徴とする半導体装置の製造
方法。2. A semiconductor having a step of forming a contact hole in an interlayer insulating film formed on a lower conductive layer, filling the contact hole with a buried conductive layer, and then forming an upper conductive layer on the interlayer insulating film. In the method of manufacturing a device, the step of filling the contact hole formed in the interlayer insulating film with a buried conductive layer, and the upper end surface of the buried conductive layer and the surface of the interlayer insulating film are substantially flush with each other. And a step of selectively removing the interlayer insulating film by a predetermined amount.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP35198791A JPH05166942A (en) | 1991-12-13 | 1991-12-13 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP35198791A JPH05166942A (en) | 1991-12-13 | 1991-12-13 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05166942A true JPH05166942A (en) | 1993-07-02 |
Family
ID=18420999
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP35198791A Pending JPH05166942A (en) | 1991-12-13 | 1991-12-13 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05166942A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0799198A (en) * | 1993-06-24 | 1995-04-11 | Nec Corp | Manufacture for semiconductor device |
WO2011111507A1 (en) * | 2010-03-12 | 2011-09-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
-
1991
- 1991-12-13 JP JP35198791A patent/JPH05166942A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0799198A (en) * | 1993-06-24 | 1995-04-11 | Nec Corp | Manufacture for semiconductor device |
WO2011111507A1 (en) * | 2010-03-12 | 2011-09-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US9917109B2 (en) | 2010-03-12 | 2018-03-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
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