JPH05166369A - Semicnductor memory device - Google Patents

Abstract

PURPOSE:To ensure the fixed value of an output by successively setting the larger charge storage capacitance of a capacitor in each memory cell as a distance between the cell and a bit line are increased and keeping an output from each cell detected by means of a sense-amplifier constant. CONSTITUTION:When the capacitance of the capacitor in each memory cell in a cell block 12 is defined as C1, C2-CN started from the nearest cell to the bit line 10, the capacitance of each capacitor is set so as to satisfy the condition: CN>...>C3>C2>C1. Since the more the cell is apart from the bit line 10, the more the capacitance of the capacitor is increased based on such a set condition, a storage charging amount of the capacitor is increased more the cell is apart from the bit line 10. Therefore, by keeping an output level from each capacitor outputted to the bit line 10 uniform, the output is ensure to keep a prescribed value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a capacitor and a capacitor.
The present invention relates to improvement of a semiconductor memory device having a structure in which a plurality of memory cells each including one transistor are connected in series.

[0002]

2. Description of the Related Art There is a demand for semiconductor integrated circuits, particularly semiconductor memory devices, to further improve the degree of integration (storage capacity), and the elements are becoming finer.

Under such a background, "1 capacitor + 1
A semiconductor memory device has been proposed in which memory cells having a “transistor” structure are connected in series to form a cell block, and one end of the cell block is connected to a bit line. According to such a memory device, writing and reading are performed. Although there is a certain constraint in the above, if the cell area is the same, the storage capacity can be increased as compared with the conventional memory device (for example, “Kimura, K. et al. ISSCC91, Article No. TAM6.2”, or “Nikkei Electronics 199”).
(March 1 issue, pp. 87-88)).

FIG. 3 shows a partial structure of the proposed memory device. A plurality of cell blocks 12 are connected to each bit line 10, and the cell blocks 12 are
A predetermined number (for example, four) of memory cells 14 connected in series
It is composed of. Here, each cell block 12 is composed of one capacitor 16 having a fixed capacity (charge storage capacity) as a storage element and a transfer transistor 18 as a transfer gate connected to a word line.

That is, each memory cell 14 is connected in series, and writing and reading are performed in block units and cannot be accessed in memory cell units, while it is necessary to connect bit lines to each memory cell. Without
There is an advantage that the degree of integration can be increased.

In FIG. 3, the first memory cell is
The voltage Vp is applied to the bit line 10 by the action of the transistor 20. Also,
The bit line 10 is connected to a sense amplifier 22 that performs data read detection.

FIG. 4 is a timing chart showing the read operation of the semiconductor memory device shown in FIG.

In FIG. 4, when reading the data stored in the cell block, first, the transistor 20 is turned on, precharge is performed, and after the precharge is completed and the transistor 20 is turned off, Word line W
₁ is maintained at "H". At this time, the data stored in the capacitor of the first memory cell (“1” or
"0") appears on the bit line, which is detected by the sense amplifier 22. The voltage V _{BL of the} bit line detected by the sense amplifier is shown at the bottom of FIG.

Similarly, when the transistor 20 is turned on next, the bit line is precharged again, and the word line W ₂ is set to "H" after the precharge is completed,
At this time, since the word line W ₁ is maintained at “H” at the same time, data appears on the bit line 10 from the second memory cell.

The above operation is performed up to the last Nth memory cell, all the data in the block is detected by the sense amplifier, and the output is once stored in the register and then output to the outside.

In the reference, the semiconductor memory device having the above structure is referred to as "BORAM (block.
Oriented Random Access Memory) ”, the series cell structure in which one end is connected to the bit line is not necessarily limited to the RAM and can be applied to other types.

[0012]

However, in the above-mentioned semiconductor memory device, the capacitance of the capacitors and the voltage between the plates of all the memory cells are the same, and the memory cells from the memory cells far from the bit line are the same. There was a problem that the output signal became weaker. That is, originally, in order to stabilize the reading of each data, it is necessary to secure a predetermined value that keeps the level of the output signal from each memory cell detected by the sense amplifier constant. However, with respect to the first memory cell connected to the bit line, the memory cell located deeper than the first memory cell has one or a plurality of other memory cells in front of itself, which is not necessary for its own output path. There is a problem that the voltage detected by the sense amplifier drops due to the presence of the capacitance. In FIG. 4, the output from the first memory cell is illustrated by 101, and the outputs from the second and subsequent memory cells are illustrated by 102 to 104.

The present invention has been made in view of the above conventional problems, and an object thereof is to provide a semiconductor memory device having a series cell structure in which one end is connected to a bit line, regardless of the distance from the bit line. The purpose is to secure a predetermined value that keeps the output from each memory cell detected by the sense amplifier substantially constant.

[0014]

In order to achieve the above object, the present invention provides a plurality of memory cells, each of which is composed of one capacitor as a storage element and one transfer transistor connected to a word line, in series. In the semiconductor memory device in which the connected cell blocks are connected to bit lines, the capacitance of the capacitors is sequentially increased as the distance from the bit lines in the cell blocks increases.

Further, the present invention, the C ₁ the capacitance of the capacitor of each memory cell from the closest memory cell to bit lines in the cell block, C _2, C _3, ..., is defined as C _N, with the bit line When the capacitance is defined as C _BL , the capacitance C _{i of} each capacitor (where i = 2, 3, ..., N) is C _i / (C _BL + C ₁ + C ₂ + ... + C _i-1 ) = C ₁ It is characterized in that it substantially satisfies the relationship of / C _BL (1).

Further, the present invention is characterized in that the memory cells in the cell block are divided into a plurality of groups, and the capacitance of the capacitors is sequentially increased for each group as the memory cells are separated from the bit line.

[0017]

According to the above structure, since the capacitance of the capacitor is gradually increased as the distance from the bit line increases, the accumulated charge amount of the capacitor increases as the distance from the bit line increases.
Therefore, when it is read, it is possible to suppress a drop in the output voltage due to the influence of other memory cells existing before itself, that is, on the bit line side of itself.

Further, if the capacitance of each capacitor is set according to the condition of the above first equation, the ratio of the capacitance of the bit line to the capacitance of the capacitor of the first memory cell (there is a capacitance ratio of other capacitors). Since the ratio of the capacitance of the capacitor to the capacitance of the bit line including the capacitance of the capacitor before the capacitor) can be matched, the output level from each memory cell can be made substantially uniform.

Further, if the cell block is divided into a plurality of groups and the capacity is changed for each group, there is an advantage that the design and manufacturing can be simplified while obtaining the same effect as the above.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a preferred embodiment of a semiconductor memory device according to the present invention, and FIG. 1 is a block diagram showing a first embodiment.

In FIG. 1, the semiconductor memory device of the first embodiment has the same basic configuration as the conventional semiconductor memory device shown in FIG. 3, but the capacitances of the capacitors of the memory cells have different values. The configuration is different from the configuration shown in FIG. That is, in the first embodiment, when the capacitance of the capacitor of each memory cell in the cell block 12 is defined as C ₁ , C ₂ , C ₃ , ..., C _n from the memory cell closest to the bit line 10, The capacitance of the capacitor is set so as to satisfy the following second equation.

C _N >...> C ₃ > C ₂ > C ₁ (2) In other words, in the first embodiment, the capacitance of the capacitor is set to be successively larger as the distance from the bit line increases. Specifically, the capacitance is changed by changing the electrode plate area of the capacitor.

According to the above-mentioned condition setting, the capacitance of the capacitor increases as the distance from the bit line increases, so that the stored charge amount of the capacitor increases as the distance from the bit line increases. It is possible to suppress a drop in the output voltage due to the influence of the capacity of other memory cells existing in.

Further, in order to more strictly achieve the equalization of the output voltage detected by the sense amplifier 22, the capacitance of each capacitor may be set so as to substantially satisfy the condition of the following third equation.

C ₁ / C _BL = C ₂ / (C _BL + C ₁ ) = ... = C _N / (C _BL + C ₁ + ... + C _N-1 ) (3) However, C _BL has a bit line. Shows capacity. The third expression shows that the capacitance ratios of the other capacitors are matched with the ratio of the capacitance of the bit line to the capacitance of the capacitor of the first memory cell as a reference, and is detected by the sense amplifier 22. The output voltage can be made more uniform. In addition, = in each formula does not indicate the same in a strict sense, but indicates almost the same.

FIG. 5 shows the level of the bit line detected by the sense amplifier 22 in the semiconductor memory circuit of this embodiment, which corresponds to V _BL in FIG. As shown in FIG. 5, it is understood that the semiconductor memory device of this embodiment can make the output levels from the capacitors uniform.

FIG. 2 shows the configuration of the semiconductor memory device of the second embodiment.

In FIG. 2, the cell block 12 is divided into M groups, and the capacitances of the capacitors in each group are set so as to substantially satisfy the condition of the following fourth equation.

C _N = C _N-1 = C _N-2 = C _N-3 > C _N-4 = ...> C ₄ = C ₃ = C ₂ = C ₁ (4) That is, the capacitors in each group Are set to almost the same capacitance, and the capacitances of the capacitors increase sequentially from the group close to the bit line 10.

In order to set the capacity more properly, the capacity should be set so that the following fifth formula is almost satisfied.

C ₁ / C _BL = C ₅ / (C _BL + C ₁ + C ₂ + C ₃ + C ₄ ) = ... = C _N / (C _BL + C ₁ + ... + C _N-3 ) (5) By the way, this first In two embodiments, each group has four
Although it is composed of one memory cell, naturally it is not limited to four and may be another number.

According to the second embodiment, as compared with the first embodiment, it is possible to collectively set a certain number of capacities, so that there is an advantage that the design and manufacture thereof can be simplified.

As described above, according to the semiconductor memory devices of the first embodiment and the second embodiment, the output levels of the capacitors detected by the sense amplifier are made uniform and a predetermined value is ensured, and the sense amplifier is secured. The data reading operation can be stabilized, in other words, the operation margin of the sense amplifier can be secured. According to the above configuration,
The number of memory cells that can be connected in series is limited due to the variation in the output level of each capacitor in the cell block. However, according to the semiconductor memory device described above, memory cells that can be connected in series are not subject to such restrictions. There is an effect that the number of can be increased.

[0035]

As described above, according to the present invention,
As the distance from the bit line increases, the accumulated charge of the capacitor can be increased and the output level of each capacitor output to the bit line can be made uniform to ensure a predetermined value.
Therefore, it is possible to stabilize the operation of the sense amplifier connected to the bit line and increase the number of serially connected memory cells.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of a semiconductor memory device according to the present invention.

FIG. 3 is a circuit diagram of a conventional semiconductor memory device.

FIG. 4 is a timing chart showing the operation of the conventional semiconductor memory device.

FIG. 5 is an explanatory diagram showing the operation of the semiconductor memory device of this embodiment.

[Explanation of symbols]

 10 bit line 12 cell block 14 memory cell 16 capacitor 18 transfer transistor 22 sense amplifier

Claims (3)

[Claims] 1. A memory cell comprising a capacitor as a memory element and a transfer transistor connected to a word line,
In a semiconductor memory device in which a plurality of cell blocks connected in series are connected to a bit line, the capacitance of a capacitor of each memory cell in the cell block is sequentially increased as the distance from the bit line increases. Semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the capacitances of the capacitors of the memory cells in the cell block are C ₁ , C ₂ , C ₃ , from the closest one to the bit line.
, C _N and the capacitance of the bit line is defined as C _BL , the capacitance C _{i of} each capacitor (where i = 2, 3,
, N) substantially satisfies the relationship of C _i / (C _BL + C ₁ + C ₂ + ... + C _i-1 ) = C ₁ / C _BL . 3. A memory cell comprising a capacitor as a memory element and a transfer transistor connected to a word line,
In a semiconductor memory device in which a plurality of cell blocks connected in series are connected to a bit line, a plurality of memory cells in the cell block are divided into a plurality of groups, and as the distance from the bit line increases, each group is divided into groups. A semiconductor memory device characterized in that the capacitance of a capacitor is sequentially increased.