JPH05150807A - Sequential controller - Google Patents

Abstract

PURPOSE:To simply execute control by serial data from a microcomputer by using a logic circuit of a small scale by varying sequentially a value of a storage means in accordance with its number of times, when a LOAD signal is sent several times. CONSTITUTION:By three pieces of signal lines 1-3, a DATA signal, a CLOCK signal, and a LOAD signal are sent to a shift register 4. The sift register 4 receives serial data by synchronizing with a clock, and a counter 5 counts the LOAD signal. Conversion logic 6 converts an output of the sift register 4 in accordance with an output of the counter 5, and a storage means 7 stores an output of this conversion logic. When the LOAD signal is sent several times, a value of the storage means 7 is varied sequentially in accordance with its number of times. In such a way, high speed sequential control can be executed simply by serial data from a microcomputer by using a logic circuit of a small scale.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequential control device for controlling a servo circuit and a signal processing circuit by sending a complicated control command from a microcomputer, such as an optical reproducing device.

[0002]

2. Description of the Related Art In recent years, a sequential control device is required to have a sophisticated function for controlling a servo circuit and a signal processing circuit, and accordingly, a signal line from the microcomputer to the servo circuit and the signal processing circuit and a microcomputer. The number of output ports is increasing. In order to prevent this, in recent years, it has been attempted to send a command from a microcomputer to a servo circuit or a signal processing circuit as serial data.

However, since commands to the servo circuit are required to have high speed, when the serial data is sent, a sequential control circuit is required in the servo circuit.

[0004]

However, since the conventional sequential control device as described above has a sequential control circuit in the servo circuit, it can be easily controlled if it is controlled by a microcomputer. There is a problem that a logic circuit is required.

In view of the above conventional problems, the present invention has been made for the purpose of providing a sequential control device which can be easily controlled by serial data from a microcomputer by a small-scale logic circuit.

[0006]

In order to solve the above problems, a sequential control device of the present invention includes a shift register for receiving serial data in synchronization with a clock, and a DATA signal, a CLOCK signal, and a LO signal for the shift register.
It is composed of three signal lines for sending an AD signal, a counter for counting the LOAD signal, a conversion logic for converting the output of the shift register according to the value of the counter, and a storage means for storing the output of the conversion logic. When the signal is sent several times, the value of the storage means changes sequentially according to the number of times.

[0007]

With the above-described structure, the present invention makes it possible to easily perform high-speed sequential control with serial data from a microcomputer by means of a small-scale logic circuit, so that all sequential control logic can be concentrated in the microcomputer, so an inexpensive sequential control device. Will be provided.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a sequential control device of the present invention will be described in detail below with reference to FIGS.

FIG. 2 shows a peripheral block diagram of a sequential control device according to an embodiment of the present invention, which is a block diagram of an optical reproducing device having the sequential control device.

In FIG. 2, 31 is a disk, 32 is an optical head, 33 is a spindle motor for rotating the disk 31, 34 is a servo circuit, 35 is a signal processing circuit, 36 is an audio circuit, 37 is a microcomputer, 38 is a signal line for sending a command to the servo circuit and the signal processing circuit, 39 is a signal line for notifying the servo status from the servo circuit, and 40 is a signal line for notifying the signal processing status from the signal processing circuit.

The operation of the optical reproducing apparatus having the sequential control device configured as described above will be described below.

First, the disk 31 is a spindle motor 33.
Is controlled by the optical head 32 controlled by the servo circuit 34 so as to focus on the disk and follow the track. The signal reproduced by the optical head 32 is controlled by the waveform shaping circuit included in the servo circuit 34. The signal is amplified, shaped into a waveform, sent to the signal processing circuit 35, decoded and converted into an analog signal, and the audio circuit 36 amplifies and outputs the audio signal. The speed of the spindle motor 33 is controlled by the signal processing circuit 35 so that the signal is read at a constant speed.

From the microcomputer 37, DAT
A command is sent to the servo circuit 34 and the signal processing circuit 35 by a signal line 38 composed of three lines A, CLOCK, and LOAD, and the status is received from the signal line 39 or 40 to issue the next command to perform sequential control.

FIG. 1 is a logic diagram of a sequential control device according to an embodiment of the present invention. This block is the logic of the portion included in the servo circuit 34 and to which the signal line 38 is input.

In FIG. 1, 1 is a DATA signal line, 2 is a CLOCK signal line, 3 is a LOAD signal line, 4 is a shift register, 5 is a counter, 6 is a conversion logic, 7 is a storage means constituted by a latch, and 9 is a storage means. , 14, 22 are inverters, 10, 11, 12, 15, 16, 23, 2
4 and 25 are AND gates (hereinafter abbreviated as AND), 1
3, 17, 18, and 19 are OR gates (hereinafter abbreviated as OR), and 20 and 21 are EXCLUSIVE-OR gates (hereinafter abbreviated as EX-OR).

The operation of the sequential control device configured as described above will be described below with reference to FIGS.

Table 1 is a command table for the servo circuit 34 of the sequential control device in the embodiment of the present invention (a command for the signal processing circuit 35 is separately provided, but omitted). T0 to T3 are traverses (optical heads). For moving the device in the radial direction) command for control, S
0 to S15 are commands for optical servo (focus control, tracking control).

[0018]

[Table 1]

FIG. 3 is a timing chart of serial commands to the servo circuit 34 of the sequential control device according to the embodiment of the present invention. DATA is command data in the command table of (Table 1) and CLOCK is for serially sending data. Clock and LOAD are load signals indicating command delimiters. DATA is bit B7-
It is composed of B0, and the bits B7 and B6 are each 1, which is an identification signal indicating that this is a command to the servo circuit 34. The LOAD signal drops four times, but this is the sequential operation which is the point of the present invention.

In Table 1, commands that need to be controlled at high speed are commands S1 and S2 relating to a multi-kick and commands S5 and S6 relating to a single kick.

FIG. 4 is an operation explanatory view by a serial command to the servo circuit 34 of the sequential control device in the embodiment of the present invention, (A) is an operation explanatory view of one Kick, and a is an optical head in the tracking direction. A Kick signal that causes acceleration and deceleration to cause a track jump, b is a CROSS signal that switches when it reaches the center of the track,
(B) is an example of multi-kick, and is an operation explanatory diagram of 10-kick, where a is a Kick signal, b is a CROSS signal, and c is an off-track (hereinafter referred to as OFTR) in which H is output when it is between tracks. ) Is a signal. Further, t1 to t8 indicate operation timings.

First, a single FWD Kick will be described. In FIG. 4A, the command S6 in (Table 1) is serially transmitted in the format of FIG. 3, and the timing when the LOAD signal falls for the first time is timing t1 and one Kick is started. Next, at a timing t2 after a fixed time, the second LOAD signal is made to fall and Kic
In the state of k HOLD, stop acceleration, fly free, monitor CROSS signal b, and at the timing t3 when it is detected that the center of the track is reached, the third LOA
The D signal is made to fall and acceleration in the opposite direction is applied to start braking, and the fourth LOAD signal is made to fall at the timing t4 when almost the same time as the initial acceleration time has elapsed.

The REV single Kick can be controlled in the same sequence as the FWD single Kick by sending the command S5.

Next, 10 FWD Kick will be described. In FIG. 4B, the timing t5 is when the command S2 in (Table 1) is serially sent in the format of FIG. 3 and the LOAD signal falls for the first time.
And 10 Kick will be started. Next, the timing t when the CROSS signal is counted five times and five tracks are skipped
At 2 the second LOAD signal is dropped, the acceleration direction is reversed, and the brake is applied.
The tracking pull-in mode is set by falling the LOAD signal for the fourth time, and the fourth LOAD signal is dropped at timing t4 when the OFTR signal becomes L for a certain time. Here, the tracking pull-in mode means the CROSS signal and O
The direction is discriminated in the phase direction of the FTR signal, and when the acceleration is generated in the direction opposite to the moving direction, the tracking signal is directly passed, and when the acceleration is generated in the same direction, the amplitude is limited and the brake is applied to perform tracking. It is a mode to pull in quickly.

The REV 10-piece Kick can be controlled in the same sequence as the FWD 10-piece Kick by sending the command S1.

The logic operation of the sequential control device shown in FIG. 1 will be described in detail below.

First, FIG. 3 input from the DATA signal line 1
The bits B0 to B7 are transmitted to the shift register 4 by the clock from the CLOCK signal line 2, converted into parallel data, and output to Q0 to Q7. When the counter 5 is reset, C0 is 1 and the others are 0. When T rises once, C1 is 1 and the others 0, when it rises 2 times, C2 is 1 and the others 0, 3 times, C3 is 1 and others. Is a counter that becomes 0, and is reset when the CLOCK signal becomes 0. Therefore, 1 is initially output to C0 and 0 is output to the others.

Therefore, the input of the AND12 of the OR13 is 0.
Therefore, the output is 0 and the AND15 input is also 0, so the output is 0
Therefore, the output is 0, and the input of AND16 is 0 for OR17.
Therefore, since the output is 0 and C1 is also 0, the output is 0, and since the inverter 22 outputs 1 because C3 is 0, the conversion logic 6 passes data directly.

The AND10 monitors whether both Q6 and Q7 are 1, that is, whether the command is for the servo circuit.
AND the OAD signal inverted by the inverter 9
11 is stored in the storage means 7 at the fall of the LOAD signal, and if it is not a command for the servo circuit, AN
D11 is closed to ignore the LOAD signal.

Next, when the CLOCK signal is fixed to 1, only C1 of the counter 5 is 1, and
If the output Q2 of the shift register 4 is 1 (one Ki
ck), 1 is output from AND12, 1 is output from OR13, and 1 is also output from OR17.
1 is output from 18 and OR19, and EX-OR20 and E
It is inverted by the X-OR 21 to output 0, and the storage means 7
0 is forcibly input to the inputs D0 and D1 of the command S
5 (Kick HOLD) is set. If the output Q2 of the shift register 4 is 0 (in the case of multiple Kick), 0 is output from AND12 and 0 is also output from AND15.
Is output, OR13 outputs 0, and OR18 and O
Since the R19 passes the data through and the OR17 outputs 1, the data is inverted and output by the EX-OR20 and the EX-OR21 and input to the inputs D0 and D1 of the storage means 7, and originally the command S2 ( Kick FWD)
If so, the command S1 (Kick REV) is set. If originally the command S1, the command S2 is set. Here, at the second fall of the LOAD signal, the data converted by the conversion logic 6 is stored in the storage means 7.

Next, when the CLOCK signal is fixed at 1, the counter 5 has only C2 set to 1,
If the output Q2 of the shift register 4 is 1 (one Ki
ck), 1 is output from AND16, 1 is output from OR17, and 0 is output from AND12 and AND15, so 0 is also output from OR13.
No. 19 outputs plain data, and EX-OR 20 and E
The data inverted by the X-OR21 is output, and the inputs D0 and D1 of the storage means 7 originally have the command S6 (Ki).
ck FWD), command S5 (Kick RE
If V) is originally command S5, command S6
Is set. If the output Q2 of the shift register 4 is 0 (in the case of multiple Kick), 0 is output from AND12, but 1 is output from AND15.
13 outputs 1 and OR18 and OR19 forcibly output 1 and AND16 outputs 0, so OR1
0 is output from 7, and EX-OR20 and EX-OR2
At 1, the data is passed through to output 1 and 1 is forcibly input to the inputs D0 and D1 of the storage means 7, and the command S3
(TR pull-in) is set. Here is the third L
At the fall of the OAD signal, the data converted by the conversion logic 6 is stored in the storage means 7.

Next, when the CLOCK signal is fixed to 1, the counter 5 outputs C 0 because the counter 22 outputs 0, and the ANDs 23, 24, 25.
0 is output, and 0 is forcibly input to the inputs D0, D1, D2 of the storage means 7, and the command S0 (FO ON, T
R ON) is set. Here, at the fourth fall of the LOAD signal, the data converted by the conversion logic 6 is stored in the storage means 7.

As described above, according to this embodiment, a small-scale logic circuit can easily perform high-speed sequential control with serial data from a microcomputer.

Further, in this embodiment, the shift register, the counter and the conversion logic are constituted by so-called random logic.
It goes without saying that the shift register may be replaced by RAM, the counter may be soft counting, the conversion logic may be software sequential logic, and the storage may be RAM in the microcomputer.

[0035]

As described above, according to the present invention, the number of output ports of a microcomputer can be reduced, and high-speed sequential control can be easily performed with serial data from the microcomputer by a small-scale logic circuit. Since all can be concentrated on a microcomputer, an inexpensive sequential control device can be provided.

[Brief description of drawings]

FIG. 1 is a logic diagram of a sequential control device according to an embodiment of the present invention.

FIG. 2 is a peripheral block diagram of a sequential control device according to an embodiment of the present invention.

FIG. 3 is a timing chart of serial commands for the servo circuit of the sequential control device according to the embodiment of the present invention.

FIG. 4A is an operation explanatory diagram of a servo circuit of the sequential control device according to the embodiment of the present invention by a serial command, and shows an operation of one kick. FIG. 9B is an operation explanatory diagram of a servo circuit of the sequential control device according to the embodiment of the present invention by a serial command, and shows an operation of multiple Kick.

[Explanation of symbols]

 1 DATA signal line 2 CLOCK signal line 3 LOAD signal line 4 shift register 5 counter 6 conversion logic 7 storage means

Claims (1)

[Claims] 1. A shift register for receiving serial data in synchronization with a clock, and a DAT for the shift register.
Three signal lines for sending an A signal, a CLOCK signal, and a LOAD signal, a counter for counting the LOAD signal, a conversion logic for converting the output of the shift register according to the value of the counter, and an output of the conversion logic A sequential control device comprising a storage means for storing.