JPH05159586A - Flash eeprom - Google Patents

Abstract

PURPOSE:To shorten a time for rewriting sharply by a construction wherein a latch circuit for page programming is provided for each bit line, while a source line of a memory cell on a selected word line is connected to a source line switch. CONSTITUTION:A plurality of latch circuits 22 which take in and latch input data from an I/O line 20 and supply a program voltage to the respective bit lines on the basis of a write control signal are provided. While an X decoder 24 selects a word line, a source line 21 of memory cells on the selected word line is connected to a source line switch 3. After the memory cells corresponding to the selected word line are erased, by this constitution, information can be written collectively in the memory cells on the selected word line on the basis of the write information latched by the latch circuits. Accordingly, rewriting of information can be executed for the memory cells for each word line without erasing all memory cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a flash EEPROM capable of significantly shortening rewriting time.

[0002]

2. Description of the Related Art FIG. 6 shows the IEEE Journal of Solid-Stat.
e Circuits, Vol.23, No.5, October 1988 1157-116
FIG. 4 is a block diagram showing a configuration of a conventional flash EEPROM shown on page 3, in which 1 is a memory array, and around the memory array 1, a Y gate 2, a source line switch 3, an X decoder 4, A Y decoder 5 is provided, an address register 6 to which an externally input address signal is input is connected to the X decoder 4 and the Y decoder 5, and an input data register is connected to the memory array 1 via the Y gate 2. (Write circuit) 7 and sense amplifier 8
The input data register 7 and the sense amplifier 8 are connected to the input / output buffer 9, respectively. Also, 1
Reference numerals 0 and 11 denote a program voltage generating circuit and a verify voltage generating circuit which generate a voltage different from Vcc and Vpp supplied from the outside. These voltages are applied to the Y gate 2,
It is supplied to the X decoder 4 and the like. Further, reference numerals 12 and 13 denote command registers and command decoders for setting operation modes according to data input from the outside, and 14 denotes input signal buffers to which control signals / WE, / CE, / OE from the outside are input.

FIG. 7 is a diagram showing a cross section of a memory cell in the memory array 1 of FIG. 6, in which 15 is a semiconductor substrate, 16 is a floating gate, 17 is a control gate, and 18 is formed on the semiconductor substrate 15. The source diffusion region 19 is a drain diffusion region formed on the semiconductor substrate 15. Here, floating gate 16
An oxide film (thickness: about 100 Å) which is not shown is formed between the semiconductor substrate 15 and the semiconductor substrate 15, and electrons can move to the floating gate 16 by utilizing the tunnel phenomenon. It is like this.

Next, the operation of this memory cell will be described.
Drain 19 and control gate 17 during programming
A program voltage of about 6.5 V and Vpp (12 V) are applied to the source 18, and the source 18 is grounded, whereby the memory cell is turned on and a current flows. Then, at this time, avalanche breakdown occurs near the drain 19 to generate electron-hole pairs, the holes flow to the ground potential (not shown) through the semiconductor substrate 15, and the electrons flow in the channel direction to flow into the source 18. Here, since some electrons are accelerated by the electric field formed between the floating gate 16 and the drain 19, they are injected into the floating gate 16 and the threshold voltage of the memory cell rises. Here, the rise of this threshold value is defined as the storage of information "0". On the other hand, at the time of erasing, when the drain 19 is opened, the control gate 17 is grounded, and Vpp is applied to the source 18, an electric field is formed between the source 18 and the floating gate 16, which causes a tunnel phenomenon.
The extraction of electrons from the floating gate 16 occurs, which lowers the threshold voltage of the memory cell. Here, this decrease in threshold value is defined as storage of information "1".

FIG. 8 is a diagram showing in detail the circuit configuration of the memory array of FIG. 6 and its peripheral portion.
The same reference numerals as those in FIG. 6 indicate the same or corresponding portions, and BL
1, BL2, BL3 are bit lines, WL1, WL2, WL
3 is a word line, 2a, 2b, 2c are Y gate transistors, 20 is an I / O line, 21 (21a, 21b, 21c)
Is the source line. And the drain 1 of each memory cell
9 is connected to the bit lines BL1, BL2, BL3, the control gate 17 is connected to the word lines WL1, WL2, WL3, respectively, the word lines WL1, WL2, WL3 are connected to the X decoder 4, respectively, and the bit lines BL1, BL2.
BL3 is connected to the sources of the Y gate transistors 2a, 2b, 2c, respectively, and is connected to the Y gate transistors 2a, 2b.
The drains of b and 2c are connected to the I / 0 line 20,
A sense amplifier 8 and a write circuit 7 are connected to the line 20, and a source line switch 3 is connected to the source lines 21a, 21b, 21c.

FIG. 11 is a diagram showing a circuit configuration of the X decoder 4 and the Y decoder 5 shown in FIG. 8, in which 30 and 32 are P channel transistors and 31, 3 respectively.
3, 34 are N-channel transistors, 35 is an inverter, 36 is a NAND gate, Vdec is a decoder power supply, ERSM is an erase control signal, Y is an output node of the Y decoder, and X is an output node of the X decoder. ..
The decoder power supply Vdec supplies Vpp at the time of writing and erasing, Vcc at the time of reading, and respective verify voltages at the time of writing and erasing verify,
If the erase signal ERSM is "L", the power supply voltage for the decoder is set to the word line and Y by the selection of the address signal.
The signal is output to the gate 2 through the output nodes X and Y, and if the erase signal ERSM is "H", the output is grounded regardless of the address signal.

FIG. 12 is a diagram showing a circuit configuration of the source line switch 3 shown in FIG.
41 is a P-channel transistor, 37, 38, 40,
42 is an N-channel transistor, 43 is an inverter, and ERSM is an erase control signal. And
If the erase control signal ERSM is "H", Vpp is supplied to the source line 21, and if the erase control signal ERSM is "L", it is grounded.

Next, the operation for writing data in the memory cell surrounded by the dotted line in FIG. 8 will be described. The write circuit 7 is activated according to the data input from the outside,
A program voltage is supplied to the I / 0 line 20. And
At the same time, the Y gate transistor 2a and the word line WL1 are transmitted through the Y decoder 5 and the X decoder 4 by the address signal.
Are selected and Vpp is applied to them through output nodes Y and X.
Is applied. At this time, the source line 21a is grounded by the source line switch 3 and surrounded by a dotted line 1 in the figure.
A current flows only in this cell, hot electrons are generated, and the threshold voltage of this memory cell is raised.

On the other hand, since the erase control signal ERSM becomes "H" during erase, the output of the X decoder 4 is grounded regardless of the address signal, the control gate 17 of each memory cell is grounded, and the drain 19 is open. To be done. Then, from the source line switch 3 to the source line 21
A positive high voltage is supplied to the sources of the memory cells connected to a, 21b, and 21c, and as a result, electrons are extracted from the floating gate 16 of each memory cell by the tunnel phenomenon, and the threshold value shifts to the lower side. Then, erasing is performed on all the memory cells at once.

Next, the read operation of the memory cell surrounded by the dotted line in FIG. 8 will be described. The address signal is decoded by the Y decoder 5 and the X decoder 4, and the selected Y gate 2a and word line WL1 become "H". At this time, the source line 21a is grounded by the source line switch 3. When the memory cell is written and the threshold value is high, the control gate 1 of the memory cell is
Even if "H" is given to the memory cell 7 by the word line WL1, the memory cell does not turn on, no current flows from the bit line BL1 to the source line 21a, while when the memory cell is erased, conversely Is turned on, a current flows from the bit line BL1 to the source line 21a, and the sense amplifier 8 detects whether or not the current flows through the memory cell to obtain read data "1""0".

By the way, since electrons are excessively extracted from the floating gate 16 at the time of erasing, the floating gate 16 is positively charged and a phenomenon called over-erasing (or over-erasing) occurs, and the threshold value of the memory transistor becomes negative. May be. When the threshold value of the memory cell becomes negative, it hinders subsequent reading and writing. That is, even if the level of the word line WL is "L" when unselected during reading and the level applied to the control gate of the memory cell is "L", current flows from the bit line through the memory cell. Therefore, even if the threshold value is high in the written state, the memory cell trying to read on the same bit line will read the read data “1”, and the over-erased memory cell will pass through even during the writing. As a result, a leak current flows, which deteriorates the writing characteristics and further disables writing. Therefore, read after erasure to check if the erasure is correct (erase verify)
However, if there is a bit that is not erased, a method of erasing again is adopted to prevent an extra erase pulse from being applied to the memory cell. FIG. 9 is a flow chart of erase and program including such a verify operation, and FIG. 10 shows a timing waveform diagram thereof.

The erase and program steps will be described below with reference to FIGS. 6, 9 and 10. In the flash EEPROM having the above-described structure, the erase and program modes are set by a combination of input data, and the mode is set by the input data at the rising edge of / WE.

First, the case of a program will be described. First, Vcc and Vpp are raised (step S
1), followed by / WE. After that, at the rising edge of / WE, the input data (40H) is latched in the command register 12 (step S2), and then the input data is decoded by the command decoder 13 and the operation mode becomes the program mode. Then / WE was turned off again,
The address signal from the outside is latched in the address register 6, and the data is latched in the write circuit 7 at the rising edge of / WE (step S3). Next, a program pulse is generated by the program voltage generating circuit 10 and applied to the X decoder 4 and the Y decoder 5, respectively, to perform programming (step S4). Next, / WE is lowered, and at the subsequent rising of / WE, the input data (C0H) is latched in the command register 12, and the operation mode becomes the program verify mode (step S5). At this time, the erase / program verify voltage generation circuit 11 causes the program verify voltage (up to 7.0) inside the chip.
V) is generated and applied to the X decoder 4 and the Y decoder 5. Further, since the voltage applied to the control gate 17 of the memory cell is higher than that during normal reading (5V), the memory cell in which writing is insufficient becomes easy to turn on, and the writing failure can be detected more reliably. next,
Reading is performed (step S7), and write data is confirmed (step S8). At this time, if the writing is insufficient, the writing is further repeated, and if the writing is performed, the operation mode is set to the reading mode (step S9), and the program ends.

Next, the case of erasing will be described. First, Vcc and Vpp are raised (step S10),
Then, "0" is written in all bits by using the above-mentioned program flow (step S11). This is because the memory cells are over-erased when the erased memory cells are further erased. Next, lower / WE,
Subsequently, the erase command (20H) is input at the rise of / WE (step S12). Then, / WE is lowered again, and the erase command (20H) is input at the subsequent rising of / WE (step S13). At this time, an erase pulse is generated inside the chip, and Vpp is applied to the source 18 of the memory cell through the source line switch 3 until the trailing edge of / WE.
Is applied (step S14). The address is also latched at this falling edge. At the subsequent rise of / WE, the erase verify command (A0H) is latched, and the operation mode becomes the erase verify mode (step S15). At this time, the erase / program verify voltage generation circuit 11 generates an erase verify voltage (up to 3.2 V), and X
It is applied to the decoder 4 and the Y decoder 5. Since the voltage applied to the control gate 17 of the memory cell is lower than the voltage (5 V) at the time of normal reading, it becomes difficult to turn on the memory cell that is not sufficiently erased, and the erase failure can be detected more reliably. Next, reading is performed (step S16) to confirm the erased data. At this time, if the erasing is insufficient, the erasing is further repeated. If erased, the address is incremented (step S1
7) Then, the erase data of the next address is verified. If the verified address is the last address (step S18), the operation mode is set to the read mode (step S19) and the erasing is completed.

[0015]

When rewriting the information in the memory cells in the above-mentioned conventional flash EEPROM, erasing is performed collectively for all the memory cells, but if the memory capacity increases, the time required for writing becomes longer. Therefore, there is a problem that the rewriting time naturally becomes long. Therefore, in order to reduce the time required for writing during rewriting, a write function for collectively writing data to be written in memory cells on the same word line in a latch circuit for a plurality of bytes, that is, a page programming function is provided. Although it may be possible to add it, as described above, in the flash EEPROM, erasing is performed collectively on all memory cells, and therefore writing is performed on all memory cells including memory cells storing information that does not need to be rewritten. Therefore, there is a problem that the rewriting time cannot be shortened sufficiently.

The present invention has been made to solve the above problems, and an object thereof is to obtain a non-volatile semiconductor memory device capable of significantly shortening the rewriting time.

[0017]

In a flash EEPROM according to the present invention, a source line of a memory cell on a word line selected by an address signal is supplied to each bit line together with a latch circuit for page programming. It is designed so that it can be connected to a source line switch based on a signal.

Further, the flash EEP according to the present invention
The ROM is provided with a latch circuit for latching write information for page programming for each bit line, and X is provided for a word line selected by an address signal.
A high negative voltage is supplied from the decoder.

[0019]

In the flash EEPROM according to the present invention, the word line of the memory cell for which information is to be rewritten is selected by the address signal, and only the source line connecting the memory cells on the selected word line receives the address signal. Since it is connected to the source line switch on the basis of this, page programming can be performed after erasing only the memory cell on the word line to be rewritten.

The flash EEP according to the present invention
In a ROM, a word line of a memory cell to be rewritten with information is selected by an address signal, and a negative high voltage is supplied from the X decoder to the selected word line. After erasing only those memory cells, page programming can be performed.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a flash E according to an embodiment of the present invention.
FIG. 9 is a diagram showing in detail the circuit configuration of a memory array and its peripheral portion in an EPROM. In the figure, the same symbols as in FIG. 8 indicate the same or corresponding portions, 24 is an X decoder, and 22a, 22b, 22c are write circuits. Latch circuits (LA1, LA2, LA3) provided on bit lines BL1, BL2, BL3 connected to 7, 23a, 23c,
23b is X with respect to the source lines 21a, 21b, and 21c.
The X gate is provided so that the output of the decoder 24 can be input. Here, the entire device configuration other than that shown in FIG. 1 is basically the same as that of the conventional flash EEPROM shown in FIG.

FIG. 5 is a circuit diagram of the latch circuit (LA
1, LA2, LA3) 22a, 22c, 22b, and 51, 53, 55, 5 in the figure.
9, 60, 61, 62 are N-channel transistors, 5
2, 54, 56, 57, 58 and 63 are P-channel transistors, 64 and 65 are inverters, and DL (/ D
L) is a latch signal, PR / O (/ PR / O), PR / O
0 indicates a write signal, and OE (/ OE) indicates a read control signal. Then, when the latch signal DL becomes "H", the input data is fetched from the I / O line 20, and when the latch signal DL becomes "L", the fetched input data is held. Further, when the write signal PR / O becomes “H”, the held input data is taken out, and if the taken-out input data is “0”, the program voltage is supplied to the bit line BL. Further, when the write signal PR / O0 becomes “H”, the program voltage is supplied to the bit line BL regardless of the held input data. Further, the control signal / OE is "L", that is, the bit line B at the time of reading.
L is directly connected to the Y gate transistor 2.

FIG. 3 is a diagram showing a circuit configuration of the X decoder 24 shown in FIG. 1. In the figure, the same reference numerals as those in FIG. 11 denote the same or corresponding portions, 67 and 68 are P channel transistors, and 69 is An N-channel transistor, Vdec is a decoder power supply, ERSM is an erase control signal, and X and X'are word lines WL (WL1, W1).
L2, WL3) and the output nodes to the source lines 21a, 21b, 2c are shown. Then, Vpp at the time of writing and erasing, Vcc at the time of reading, and verify voltages at the time of programming and erasing verification are supplied from the decoder power supply voltage Vdec. The decoder power supply voltage Vdec is output to the selected word line, and if the erase control signal ERSM is "H", the decoder power supply voltage is grounded regardless of the address signal. Further, the decoder power supply voltage Vdec is output from the other output node X ′ to the selected source line by selecting the address signal regardless of the erase control signal ERSM.

Next, a description will be given of a case where the memory cell for one word line surrounded by a dotted line in the drawing is rewritten by using the page programming function. Rewriting of a memory cell is performed during a period in which write information and its address are latched, a period in which “0” is written regardless of the write information to prevent overerasure, a period in which erase is performed, and a period in which write information is written It is divided into

First, the Y date transistors 2a, 2b, 2c are sequentially selected through the Y decoder 5 by the address signal, and the information for one word line is latched by the latch circuit 22 (22).
a, 22b, 22c) and latched. Here, the address register 6 includes a latch circuit, and the last input address signal is latched.

The writing of "0" is performed as follows. That is, the word line WL1 is selected through the X decoder 24 (through the output node X) by the address signal latched in the address register 6, and the word line W1 is selected.
Vpp is supplied to L1. Then, each latch circuit 22
Write pulse signal P input to a, 22b, and 22c
RO0 becomes “H” at the same time or sequentially and each latch circuit 2
The program voltage is supplied to the bit lines BL1, BL2, BL3 simultaneously or sequentially regardless of the write information latched in 2a, 22b, 22c. At this time, the write signal PR / O is fixed at "L". In addition, the X decoder 2 receives the address signal latched in the address register 6.
X gate 23a through 4 (through output node X ′)
Is selected, and the source line 21a is grounded by the source line switch 3. As a result, a current flows through all the memory cells for one word line surrounded by the dotted line in the figure, hot electrons are generated, and the threshold voltage of the memory cell is increased.

Erasing is performed as follows. First,
Since the erase control signal ERSM becomes "H" during erase,
The output node X of the X decoder 24 and the output node Y of the Y decoder are grounded regardless of the address signal, the control gate 17 of each memory cell is grounded, and the drain 19 is opened. Further, the X signal 23a is selected through the other output node X'of the X decoder 24 by the address signal latched in the address register 6, and a positive high voltage is applied to the source of the memory cell connected from the source line switch 3 to the source line 21a. Is supplied. As a result, the tunnel phenomenon causes the electrons in the floating gate 16 of each memory cell corresponding to the word line WL1 to be withdrawn, and the threshold value is shifted to the lower side for erasing.

Writing is performed as follows. First, the word line WL1 is selected and Vpp is supplied through the X decoder 24 (through the output node X) by the address signal latched in the address register 6.
The write pulse signals PRO input to the latch circuits 22a, 22b, 22c are "H" simultaneously or sequentially.
If the write information latched by the latch circuits 22a, 22b, 22c is "0", the program voltage is supplied to the bit line BL connected to the latch circuit simultaneously or sequentially. At this time, the write signal PRO0 is fixed at "L". Further, the X gate 23 a is selected through the output node X ′ of the X decoder 4 by the address signal latched in the address register 6, and the source line 21
a is grounded by the source line switch 3. as a result,
Current flows only in the memory cell to be written among the memory cells for one word line surrounded by the dotted line in the figure, hot electrons are generated, and the threshold voltage of the memory cell is increased.

Next, the read operation of the memory cell surrounded by the dotted line in FIG. 1 will be described. When the address signal is decoded by the Y decoder 5 and the X decoder 24 and selected, the Y gate 2a and the word line WL1 become "H".
Since the control signal / OE becomes "L" during reading, the bit line BL is directly connected to the Y gate transistor 2 in the latch circuit 22 (22a, 22b, 22c).
Further, the X gate 23a is selected through the output node of the X-dacoder 24 by the address signal through X ', and the source line 2
1a is grounded by the source line switch 3. And
The sense amplifier 8 detects whether or not a current flows through the memory cell to obtain read data "1" and "0".

In the nonvolatile semiconductor memory device according to this embodiment, the input data from the I / O line is fetched and latched, and the program voltage is supplied to each bit line based on the write control signal. Since it has a plurality of latch circuits and the X decoder selects a word line and connects the source line of the memory cell on the selected word line to the source line switch, it corresponds to the selected word line. After erasing only the memory cells, the write information can be collectively written to the memory cells on the selected word line based on the write information latched by the latch circuit, and all the memory cells can be erased. Instead, information can be rewritten in memory cells in word line units.

FIG. 2 is a diagram showing in detail the circuit configuration of the memory array of the flash EEPROM and its peripheral portion according to the second embodiment of the present invention. In the figure, the same symbols as those in FIG. 8 and FIG. The corresponding part is shown. 4 is a diagram showing a circuit configuration of the X decoder shown in FIG. 2. In the figure, 70 and 71 are P channel transistors, 72 is an N channel transistor, and 73 is a NAN.
D gate, Vdec is a power supply voltage for the decoder, and Vneg is a negative voltage power supply. When writing and erasing, V
pp, Vcc at the time of reading, each verify voltage at the time of write / erase verify is supplied from the decoder power supply voltage Vdec, and the negative voltage power supply Vneg.
Is normally supplied with a ground potential, and is supplied with a negative high voltage at the time of erasing. Normally, the decoder power supply voltage is output to the word line selected by the address signal through the output node X, and at the time of erasing, by the address signal. A high negative voltage is output to the selected word line through the output node X. Here, the entire device configuration other than that shown in FIG. 1 is basically the same as that of the conventional flash EEPROM shown in FIG.

Next, the operation of this flash EEPROM will be described in the case where the memory cell for one word line surrounded by the dotted line in the figure is rewritten by using the page programming function.

The memory cell is rewritten by latching the write information and its address, writing "0" regardless of the write information to prevent overerasure, erasing, and writing the write information. It can be divided into periods.

First, the Y gate transistors 2a, 2b, 2c are sequentially selected through the Y decoder 5 by the address signal, and the write information for 11 word lines WL is fetched and latched by the latch circuit 22 (22a, 22b, 22c). It The address register 6 includes a latch circuit, and the address signal input last is latched.

Writing of "0" is performed as follows. That is, the word line WL1 is selected through the X decoder 25 (through the output node X) by the address signal latched in the address register 6, and the word line WL1 is selected.
1 is supplied with Vpp. Then, each latch circuit 22
Write pulse signal P input to a, 22b, and 22c
RO0 becomes “H” at the same time or sequentially and latch circuit 2
The program voltage is simultaneously or sequentially supplied to the bit lines BL1, BL2, BL3 regardless of the write information latched in 2 (22a, 22b, 22c). At this time, the write signal PRO is fixed at "L", and the source 2
1 is grounded. As a result, a current flows through all the memory cells for one word line surrounded by the dotted line in the figure, hot electrons are generated, and the threshold voltage of the memory cell is increased.

Erasing is performed as follows. First,
Since the erase control signal ERSM becomes "H" during erase,
The output Y of the Y decoder 5 is grounded regardless of the address signal, and the drain 19 of each memory cell is opened.
Then, the word line WL1 is selected by the address signal latched in the address register 6 through the X decoder 25 (through the output node X), and the word line WL1 is selected.
Is supplied with a negative high voltage from the negative voltage power source Vneg. At this time, the source line 21 is grounded. As a result, the tunnel phenomenon causes the electrons in the floating gate 16 of each memory cell corresponding to the word line WL1 to be withdrawn, and the threshold value is shifted to the lower side for erasing.

Writing is performed as follows. First, the word line WL1 is selected and Vpp is supplied through the X decoder 25 (through the output node X) by the address signal latched in the address register 6. And
If the write pulse signals PRO input to the respective latch circuits 22a, 22b, 22c simultaneously or sequentially become "H" and the write information latched by the respective latch circuits 22a, 22b, 22c is "0", the latch circuit is The program voltage is supplied to the connected bit lines BL simultaneously or sequentially. At this time, the write signal PRO0 is fixed at "L". Further, the source line 21 is grounded. As a result, current flows only in the memory cell to be written among the memory cells for one word line surrounded by the dotted line in the figure, hot electrons are generated, and the threshold voltage of the memory cell is increased.

Next, the read operation of the memory cell surrounded by the dotted line in FIG. 2 will be described. The address signal is decoded by the Y decoder 5 and the X decoder 25, and the selected Y gate 2a and word line WL1 become "H".
Since the control signal / OE becomes "L" during reading, the bit line BL is directly connected to the Y gate transistor 2 in the latch circuit 22 (22a, 22b, 22c).
Further, the source line 21 is grounded. Then, the sense amplifier 8 reads whether or not a current flows through the memory cell to obtain read data “1” and “0”.

In the nonvolatile semiconductor memory device according to this embodiment, the input data from the I / O line is fetched and latched, and the program voltage is supplied to each bit line based on the write control signal. Since the X decoder has a plurality of latch circuits and is configured to select a word line and supply a high negative voltage to the selected word line, only the memory cell corresponding to the selected word line is selected. After erasing, the write information can be collectively written to the memory cells on the selected word line based on the write information latched by the latch circuit, and the word line can be written without erasing all the memory cells. Information can be rewritten on a unit memory cell.

The flash EEPROM of the above embodiment
In the above, the block diagram showing the entire configuration is basically the same as that of the conventional flash EEPROM shown in FIG. 6 as described above, and the circuit configuration other than the above-mentioned memory array and its peripheral portion is as necessary. It goes without saying that various changes can be made.

[0041]

As described above, the flash EE according to the present invention is used.
According to the PROM, a latch circuit for page programming is provided for each bit line, and a source line connecting a memory cell on a word line selected by an address signal is changed to a source line switch based on the address signal. Since connection is made possible, page programming can be performed after selectively erasing the write information of the memory cell on the word line including the memory cell to be rewritten, so it is necessary to write to all the memories. This has the effect of significantly reducing the rewriting time.

The flash EEP according to the present invention
According to the ROM, a latch circuit for page programming is provided for each bit line, and a negative high voltage can be supplied from the X decoder to the word line selected by the address signal. Therefore, rewriting should be performed. Since page programming can be performed after selectively erasing the write information of the memory cells on the word line including the memory cells, it is not necessary to write to the entire memory, and the rewrite time can be significantly shortened. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a flash EEPR according to an embodiment of the present invention.
The figure which showed the memory array of OM, and its peripheral part in detail.

FIG. 2 is a flash EEP according to another embodiment of the present invention.
FIG. 3 is a diagram showing in detail a ROM memory array and its peripheral portion.

FIG. 3 is a diagram showing a circuit configuration of an X decoder of the flash EEPROM shown in FIG.

FIG. 4 is a diagram showing a circuit configuration of an X decoder of the flash EEPROM shown in FIG.

5 is a diagram showing a circuit configuration of a latch circuit of the flash EEPROM shown in FIG.

FIG. 6 is a block diagram of a conventional flash EEPROM.

FIG. 7 is a cross-sectional view of the memory cell shown in FIGS.

FIG. 8 is a diagram showing in detail a memory array of a conventional flash EEPROM and its peripheral portion.

9A and 9B are flowcharts of operations including a verify operation of the flash EEPROM of FIG. 8, FIG. 8A is a flowchart for erasing, and FIG. 8B is a flowchart for programming.

10 is a timing waveform chart corresponding to the flowchart of FIG. 9, FIG. 7 (a) is a diagram corresponding to FIG. 8 (a), and FIG.
(b) is a view corresponding to FIG. 8 (b).

11 is a diagram showing a circuit configuration of an X decoder and a Y decoder of the flash EEPROM shown in FIG.

12 is a diagram showing a circuit configuration of a source line switch of the flash EEPROM shown in FIG.

[Explanation of symbols]

1 Memory Cell 2a, 2b, 2c Y Gate Transistor 3 Source Line Switch 4 X Decoder 5 Y Decoder 6 Address Register 7 Input Data Register (Write Circuit) 8 Sense Amplifier 9 Input / Output Buffer 10 Program Voltage Generating Circuit 11 Verify Voltage Generating Circuit 12 Command register 13 Command data 14 Input signal buffer 15 Semiconductor substrate 16 Floating gate 17 Control gate 18 Source diffusion region 19 Drain diffusion region 20 I / O line 21,21a, 21b, 21c Source line 22a, 22b, 22c Latch circuit 23a, 23b , 23c X gate 24 X decoder 25 X decoder 30, 32, 39, 41 P-channel transistor 31, 33, 34, 37, 38, 40, 42 N-channel transistor 5 inverter 36,73 NAND gate 43,64,65 inverter 51,53,55,59,60~62,69,72 N
Channel transistor 63, 67, 68, 70, 71 P channel transistor BL1, BL2, BL3 Bit line WL1, WL2, WL3 Word line Vdec Power supply voltage for decoder ERSM Erase control signal Y Y Decoder output node X, X 'X Decoder decoder Output node DL (/ DL) Latch signal PR / O (/ PR / O) Write signal OE (/ OE) Read control signal Vneg Negative voltage power supply

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[Procedure amendment]

[Submission date] June 17, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

FIG. 7 is a diagram showing a cross section of a memory cell in the memory array 1 of FIG. 6, in which 15 is a semiconductor substrate, 16 is a floating gate, 17 is a control gate, and 18 is formed on the semiconductor substrate 15. The source diffusion region 19 is a drain diffusion region formed on the semiconductor substrate 15. Here, floating gate 16
A thin oxide film (film thickness: about 100 angstroms) (not shown) is formed between the semiconductor substrate 15 and the semiconductor substrate 15, and thereby the tunneling phenomenon is utilized to make the floating diffusion from the floating gate 16 to the source diffusion region 18 The electrons can be moved to.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

FIG. 5 is a circuit diagram of the latch circuit (LA
1, LA2, LA3) 22a, 22c, 22b, and 51, 53, 55, 5 in the figure.
9, 60, 61, 62 are N-channel transistors, 5
2, 54, 56, 57, 58 and 63 are P-channel transistors, 64 and 65 are inverters, and DL (/ D
L) indicates a latch signal, P RO (/ P RO ), P RO 0 indicate a write signal, and OE (/ OE) indicates a read control signal. Then, when the latch signal DL becomes "H", I
Input data is taken in from the / O line 20 and the latch signal D
When L becomes "L", the input data taken in is held. Further, when the write signal PRO becomes "H", the held input data is taken out, and if the taken input data is "0", the program voltage is supplied to the bit line BL. Further, when the write signal PRO0 goes "H", the program voltage is supplied to the bit line BL regardless of the held input data. Further, the control signal / OE is "L", that is, the bit line BL is directly connected to the Y gate transistor 2 at the time of reading.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

The writing of "0" is performed as follows. That is, through the X-decoder 24 by A <br/> de-less signal latched in the address register 6 (through the output node X) word line WL1 is selected, the word line WL
1 is supplied with Vpp. Then, each latch circuit 22
Write pulse signal P input to a, 22b, and 22c
RO0 becomes “H” at the same time or sequentially and each latch circuit 2
The program voltage is supplied to the bit lines BL1, BL2, BL3 simultaneously or sequentially regardless of the write information latched in 2a, 22b, 22c. At this time, the write signal PRO is fixed to "L". In addition, the X decoder 24 receives the address signal latched in the address register 6.
The X gate 23a is selected via (through the output node X '), and the source line 21a is grounded by the source line switch 3. As a result, the word line 1 surrounded by the dotted line in the figure
A current flows through all the memory cells for this line, hot electrons are generated, and the threshold voltage of the memory cells is increased.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/792 H01L 29/78 371

Claims (2)

[Claims] 1. A plurality of memory cells arranged in a matrix in the row and column directions, and a plurality of bit lines each connected to the drains of the memory cells arranged in corresponding columns of the plurality of memory cells. , A plurality of word lines each connected to a control gate of a memory cell arranged in a corresponding row of the plurality of memory cells, and a source of memory cells arranged in a corresponding row of the plurality of memory cells A plurality of source lines connected to the source line, a source line switch for grounding the source line or applying a high voltage to the source line, and an address signal input from the outside to decode the bit. Y decoders for selecting a line, and a Y decoder provided for each of the bit lines corresponding to the plurality of bit lines. A plurality of Y gate transistors input to the gate, an X decoder for decoding an address signal input from the outside, and selecting the word line, and an X decoder for each bit line corresponding to the plurality of bit lines. A plurality of latch circuits which are provided corresponding to the input data from the I / O lines and latch the data and supply a program voltage to each bit line based on a write control signal. X-gates, which are provided for respective source lines corresponding to the plurality of source lines and which selectively receive the output of the X-decoder and connect the source lines to the source-line switch. A source line of a memory cell on a word line selected by the X decoder, High voltage is applied from the switch, the flash EEPROM, characterized in that information of the word line of the memory cell is erased. 2. A plurality of memory cells arranged in a matrix in the row and column directions, and a plurality of bit lines each connected to the drains of the memory cells arranged in corresponding columns of the plurality of memory cells. , A plurality of word lines each connected to a control gate of a memory cell arranged in a corresponding row of the plurality of memory cells, and a plurality of memory cells arranged in a corresponding row of the plurality of memory cells, A plurality of source lines connected to the sources, a Y decoder for decoding the address signal input from the outside and selecting the bit line, and a Y decoder for decoding the address signal input from the outside to select the word line X-decoders for performing the above, and each of them is provided for the corresponding bit line of the plurality of bit lines, and takes in the input data from the I / O line. And a latch circuit that supplies a program voltage to each bit line based on a write control signal and performs writing by page programming, wherein the X decoder is a negative voltage power supply. And the source line is grounded, a negative high voltage is applied from the negative voltage power source to the word line selected by the X decoder, and information of the memory cell on the selected word line is Flash EEPRO characterized by being erased
M.