JPH0514397A - Route distributing switch for atm cell - Google Patents

Abstract

PURPOSE:To prevent the extension of the buffer length and the increase of the internal processing speed in an ATM cell route distributing switch which outputs cells from plural input lines to one desired output line by the ATM transmission system. CONSTITUTION:Numbers of cells staying in buffers where cells are allowed to stay correspondingly to respective input lines INHW of switch elements SW-11 to SW-NN are monitored by an entire read control part CNT and are compared with plural thresholds to read out cells from buffers in the order from the buffer where the number of staying cells exceeds the larger threshold.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM cell route allocating switch, and more particularly to an ATM cell route allocating switch in an ATM cross-connect device.

Recently, research on ATM (Asynchronous Transfer Mode) networks has been actively conducted as a technology for realizing a high-speed / broadband integrated network (B-ISDN) aiming at a wide range of multimedia services. Is a cell format composed of a header part (5 bytes) and a payload part (48 bytes), which unifies all information and asynchronously transmits a path between many nodes, that is, an ATM cross-connect device. (Synch
ronous Transfer Mode: Synchronous transfer technology) Compared to the network, the time-slot allocation process is less laborious, so it is suitable for distributed processing control, and flexible multiplex transmission is possible.

In such an ATM network, a link (high-speed transmission line) is provided between each cross-connect device.
Further, an allocation route (path) called a VP (Virtual Path) is set between an arbitrary pair of terminal devices (CPE) indicated by the same number.

In order for a cell to flow through a desired VP in such a network, a 12-bit VPI (Vir (Vir) is used for identifying the VP in the header of the cell.
tualPath Identifier) is provided, and a map showing the correspondence between the cross-connect information and the VPI for setting the VP in each cross-connect device is prepared so that a different VPI value is set for each link. In each cross-connect device, cells are distributed by looking at this VPI.

Therefore, such cell allocation is
Since it is related to the operation speed of the TM cross connect device, it is necessary to perform it as efficiently as possible.

[0006]

2. Description of the Related Art FIG. 9 shows a conventionally known ATM.
A cross-connect device is shown, a terminal device or an AT
An input cell from the M cross-connect device is multiplexed (MU
X) 3 multiplexes into N cells, and the VPI converters 1 ₁ to 1 _N respectively set the VPI of each cell to VP for the next link
It is rewritten to I and sent to the input line of the switch 2 corresponding to the rewritten VPI. In the switch 2, the cells are distributed from the corresponding output line based on the header information of each cell and output, and the cells from this output line are separated (DMU).
X) 4 is separated and sent to the link or communication device to the adjacent ATM cross-connect device.

FIG. 10 shows each of the above VPI converters 1 ₁ to ₁ .
A configuration example of 1 _N is shown, and when the header information (12 bits) of the input cell is sent to the VPI table 11, this table 11 converts it into a new VPI and, together with other data that has passed through the delay unit 12, The combined result is output by the selector (SEL) 13.

FIG. 11 shows an example of the configuration of the switch 2 described above, in which N input lines and N output lines are connected to N lines.
^Two buffer memories (eg FIFO memory) BM ₁₁
To BM _NN are used to form a matrix, and VPI determination units JD _{11 to} JD _{NN in the} cell are provided at each cross point. Then, in the determination units JD _{11 to} JD _NN , the corresponding output line is detected based on the VPI of the cell from the input line, and the cross point corresponding to the VPI is controlled by the write control from the control unit (not shown). The cell is once written into the buffer memory, and the read cells are read out from the controller in a predetermined order and output from the corresponding output line.

[0009]

In such an ATM cell route distribution switch, in order to prevent cell discarding even in the case of bursty incoming traffic, the buffer of each buffer is It is necessary to increase the length, and if the buffer length is increased, there is a problem in that the hardware scale and power consumption increase.

As a method of shortening the buffer length, a method of sharing a buffer with a plurality of input lines and output lines is known. In this case, the internal signal processing speed is increased or I need a multi-port memory,
The size of the device becomes large and the cost becomes high.

Therefore, according to the present invention, in the ATM cell route allocating switch for outputting cells from a plurality of input lines to one desired output line by the ATM transmission method,
The purpose is not to lengthen the buffer length and increase the internal processing speed.

[0012]

FIG. 1 conceptually shows the structure of a switch for allocating a route of an ATM cell according to the present invention. In the present invention, a cell corresponding to each input line is provided. Switch element SW that includes a buffer that retains
-11 to SW-NN, and the total read control unit CNT that monitors the number of cells staying in the buffer, compares them with a plurality of thresholds for the number of cells, and sequentially reads cells from the buffer that exceeds the larger threshold. I have it.

Therefore, the switch elements SW-11 to SW-N
While the ATM cells corresponding to the buffers respectively included in N are accumulated, the total read control unit CNT constantly monitors the number of cells retained in each buffer, and the total number of retained cells is adjusted to some number. Compare with threshold.

As a result, the overall read control unit CNT does not need to use an unnecessarily long buffer length by reading the ATM cells in order from the buffer that exceeds the larger threshold value. Become.

Further, in the present invention, in the above case,
When the total read control unit CNT has a plurality of buffers that exceed each threshold value, cells are read sequentially among those buffers, and when the number of read cells at one threshold value exceeds a predetermined number, the threshold value below that threshold value is set. It is possible to read from the buffer at least once. In such a case, even if the number of staying cells is small at the time of monitoring, the number of staying cells may increase during reading. The number of staying cells can be reduced.

Further, according to the present invention, in the above case, the entire read control unit CNT can realize an efficient read operation by skipping the buffer in the empty state and performing the read.

Further, according to the present invention, in the above case, if the whole read control unit CNT weights the cell read frequency with respect to a specific buffer, A from the specific output line can be obtained.
The TM cell is preferentially used for route distribution.

Further, according to the present invention, in the above case, when the entire read control unit CNT has a specific cell insertion request, reading from each buffer is prohibited during the period in which this request is maintained, It is also possible to send the specific cell to the output line.

Further, in the present invention, in the above-mentioned case, the total read control unit CNT defines the maximum continuous effective cell number N _MAX when there is a cell flow rate control request to the output line,
It is also possible to prohibit the reading so that the number of consecutive valid cells to be read does not exceed this maximum value, and by doing so, it is possible to avoid a situation in which each buffer overflows.

[0020]

FIG. 2 shows the switch element SW shown in FIG.
-11 to SW-NN are collectively shown by SW, and in this embodiment, the input line INHW (highway) is used.
Buffer 1 for accumulating data from the input line and A from the input line
TM cell is the output line OUTHW of the relevant switch element SW
To the buffer 1 according to the determination result from the determination unit 2 and the determination result from the determination unit 2 and the write enable signal WE. And a read control signal which will be described later and a write control section 3 which outputs a write pulse WP at the end of writing.
When a read from the buffer 1 is requested by the SWCONT, the read address signal RA and the read enable signal RE are given to the buffer 1 and a read control unit 4 that generates a read pulse RP at the time of reading, and the read control unit 4 Counts up by the selector (SEL) 5 that allows the cell read from the buffer 1 to pass or the cell from the extended input from another switch element above and the write pulse WP from the write control unit 3 according to the instruction. A counter 6 for counting and outputting the staying cell number a of the buffer 1 by counting down by the read pulse RP from the read control unit 4.
And a decoder 7 for receiving the counted number of cells a and judging to which range the number of cells a belongs by comparing with a plurality of threshold values. The thresholds of the decoder 7 are, for example, a level EMP indicating a vacancy and an EM
A level X1 equal to or higher than P and a level X2 higher than X1 are used. The output signal of the decoder 7 is a <1,
It may be divided into three signals of 1 ≦ a <X1 and X1 ≦ a <X2, and may be output by corresponding signal lines, or a <1,1
The four determination results of ≦ a <X1, X1 ≦ a <X2, X2 ≦ a may be output in 2 bits.

FIG. 3 shows the entire read control unit CNT shown in FIG.
In this embodiment, assuming that there are eight switch elements SW-11 to SW-NN, the buffer level EMP from each decoder 7 in the switch elements SW-1 to SW-8, Latch circuit 11-1 for latching X1 and X2
~ 11-8 and a latch circuit 120 for collecting and latching the buffer levels latched by the latch circuits 11-1 to 11-8 by collecting switch elements SW-1 to SW-8 for each level EMP, X1 and X2. To 122 and these latch circuits 120 to 1
The read control signal generator 13 for generating the read control signal SWCONT from 22 in order of increasing level, and the read pulse when the highest level X2 is read are counted and the control signal is given to the generator 13. And a counter 14.

As described above, in the operation of the embodiment shown in FIGS. 2 and 3, when an ATM cell is input to the switch element SW from the input line INHW, the determination section 2 causes the cell to pass through the switch element SW. Output line OUTH
It is determined whether or not it should be output from W, and if it is not, it will be passed through and it will be separately determined by the next switch element, but it should be output from the output line OUTHW. When the determination is made, the write control section 3 sends the write address signal WA and the write enable signal WE to the buffer 1, and the buffer 1 stores the input cell and is output from the write control section 3 at this time. The counter 6 counts up by the write pulse WP.

The buffer 1 is read by a read control signal.
The read control unit 4 receiving the SWCONT gives the read address signal RA and the read enable signal RE to the buffer 1, and the selector 5 also controlled by the read control unit 4 passes through the cell read from the buffer 1. By doing so, the output is outputted from the output line OUTHW. At this time, the read pulse RP is given from the read control unit 4 to the counter 6, so that the counter 6 is counted down.

Accordingly, the counter 6 of the switch element SW always counts and outputs the staying cell number a of its own buffer 1, and the decoder 7 discriminates this and sets it as the respective buffer levels EMP, X1, X2 of FIG. It is given to the entire read control unit CNT.

In this total read control unit CNT, the number of staying cells a of each switch element SW-1 to SW-8 is set to the latch circuit 11-1.
To 11-8, and latch circuits 120, 121 and 122 for each level EMP, X1 and X2 to latch the retained cell number a of each switch element SW-1 to SW-8 and then read control signal. It is given to the generating unit 13.

Therefore, the generation unit 13 can perform the following processing, for example. First, when there is a switch element in which the number of staying cells a exceeds the threshold value X2, in order to specify the switch element, one of the eight parallel signals is set to the “H” level. When there are a plurality of such switch elements, a signal designating the switch elements is output in a predetermined order. Then, after the cell reading of the buffer of the switch element for the threshold value X2 is executed, the threshold value X1 is similarly read. However, for example, when the cell reading at the threshold value X2 has continued for a predetermined number of N1 times, the buffer of any switch element of the threshold value X1 below it is controlled by the control signal from the counter 14 which counts it as shown in FIG. The cell is read from.
The control signal SWCONT for reading is not sent to the empty level EMP buffer.

In this way, the read control signal SWCONT is sent from the entire read control unit CNT to each switch element SW.

FIG. 4 shows an embodiment in which a certain switch element is weighted, and the read control signal generator 13 is the same as that shown in FIG. 3, so that its input signal also has a threshold value. It is the number a of retained cells of the switch element group for each of EMP, X1, and X2. However, in this embodiment, since the reading of the switch element SW-1 is performed with priority, the read control signal generating unit 13 has the switch element SW-1.
-2 to the number of retained cells from SW-8 are given.

The accumulated cell number a of the switch element SW-1 is latched by the latch circuit 11-1, and the latch output and the read control signal SWCONT for designating the switch element from the read control signal generating section 13 are respectively ANDed. Gate
15-1 to 15-8 are logically ANDed with the weighted signal. However, in this case, the weighting signal to the AND gate 15-1 is inverted and given.

Therefore, normally, the weighting signal in which the "H" level and the "L" level alternate is the AND gate 15.
-1 to 15-8, as shown in FIG. 5, during the "L" level period A, only the AND gate 15-1 is enabled and the staying cell number a of the switch element SW-1 is read controlled. The signal SWCONT is preferentially output to the switch element SW-1, and in the "H" level period B, the read control signal SWCONT for the switch elements SW-2 to SW-8 is generated.

As shown in FIG. 5, when the number of staying cells of the switch element SW-1 is an empty EMP, the period A shown in the figure is changed from the "L" level shown by the dotted line to the "H" level shown by the solid line. When the number of accumulated cells of the switch elements SW-2 to SW-8 is an empty EMP, the period B shown in the figure is changed from the “H” level indicated by the dotted line to the “L” level indicated by the solid line, thereby eliminating waste for the empty switch elements. Read access operation can be omitted.

FIG. 6 shows an embodiment in which a special cell including an empty cell is inserted. As shown in the figure, if a special cell occurs in a certain switch element SW, this special cell is inserted. A special cell insertion request signal defining a period is given to the overall read control unit CNT, which causes the overall read control unit CNT to output the output signal of the read control signal generation unit 13 to AN.
It can be prohibited by the D gate, and during this prohibition period, the special cell passes through the switch element SW and is output to the output line.

FIG. 7 shows an embodiment in the case where there is a cell flow rate control request to the output line in the entire read control unit CNT. In this embodiment, the read control signal generator 13 shown in FIG. The 8-bit parallel output read control signal SWCONT is counted by the up counter 22 via the OR gate 21 and is set so that the carry output of the up counter 22 is generated at the maximum number of consecutive effective cells N _MAX. When the output reaches the maximum number of consecutive effective cells N _MAX by passing through the inverter 23 and the AND gate 24, the read control signal SWCONT is set to all "0" to forcibly prohibit the reading. In addition, the reset of the counter 22
Reading is performed by way of a NOR gate 25 that receives the read control signal SWCONT, and an AND gate 26 that inputs the output signal of the NOR gate 25 and a cell pulse that defines the reading period of one cell as shown in the time chart of FIG. This is performed when the 8-bit parallel signal from the control signal generator 13 is all "0".

[0034]

As described above, according to the ATM cell route allocating switch according to the present invention, the total number of cells retained in the buffer for retaining the cells corresponding to each input line in each switch element is read out as a whole. Since it is configured to read the cells in order from the buffer that exceeds the larger threshold by comparing with a plurality of thresholds for the number of cells monitored by the unit,
It is possible to efficiently perform read control from a plurality of buffers in which cells to be output to one output line are accumulated,
In particular, it is possible to avoid the cell discard that occurs because the buffer length is limited. In addition, A coming in burst
The buffer length required for the TM cell can be reduced, and the hardware and power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of an ATM cell route distribution switch according to the present invention.

FIG. 2 is a block diagram showing an embodiment of each switch element used in the ATM cell route distribution switch according to the present invention.

FIG. 3 is a diagram showing an embodiment of an entire read control unit used in a route distribution switch for ATM cells according to the present invention.

FIG. 4 is a block diagram showing a modification of the entire read control unit used in the present invention.

5 is a waveform diagram of a weighting control signal used in the embodiment of FIG.

FIG. 6 is a block diagram showing an embodiment when inserting a special cell in the present invention.

FIG. 7 is a circuit diagram showing an embodiment of an entire read control unit when a cell flow rate is limited in the present invention.

8 is a time chart diagram for explaining the operation of the embodiment in FIG. 7. FIG.

FIG. 9 is a block diagram showing a general configuration of an ATM cross-connect device of the present invention and a conventional example.

FIG. 10 is a block diagram showing a configuration of a general VPI conversion unit used in an ATM cross connect device.

FIG. 11 is a block diagram showing a configuration of a switch for allocating routes of ATM cells in a conventional example.

[Explanation of symbols]

SW-11 to SW-NN switch element CNT whole read control unit INHW input line OUTHW output line In the drawings, the same reference numerals indicate the same or corresponding parts.

Continuation of front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location 9076-5K H04Q 11/04 E (72) Inventor Ryuichi Kondo 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (72) Inventor Takaaki Wakisaka 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor Toshiyuki Sudo 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited

Claims (6)

[Claims] 1. A switch for routing ATM cells, which outputs cells from a plurality of input lines to a desired one output line by an ATM transmission system, has a buffer for retaining the cells corresponding to each input line. Switch element (SW-11 to SW-NN) that includes it, and monitors the number of cells staying in the buffer, compares it with multiple thresholds for the number of cells, and sequentially reads cells from the buffer that exceeds the larger threshold. A switch for allocating routes of ATM cells, characterized by comprising a control unit (CNT). 2. When the total read control unit (CNT) has a plurality of buffers that exceed each threshold value, cells are sequentially read between the buffers and a predetermined number of cells are read at one threshold value. 2. The ATM cell route allocating switch according to claim 1, wherein when it exceeds the threshold value, reading is performed at least once from a buffer having a threshold value equal to or lower than the threshold value. 3. The switch for allocating routes of ATM cells according to claim 1, wherein the entire read control unit (CNT) skips a buffer in an empty state to perform reading. 4. The overall read control unit (CNT) according to claim 1, wherein the cell read frequency is weighted for a specific buffer. ATM cell route distribution switch. 5. When the entire cell read control unit (CNT) has a specific cell insertion request, it prohibits reading from each buffer during the period when this request is maintained, 5. The ATM cell route distribution switch according to claim 1, wherein a specific cell is transmitted. 6. The total read control unit (CNT) defines the maximum number of consecutive effective cells (N _MAX ) when there is a cell flow rate control request to the output line, and 6. The ATM cell route allocating switch according to claim 1, wherein reading is prohibited so that the maximum value is not exceeded.