JPH05133766A - Encoder interpolation device - Google Patents

Abstract

PURPOSE:To generate sensing signals of high accuracy by controlling the counting operation of two up/down counters, allowing assumed Lissajous signals to follow up after two real Lissajous signals having 90 deg. differing phases, reading interpolation data from a memory means using the assumed Lissajous signals as address, and interpolating the output of encoder. CONSTITUTION:Two Lissajous signals having 90 deg. differing phases emitted from an encoder are converted into digital signals by A/D convertoors 1, 2 and supplied to comparators 3, 4 as real Lissajous signal. The outputs of up/ down counters 5, 8 are fed as assumed Lissajous signal to one of the comparators 3, 4, and the two are compared. AND gates 6, 9 supply signals to other AND gates 7, 10 depending upon the result from comparison, and thereby the operation of the counters is controlled, and the assumed Lissajous signals are left following up after the real Lissajous signals. These assumed Lissajous signals are fed to a ROM 11 as address signals, and corresponding data is obtained. This, way permits interpolation of the encoder output accurately at all times, which leads to precise sensing of the displacement and velicity of the object.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoder interpolation device.

[0002]

2. Description of the Related Art Conventionally, a resistance division method, a phase modulation method and the like have been known as interpolation methods for increasing the resolution of an encoder. However, in the resistance division method,
With high interpolation, there is a problem that the number of division resistors and the number of comparators for binarization increase and the circuit scale increases, and there is a problem that erroneous detection occurs due to variations in division resistors and comparators. Further, in the phase modulation method, since the time from zero-cross to zero-cross of the phase-modulated wave is measured, the real-time property is poor and there is a problem in applying it to high-speed, high-precision control.

As an interpolation method for solving such a problem, for example, JP-A-2-38814 and JP-A-2-186.
In Japanese Patent No. 221, the ROM in which the phase angle data corresponding to the sine component and the cosine component is stored in advance is used, and the sine component (A phase) and the cosine component (B phase) with different 90 ° phases from the encoder are used as address signals. It has been proposed to read corresponding phase angle data from a ROM.

[0004]

However, in the interpolation method disclosed in the above publication, if the sine component or cosine component from the encoder has a noise component, the object to be measured is actually measured. Even if is not displaced, the address component abruptly changes due to the noise component, and an incorrect phase angle is output. Therefore, in order to detect the displacement amount and speed of the object to be measured, the up / down counter is operated based on the phase angle data from the ROM,
When the phase and B phase are created, the displacement direction of the object to be measured cannot be discriminated due to the abrupt change of the phase angle due to the noise component, and the up / down counter and the A phase and B phase creation circuit malfunction. However, there is a problem that an accurate detection signal cannot be obtained for a while.

The present invention has been made by paying attention to such conventional problems, and is not affected by noise or the like.
An object of the present invention is to provide an encoder interpolating device that is appropriately configured so as to always obtain a highly accurate detection signal.

[0006]

In order to achieve the above object, according to the present invention, there are provided two up / down counters which respectively output virtual Lissajous signals corresponding to two real Lissajous signals having different 90 ° phases from an encoder. , Two comparing means for comparing each virtual Lissajous signal from these up / down counters with the corresponding real Lissajous signal, and the virtual Lissajous signal follows the corresponding real Lissajous signal based on the output of each comparing means. As described above, the two up / down counters are provided with two control means for independently controlling the counting operation of the up / down counter and a storage means for preliminarily storing interpolation data.
Using the virtual Lissajous signal output from the down counter as an address, the interpolation data is read from the storage means and the output of the encoder is interpolated.

[0007]

In this structure, 90 ° from the encoder
The real Lissajous signals having different phases are compared with the virtual Lissajous signals from the corresponding up / down counters in the respective comparing means, and each virtual Lissajous signal follows the corresponding real Lissajous signal based on the comparison. The counting operation of the up / down counter is controlled by the corresponding control means, and the interpolation data stored in advance in the storage means is read by using the virtual Lissajous signal from these up / down counters as an address.

[0008]

FIG. 1 shows a first embodiment of the present invention. In this embodiment, analog A-phase and B-phase Lissajous signals having different 90 ° phases from the encoder are
The A / D converters 1 and 2 convert the signals into digital signals, and the outputs of the A / D converters 1 and 2 are supplied as real Lissajous signals dA and dB to one input terminal A of the comparators 3 and 4, respectively. .. To the other input terminal B of the comparator 3, the output of the up / down counter 5 is supplied as a virtual Lissajous signal dA ', and here the input terminal A
The signals supplied to B and B are compared with each other, and when A <B, one input terminal of the AND gate 6 and when A> B, A
A high level signal is supplied to one input terminal of the ND gate 7. A clock signal is supplied to the other input terminals of the AND gates 6 and 7, respectively, and AN
The output of the D gate 6 is supplied as a down signal and the output of the AND gate 7 is supplied as an up signal to the up / down counter 5, and the output dA ′ of the up / down counter 5 is supplied from the A / D converter 1. Follow dA.

Similarly, the output of the up / down counter 8 is supplied to the other input terminal B of the comparator 4 as a virtual Lissajous signal dB ', and the signals supplied to the input terminals A and B are compared here. , A <B, the AND gate 10 is supplied with a high level signal when A> B, and the AND gate 10 is supplied with a high level signal.
The count operation of the down counter 8 is controlled so that the output dB 'of the up / down counter 8 follows the dB from the A / D converter 2.

Up / down counters 5 and 8
The outputs dA 'and dB' of the
Supply to M11. The ROM 11 stores the A-phase and B-phase signals, the vector length, and the vector length divided corresponding to the desired interpolation number, corresponding to the A-phase and B-phase real Lissajous signals (digital signals dA and dB). Data indicating an error when the value is out of the normal value range is stored in advance, and the address signals dA ′ and dB ′ from the up / down counters 5 and 8 are stored.
Causes the corresponding data to be output.

According to this embodiment, in the comparators 3 and 4, the outputs dA and dB of the A / D converters 1 and 2 and
While comparing the outputs dA ′ and dB ′ of the down counters 5 and 8, respectively, the counting operation of the up / down counters 5 and 8 is controlled so that dA ′ and dB ′ follow dA and dB, respectively. Since the output of the encoder is interpolated by using the change of ′ and dB ′, the noise component of the A phase signal or B phase signal from the encoder causes RO
Even if the address signal dA 'or dB' of M11 changes suddenly, the direction of the change can be easily determined, and by making dA 'follow dA and dB' follow dB, respectively, It can have a kind of filtering effect that cuts the components. Therefore, the output of the encoder can always be accurately interpolated with high resolution and hardly affected by the abrupt change of the Lissajous signal due to the noise component, and the displacement amount, speed, etc. of the object to be measured are always highly accurate. Can be detected with.

FIG. 2 shows a second embodiment of the present invention. This embodiment uses 9 from the encoder in FIG.
It is designed to process analog A-phase and B-phase real Lissajous signals having different 0 ° phases without converting them into digital signals, and those having the same operation as those shown in FIG. However, the description is omitted. The analog A-phase and B-phase real Lissajous signals from the encoder having different 90 ° phases are amplified by amplifiers 12 and 13, respectively, and their outputs A and B are input to one input terminals of differential amplifiers 14 and 15, respectively. Supply.

A virtual Lissajous signal dA from the up / down counter 5 is applied to the other input terminal of the differential amplifier 14.
Is converted into an analog signal A _I by the D / A converter 16 and supplied, and the output A-A _I of the differential amplifier 12 is supplied to one of the input terminals of the comparators 17 and 18, respectively. In the comparator 17, the output A− of the differential amplifier 12
By comparing A _I with the reference value V _TH , as shown in the waveform diagram of FIG. 3A, when A−A _I > V _TH , a low level signal as shown in FIG. 3B is input to one input of the gate circuit 19. Supply to the terminal. In the comparator 18, the output A-A _I of the differential amplifier 12 is compared with the reference value -V _TH, and the output is inverted by the inverter 20, so that A-A _I <-V _TH
At this time, a low-level signal as shown in FIG. 3C is supplied to one input terminal of the gate circuit 21.

A clock signal is supplied to the other input terminal of each of the gate circuits 19 and 21, and the clock signal is supplied to one input terminal of each of the gate circuits 19 and 21 as shown in FIGS. 3D and 3E, respectively. When it is at a low level, it is passed and the output of the gate circuit 19 (see FIG.
D) is supplied as a down signal and the output of the gate circuit 21 (FIG. 3E) is supplied as an up signal to the up / down counter 5. In this way, the output A _{I of} the D / A converter 16, that is, the virtual Lissajous signal dA ′ of the up / down counter 5 is made to follow the actual Lissajous signal A.

Similarly, the virtual Lissajous signal dB 'from the up / down counter 8 is converted into an analog signal B _I by the D / A converter 22 and supplied to the other input terminal of the differential amplifier 15. The outputs B-B _I of the differential amplifier 15 and the reference values V _TH and -V _TH are compared with the comparators 23 and 24.
Compare each with. From the comparator 23, BB
_{When I} > V _TH , a low-level signal is supplied to one input terminal of the gate circuit 25, and the comparator 24 outputs B
When −B _I <−V _TH , a low level signal is supplied to one input terminal of the gate circuit 27 via the inverter 26. Thus, when the output of the comparator 23 is low level, the clock signal passing through the gate circuit 25 is used as a down signal, and when the output of the inverter 26 is low level, the clock signal passing through the gate circuit 27 is changed. It is supplied to the up / down counter 8 as an up signal, whereby the output B of the D / A converter 22 is supplied.
_I, that is, the virtual Lissajous signal dB ′ from the up / down counter 8 is made to follow the actual Lissajous signal B.

In this way, the outputs A-A _I ; B-B _I of the differential amplifiers 14; 15 are compared with the comparators 17, 18;
By comparing the virtual Lissajous signals dA ′; dB ′ from the up / down counters 5; 8 with the actual Lissajous signals A; B by comparing with the reference values V _TH and −V _{TH at 3} and 24, respectively, noise components Can be effectively canceled, and the virtual Lissajous signal dA ′; dB ′ can always follow the actual Lissajous signal A; B with an error of 1 LSB.

The virtual Lissajous signals dA 'and dB' from the up / down counters 5 and 8 are supplied to the ROM 11 as address signals in the same manner as in the first embodiment, whereby the corresponding data, that is, the desired interpolation. The A-phase and B-phase signals divided according to the number, the vector length, and the data representing the error when the vector length is outside the normal value range are output.

Also in this embodiment, the virtual Lissajous signal dA output from the up / down counters 5 and 8 is used.
′, DB ′ is the actual Lissajous signal A from the encoder,
Since the output of the encoder is interpolated by using the changes in dA ′ and dB ′, the noise of the A-phase signal and the B-phase signal from the encoder is also used, as in the first embodiment. The output of the encoder can always be accurately interpolated with high resolution, almost without being affected by abrupt changes due to the components.

[0019]

As described above, according to the present invention, each actual Lissajous signal from the encoder and the corresponding up / down
While comparing with the virtual Lissajous signal from the down counter, each up / down counter is controlled so that the virtual Lissajous signal follows the actual Lissajous signal, and the interpolation data is stored from the storage means using each virtual Lissajous signal as an address. Since the signal is read from the encoder, even if the virtual Lissajous signal from the up / down counter changes abruptly due to the noise component of the signal from the encoder, by making the virtual Lissajous signal follow the actual Lissajous signal The output of the encoder can always be accurately interpolated with high resolution without being substantially affected by changes in the actual Lissajous signal, and therefore the displacement amount and speed of the measured object can always be detected with high accuracy. it can. Also, since the interpolation data is stored in the storage means, the number of interpolations can be increased and the number of interpolations can be increased by simply changing the storage pattern in the storage means without increasing the circuit scale. The length and its abnormality can be detected at the same time, and adjustment and maintenance can be facilitated. Further, since the virtual Lissajous signal is made to follow the actual Lissajous signal, it is possible to perform interpolation with good real-time property.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a waveform diagram for explaining the operation of the second embodiment.

[Explanation of symbols]

 1, 2 A / D converter 3, 4 Comparator 5, 8 Up / down counter 6, 7, 9, 10 AND gate 11 ROM 12, 13 Amplifier 14, 15 Differential amplifier 16, 22 D / A converter 17 , 18, 23, 24 Comparator 19, 21, 25, 27 Gate circuit 20, 26 Inverter

Claims (1)

[Claims] 1. Up / down counters for respectively outputting virtual Lissajous signals corresponding to two real Lissajous signals having different 90 ° phases from an encoder and corresponding virtual Lissajous signals from these up / down counters. Two comparing means for comparing the actual Lissajous signal with each other, and the counting operation of the up / down counter is independently controlled so that the virtual Lissajous signal follows the corresponding actual Lissajous signal based on the output of each comparing means. And two storage means for storing the interpolation data in advance. The interpolation data is read from the storage means by using the virtual Lissajous signal output from the two up / down counters as an address. Interpolation of the encoder characterized by being configured to interpolate the output of the encoder Location.