JPH05130068A - Frequency spread modulator - Google Patents

Abstract

PURPOSE:To quicken the signal transmission speed in frequency spread communication. CONSTITUTION:A PN code generating circuit 8 outputs plural PN codes PN1, PN2, PN3, PN4. A signal division circuit 5 divides a signal to be sent, e.g. a 16-bit parallel signal SO into four by 4-bits each, and converts them into serial signals and outputs the result as division signals S1, S2, S3, S4. Primary modulation circuits 11, 21, 31, 41 modulate the division signals S1, S2, S3, S4 by a conventional modulation system such as SSB, PSK, FM to output the result as primary modulation signals S1', S2', S3', S4'. Secondary modulation circuits 12, 22, 32, 42 apply frequency spread modulation to the primary modulation signals S1', S2', S3', S4' by using different PN codes PN1, PN2, PN3, PN4 respectively to output secondary modulation signals M1, M2, M3, M4. An adder circuit 3 adds the secondary modulation signals M1, M2, M3, M4 outputted from the secondary modulation circuits 12, 22, 32, 42 to give the sum to a transmission means such as an antenna. The PN code generating circuit 8 is provided with a PN code generator 6 and a delay circuit 7 delaying the generated PN code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum modulator, and more particularly to a device capable of increasing the speed of signal transmission.

[0002]

2. Description of the Related Art A conventional spread spectrum modulator has a single P
The spread spectrum modulation is performed by one type of M-sequence PN code generated from the N code generation circuit. For example, if the signal to be modulated is a 16-bit parallel signal, it is converted into a serial signal, this serial signal is primary-modulated by the conventional modulation method, and this is subjected to frequency spread modulation by one type of PN code. Met.

Further, Japanese Laid-Open Patent Publication No. 2-299334 discloses a pseudo noise generating means, a plurality of delay elements for shifting the phase of the pseudo noise generating means by an arbitrary different number of bits, and an information signal based on the delay element. There is disclosed a spread spectrum communication system including a selection / encoding means for selecting and outputting outputs from a plurality of delay elements. This is a phase modulation technique of spectrum spread communication in which an information signal is divided into two bits and a pseudo noise code having a different phase is selected according to the input signal.

[0004]

However, even if an attempt is made to transmit a signal at high speed by using the conventional spread spectrum modulation method as described above, a signal faster than the PN code, or P
It was difficult to transmit a signal having a frequency close to the N code frequency. Further, the technique disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 2-299334 is a phase modulation technique of spectrum spread communication in which a pseudo noise code having a different phase is selected according to an input signal, and the phase modulation is performed by a serial signal. The signal is transmitted, and the signal transmission speed is not increased. For example, when using a PN code having a long bit length, the operation becomes very slow.

Therefore, an object of the present invention is to increase the signal transmission speed in spread spectrum communication.

[0006]

SUMMARY OF THE INVENTION In the present invention, a frequency spread modulator is provided with a P that outputs a plurality of different PN codes.
An N code generating circuit, a signal dividing circuit for dividing a signal to be transmitted into a plurality of divided signals, and a plurality of primary modulating circuits for respectively modulating the divided signals and outputting a primary modulated signal,
A plurality of secondary modulation circuits that perform spread spectrum modulation on the respective primary modulation signals by the different PN codes and output as secondary modulation signals are added to the secondary modulation signals output from the respective secondary modulation circuits. And an adder circuit.

Further, the PN code generating circuit has one P
An N code generator and a delay circuit that delays the generated PN code may be provided so as to output a plurality of PN codes that are the same series PN code and have at least one chip phase different from each other.

[0008]

According to the spread spectrum modulator of the present invention, first,
A plurality of different PN codes are generated in the PN code generation circuit. Then, the plurality of divided signals obtained by dividing the signal to be transmitted are each modulated to form a primary modulated signal.
It is output from the next modulation circuit.

At this time, the PN codes supplied to the plurality of secondary modulation circuits which respectively perform the spread spectrum modulation of the respective primary modulation signals and output as the secondary modulation signals, the mutual PN codes generated in the PN code generating circuit. Is subjected to frequency spread modulation by different PN codes and output as a secondary modulation signal,
After being added, they are transmitted by, for example, one transmission means.

Further, when the PN code generated from one PN code generator is delayed by at least one chip with respect to each other by the delay circuit, even if there is one PN code generator, a plurality of apparently different PN codes are generated. can get.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A spread spectrum modulator of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of a spread spectrum modulator for modulating and transmitting a 16-bit parallel signal, and FIG. 2 is an explanatory diagram of a plurality of PN codes.

In FIG. 1, 8 is a plurality of different PN codes.
A PN code generation circuit 5 for outputting PN1, PN2, PN3, PN4 is a signal to be transmitted, for example, a 16-bit parallel signal S0 is 4
A signal division circuit that divides each bit into four and converts each into a serial signal and outputs as divided signals S1, S2, S3, S4, 11, 21, 31, 41 are the divided signals S1, S2, S3, S
The primary modulation circuits, 12, 22, 32, and 42, which modulate 4 by the conventional modulation method such as SSB, PSK, FM, and output as the primary modulation signals S1 ', S2', S3 ', S4', The primary modulation signals S1 ', S2', S3 ',
This is a secondary modulation circuit that frequency-spread modulates S4 'with the different PN codes PN1, PN2, PN3, PN4 and outputs as secondary modulation signals M1, M2, M3, M4.

An adder circuit 3 adds the secondary modulation signals M1, M2, M3, M4 output from the secondary modulation circuits 12, 22, 32, 42 and supplies them to a transmitting means such as an antenna. .. The spread spectrum modulation unit 1 includes the primary modulation circuits 11, 21, 31, 41 and
It is composed of the following modulation circuits 12, 22, 32, 42 and the adder circuit 3. The PN code generator 8 is a single PN code generator.
6 and a delay circuit 7 for delaying the generated PN code, as shown in FIG. 2, a plurality of PN codes PN1, PN codes of the same series and different in phase by one chip from each other.
Outputs PN2, PN3, PN4.

The PN code generator 6 outputs a nine-stage M-sequence PN code PN1 by a shift register, for example. When the PN code PN1 is input, the delay circuit 7 receives the original PN code PN1, the PN code PN2 delayed by one chip in the first delay circuit 71, and one chip in the second delay circuit 72. The delayed PN code PN3 and the third delay circuit 7
At 3 the four PN codes PN1, PN2, PN3 and PN4 with the PN code PN4 further delayed by one chip are output.

The operation of the PN code generating circuit 8 is synchronized with the clock from the clock generating circuit 4.

In the spread spectrum modulator having the above structure,
16-bit parallel signal S0 as a signal to be transmitted
Is input to the signal division circuit 5, it is divided into 4 bits. Then, it is converted into serial signals by the built-in parallel / serial converters and output as divided signals S1, S2, S3, S4.

The divided signal S1 is input to the primary modulation circuit 11 and modulated by a conventional modulation method such as SSB, PSK, FM, etc.
It becomes the next modulation signal S1 '. The primary modulation signal S1 'is spread-modulated by the PN code PN1 output from the PN code generation circuit 8 in the secondary modulation circuit 12 to become a spread modulation signal M1.

Similarly, the divided signals S2, S3, S4 are also primary-modulated by a conventional modulation method such as SSB, PSK, FM, and then spread-modulated as a secondary modulation to generate secondary-modulated signals M2, M3, M4. Is output.
PN code supplied to the above secondary modulation circuits 12, 22, 32, 42
Since PN1, PN2, PN3, and PN4 are each delayed by one chip, it means that they are spread-spectrum-modulated by apparently different PN codes, and after addition in the adder circuit 3, they can be demodulated as separate signals.

As described above, in the case of the conventional spread spectrum modulator that converts a 16-bit parallel signal into a serial signal and performs spread spectrum modulation, the transmission speed is faster than the product of the clock rate and the number of bits of the serial signal. However, according to the above-described spread spectrum modulator, the 16-bit parallel signal S0 is divided into 4 bits by 4 bits to be converted into 4 serial signals, and the spread spectrum modulation is performed in parallel.
It is possible to obtain a transmission speed four times that of the conventional one.

Moreover, one type of PN code generated from the single PN code generator 6 is used to apparently generate a different type of P
The N code can be obtained.

In the above embodiment, the example in which the original signal to be transmitted is divided into four is shown, but the number of divisions is not limited to four, and N divisions are provided to provide N sets of the primary modulation circuit and the secondary modulation circuit. By adding them, it is possible to further increase the transmission speed, and it is also possible to transmit a high-speed signal at a speed close to the bit rate of the PN code. Also, PN code
The mutual phase difference between PN1, PN2, PN3, and PN4 is not limited to the one-chip difference as in the above embodiment. Eg 3
It is also possible to make a difference between chips, a difference between one chip, and a difference between two chips.

As the PN code generation circuit, for example, a 9-stage M-sequence shift register code sequence generator of feedback taps [9, 4] is used, and 9-stage, 8-stage, 7-stage shift registers are used.
PN code PN that differs from chip to chip by utilizing the fact that the signals extracted from the 1st and 6th stages are out of phase by 1 chip
It is also possible to directly obtain 1, PN2, PN3, PN4 from one 9-stage M-sequence shift register code sequence generator without using a delay circuit.

[0023]

According to the present invention, a signal to be transmitted in frequency spread communication is divided into a plurality of divided signals, and the divided signals are subjected to frequency spread modulation by different PN codes and then added together. Since the transmission is performed, the transmission can be performed in a shorter time as compared with the conventional spread spectrum modulation method using one type of PN code.

Therefore, a signal close to the bit rate of the PN code or a signal faster than the bit rate of the PN code can be transmitted, and the signal transmission speed can be increased. Further, when the band of the transmission means for transmitting the modulated signal is limited, it is possible to obtain the effect that the transmission can be performed without reducing the processing gain.

If one type of PN code is delayed to obtain PN codes of different types in appearance, it is not necessary to provide a plurality of PN code generating circuits, which is an economical effect in addition to the above effect. Can also be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a spread spectrum modulator of the present invention.

FIG. 2 is an explanatory diagram of a PN code in the above embodiment.

[Explanation of symbols]

 3 Adder circuit 5 Signal division circuit 6 PN code generator 7 Delay circuit 8 PN code generator circuit 11,21,31,41 Primary modulation circuit 12,22,32,42 Secondary modulation circuit M1, M2, M3, M4 2 Secondary modulation signal PN1, PN2, PN3, PN4 PN code S0 Parallel signal (signal to be transmitted) S1, S2, S3, S4 Split signal S1 ', S2', S3 ', S4' Primary modulation signal

Claims (2)

[Claims] 1. A PN code generation circuit that outputs a plurality of different PN codes, a signal division circuit that divides a signal to be transmitted into a plurality of divided signals, and each of the divided signals is modulated to obtain a primary modulation signal. A plurality of primary modulation circuits for outputting, and a plurality of two secondary modulation signals for performing the spread spectrum modulation of the respective primary modulation signals by the different PN codes.
A frequency spread modulator comprising a secondary modulation circuit and an adder circuit for adding secondary modulation signals output from the secondary modulation circuits. 2. The PN code generating circuit comprises one PN code generator and a delay circuit for delaying the generated PN code, and the same PN code and at least one chip phase different from each other. The spread spectrum modulator according to claim 1, wherein the spread spectrum modulator is a PN code generation circuit that outputs a plurality of PN codes.