JPH0513696A - Signal transmission circuit - Google Patents

Abstract

PURPOSE:To prevent damage of an output buffer at the time of failure in power supply to an input buffer, in a signal transmission circuit having a MOS output buffer, a MOS input buffer with an output signal of the output buffer as an input, a clamp circuit for protecting the input buffer and a power supply circuit for supplying power to the input buffer. CONSTITUTION:A power supply comparison circuit 200 for comparing a power supply level to an input buffer 7 with a reference value is provided, wherein when the comparison result shows detection of a drop in the level, an output buffer 3 is set at high impedance.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a signal transmission circuit, and particularly to a MOS (Metal Oxide Semiconductor) used in a transmission device or the like.
) A circuit for protecting an output buffer of an integrated circuit.

[0002]

2. Description of the Related Art Generally, in an output buffer of a MOS integrated circuit, in order to avoid device destruction of the MOS integrated circuit itself when an excessive current flows, a mechanism for suppressing the current flowing in the output buffer (for example, a current limiting current). Incorporating a limiting resistor, etc.) is adopted. The input buffer of the MOS integrated circuit uses a mechanism for protecting the input circuit from electrostatic breakdown, latch-up, etc. (for example, incorporating a diode clamp circuit into the input signal).

The conventional circuit will be described with reference to FIG.

In the figure, communication between the MOS integrated circuit 2 and the MOS integrated circuit 6 is performed by connecting an output buffer 9 of the MOS integrated circuit 2 and an input buffer 7 of the MOS integrated circuit 6. Further, the MOS integrated circuit 2 is powered by the power supply 1, and the MOS integrated circuit 6 is powered by the power supply 5.

In such a structure, when a predetermined power source is applied to both the MOS integrated circuit 2 and the MOS integrated circuit 6, the output buffer 9 and the MOS of the MOS integrated circuit 2 are connected.
Electrically normal operation is performed with the input buffer 7 of the integrated circuit 6. However, especially when the output of the power supply 5 of the MOS integrated circuit 6 is lowered or the power supply is cut off, the power supply of the MOS integrated circuit 6 and the input buffer 7 of the MOS integrated circuit 6 are equivalently connected by a diode. It becomes a state. As a result, the input buffer 7 of the MOS integrated circuit 6 is brought into a low impedance state, so that the MOS integrated circuit 2 receives the M
A large current flows in the direction of the OS integrated circuit 6. In this case, M
The output buffer 9 of the OS integrated circuit 2 is damaged or the MO
Even if the output buffer 9 of the S integrated circuit 2 is current-limited, the maximum rated current continues to flow, and finally MO due to heat.
The output buffer 9 of the S integrated circuit 2 may be destroyed.

As described above, in the conventional circuit, when the input buffer and the output buffer between the MOS integrated circuits having different power supplies are directly connected, the power of the MOS integrated circuit having the input buffer is not supplied. The MOS integrated circuit having the output buffer is damaged.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and an object thereof is to provide a signal transmission circuit capable of preventing the destruction of a MOS output buffer.

[0008]

A signal transmission circuit according to the present invention is a signal transmission circuit having a MOS output buffer, a MOS input buffer for receiving an output signal of the output buffer, and a power supply circuit for supplying power to the input buffer. A comparison circuit that compares the power supply level to the input buffer with a reference value, and a control circuit that puts the output buffer in a high impedance state when a decrease in the power supply level is detected by the comparison result. It is characterized by

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a signal transmission circuit according to the present invention, and the same portions as those in FIG. 2 are designated by the same reference numerals.

In the figure, the connection between the MOS integrated circuit 2 and the MOS integrated circuit 6 is made through the signal line 100 by using the output tristate buffer 3 of the MOS integrated circuit 2 and the input buffer 7 of the MOS integrated circuit 6. ..

On the side of the MOS integrated circuit 2, a power supply comparison circuit driven by the same power supply as the power supply 1 of the MOS integrated circuit 2.
Has 200. The power supply comparison circuit 200 compares the level of the output 202 of the driving power supply 5 on the MOS integrated circuit 6 side with the output level of the power supply 1. That is, the output level of the power supply 1 is the reference value, and it is monitored whether or not the level of the output 202 is lower than this reference value.

Furthermore, the output of the power supply comparison circuit 200 is connected to the enable terminal of the output tristate buffer 3 of the MOS integrated circuit 2 via the power supply disconnection signal line 201. That is, when the level of the output 202 of the driving power supply 5 on the MOS integrated circuit 6 side is lowered, the output tristate buffer 3 is controlled to a high impedance state. The MOS integrated circuit 2 is powered by the power supply 1 and the MOS integrated circuit 6 is powered by the power supply 5. However, in a normal state, both power supply levels are the same, and the output of the power supply comparison circuit 200 is Not sent out.

In such a structure, the comparison results match when a predetermined power source is applied to both the MOS integrated circuit 2 and the MOS integrated circuit 6. Therefore, the power supply comparison circuit 200
Output is stopped, and the MOS via the power supply disconnection signal line 201
The enable terminal of the output tristate buffer 3 of the integrated circuit 2 becomes the enable state. As a result, an electrically normal operation is performed between the output tristate buffer 3 of the MOS integrated circuit 2 and the input buffer 7 of the MOS integrated circuit 6.

In this state, the interface is the same as the interface between the MOS integrated circuit 2 and the MOS integrated circuit 6 described in the conventional circuit (FIG. 2).

Since the power supply comparison circuit 200 monitors the power supply 5 on the MOS integrated circuit 6 side by the above-described comparison operation, when the output 202 of the power supply 5 drops to a voltage at which the MOS integrated circuit 6 does not operate normally. , Outputs power-off information to the signal line 201. When this power-off information is given to the enable terminal of the output tri-state buffer 3 of the MOS integrated circuit 2 via the power-off signal line 201, the output tri-state buffer 3 of the MOS integrated circuit 2 becomes a high impedance state at that time. Controlled.

As a result, since the signal line 100 is in the high impedance state, even if the input buffer 7 of the MOS integrated circuit 6 is in the low impedance state as described in the conventional circuit, the MOS integrated circuits 2 to 6 are integrated.
It is possible to prevent the output tristate buffer 3 of the MOS integrated circuit 2 from being destroyed because the current does not flow into it.

Here, the power supply comparison circuit 200 is a circuit for comparing the output level of the power supply 5 with the output level of the power supply 1. For example, a well-known comparator using an OP amplifier can be easily constructed by those skilled in the art. it can. Further, another voltage supply source may be provided without using the output level of the power supply 1 as the reference value. In addition, the power supply comparison circuit 200 should be M
A configuration provided on the OS integrated circuit 6 side is also conceivable.

[0019]

As described above, according to the present invention, the output level of the power supply to the input buffer is compared with the reference value and the output side is set to the high impedance state when the power supply is abnormal, so that the power supplies are driven by different power supplies. In the configuration in which the output buffer and the input buffer between the MOS integrated circuits are directly connected,
Even if the power supply to the MOS integrated circuit having the input buffer is cut off, the MOS integrated circuit having the output buffer can be prevented from being destroyed.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a signal transmission circuit according to an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a conventional signal transmission circuit.

[Explanation of symbols]

 1,5 power supply 2,6 MOS integrated circuit 3 tri-state buffer 7 input buffer 200 power supply comparison circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H03K 19/003 B 8941-5J H04L 25/02 S 8226-5K 8225-4M H01L 29/78 301 K

Claims (1)

Claims: What is claimed is: 1. A signal transmission circuit comprising a MOS output buffer, a MOS input buffer that receives an output signal of the output buffer, and a power supply circuit that supplies power to the input buffer. A comparison circuit that compares the power supply level to the input buffer with a reference value; and a control circuit that puts the output buffer into a high impedance state when a decrease in the power supply level is detected by the comparison result. Characteristic signal transmission circuit.