JPH05122496A - Image synthesizer - Google Patents

Abstract

PURPOSE:To efficiently obtain a synthetic image in which an arbitrary image is synthesized with an original image by storing the synthetic image to be stored in a memory card by applying image compression processing. CONSTITUTION:The image information of an original is converted to an electrical signal by a CCD 101, and is stored in the memory card 1 after applying compression, and the image information expanded by reading out from the memory card 117 is synthesized with the image information of the original further outputted by the CCD 101. In other words, trimming and masking processing, etc., are performed at an area processing circuit 106, and the output signals of them are inputted to an image synthesis circuit 109, then, compression and expansion processing is applied to them. A compressed image signal is stored once in the buffer memory of the compression and expansion circuit 109, and after that, it is transferred to the memory card 117 by a CPU 114. Meanwhile, when the expansion processing is performed, the image reproduction of the synthetic image can be realized by transferring the signal to the buffer memory by the CPU 114. synthesizing it with an image to be synthesized, and driving a laser 113 according to a synthetic image signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image synthesizing apparatus for synthesizing a standard image in a removable storage means such as a memory card after data compression and synthesizing the stored data while expanding the stored data. It is about.

[0002]

2. Description of the Related Art Currently, a digital copying machine is developed and put on the market, which converts image information of an original into an electric signal by a photoelectric conversion element such as CCD, performs image processing, and then forms an image by an electrophotographic process. ing.

Also, a removable storage device such as a memory card is attached to a copying machine, and image signals such as fixed characters and marks are stored in the storage device and combined with the image signal read during the copying operation. A device capable of obtaining an output image has also been developed.

[0004]

However, in the conventional example, as the image to be combined, it is not possible to combine the entire copy image of the normal copy image due to the limitation of the capacity of the memory card, and its application is limited.

Further, when such a function is used, the operator has to instruct the output position and the like each time by using the operation unit or the digitizer, and the operability cannot be said to be good.

[0006]

In view of the above, the present invention intends to cover the entire area of a copy of A4 to A3 by compressing and storing a composite image stored in a memory card.

Further, when image editing processing such as scaling and movement is required when synthesizing images, the information is also stored in the memory of the same memory card, and the information is copied when the memory card is attached to the apparatus. It is intended to improve the operability by reading the data into the main body of the apparatus and automatically setting the corresponding copy mode.

[0008]

Embodiments of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing an image processing circuit of an electrophotographic digital copying machine using a laser.

Image information of the original is converted into an electric signal formed on the CCD 101. The timing signal for driving the CCD and the subsequent image processing is the timing generation circuit 1.
It is generated in 07 and supplied to each part.

After the image signal is amplified by the amplifier 102, A
The signal is converted into a digital signal by the / D converter 103. The shading circuit 104 applies the digital image signal to illumination unevenness and C
Shading distortion such as CD sensitivity unevenness is corrected. As the correction coefficient for shading correction, the standard white signal obtained through the shading correction circuit 104 is sent to the CP via the data bus DATA and the address bus ADRES.
It is taken into U114 and calculated based on this, and the calculation result is stored in the memory of the shading correction circuit 104.

The image signal subjected to the shading correction is subjected to scaling / moving processing by the scaling / moving circuit 105. Parameters such as the scaling factor and the moving distance are set by the CPU 114 input through the operation unit 116.

Next, processing such as trimming and masking is performed in the area processing circuit 106, and the output signal thereof is input to the image synthesizing circuit and compressed / expanded. The compressed image signal is temporarily stored in the buffer memory 2 of the compression / expansion circuit 109.
After being stored in 04 and 205, they are transferred to the memory card 117 by the CPU 114.

The memory card 117 is a non-volatile memory such as a battery backup, and the stored data is not lost even if it is removed from the main body.

On the other hand, in the case of decompression processing, the CPU 114 transfers the images to the buffer memories 204 and 205 and combines them with the image to be combined, and the laser 113 is driven according to the combined image signal to realize image reproduction of the combined image.

Details of the image synthesizing circuit 109 will be described with reference to FIG.

Image signal Vin from the area processing circuit 106
Is compressed by the compression circuit 201 by a run length method in which coding is performed based on the continuous length of white pixels / black pixels of the image. Compressed code D ₀ is inputted to the X input of the two-way selector circuit 203, a buffer memory 2 in response to the select signal C _1, C ₂
04 or the buffer memory 205.

Here, the relationship between C ₁ and C ₂ of the selector circuit 203 and the signal flow is as shown in Table 1, and (C ₁ , C ₂ )
= (0,0) to the buffer memory 204, (C ₁ ,
When C ₂ ) = (0,1), it is stored in the buffer memory 205.

[0019]

[Table 1]

C ₁ and C ₂ are set by the CPU 114 latching the data on the data bus DATA with the latch 210. The timing signal of the latch is the CPU
This is a signal obtained by the OR gate 209 of the logical sum of the write signal WR 114 and the enable signal CS. Latch 210
Output CE0, CE1 of respectively correspond to C _1, C _2.

On the other hand, for the address for the buffer memory, the clock CCLK1 synchronized with the changing point of the image signal is generated in the compression circuit 201, and the address clock selector 2
It is input to the address counter 207 via 08, and the address value is incremented by 1 in synchronization with the rising edge of the clock. This address data is the address selector 206.
Is input to the buffer memories 204 and 205 through the buffer memory and the compressed data is written using the clock CCLK1 as a write signal.

Here, the initial setting of the count value of the address counter 207 is performed by the CPU 114 in synchronization with the output CE6 of the latch 210.

The data flow of the address selector 206 is as shown in Table 2. When (C ₁ , C ₂ ) = (0, 0), the buffer memory 204 is accessed and (C ₁ , C ₂ ) is accessed.
When = (0,1), the buffer memory 205 is accessed.

[0024]

[Table 2]

The data stored in the buffer memory is CP
It is transferred to the memory card 117 by U114.

As can be seen from Tables 1 and 2, the operations of the buffer memories 204 and 205 are independent of each other,
By controlling C ₁ and C ₂ , it is possible to transfer the data in the buffer memory 205 to the memory card 117 while writing the compressed data in the buffer memory 204, and conversely, while writing the compressed data in the buffer memory 205. The data in the buffer memory 204 can be transferred to the memory card 117. That is, by repeating this operation, it becomes possible to transfer the image data larger than the capacity of the buffer memories 204 and 205 to the memory card 117.

Next, a description will be given of how the compressed data in the memory card 117 is expanded and the images are combined. The compressed data stored in the memory card 117 is, as shown in Table 1 and Table 2, CP according to the control signals C ₁ and C ₂ to the bidirectional data selector 203 and the address selector 206.
It is transferred to the buffer memory 204 or the buffer memory 205 by U114.

At the same time, the data in the buffer memories 204 and 205 are input to the decompression circuit 202, and the clock DCLK generated every time the decompression process of the code data is completed.
However, the address counter 207 is incremented by 1 via the clock selector 208, the next address of the buffer memory is accessed, and the next code data processing is performed.

The image data from the decompression circuit 202 is combined with the image data of the original by the OR gate 211, and the laser 1
13 is output.

(Explanation of the compression circuit 201) The details of the compression circuit 201 will be described with reference to FIGS.

The compression method of this embodiment is a run length method for coding how many black or white pixels continue, and in this embodiment the pixel length is used as it is as a compression code. The bit length is 16 bits / code in consideration of the data length of the CPU 114. FIG. 3 is a circuit block diagram, and FIG. 4 is its timing chart.

The image signal Vin is supplied to a pixel clock VCLK by a D flip-flop (hereinafter referred to as DF / F) 301.
Is held in synchronism with the input signal, the exclusive OR of the inverted output and the input signal is calculated by the EXOR gate 302, and the output signal CLOAD is connected to the load terminal of the counter 304. This signal CLOAD becomes L at the change pixel of the image signal Vin, and "1" is set to the counter 304 at this timing.

The counter 304 counts up in synchronization with the pixel clock VCLK until the next change point of the image signal Vin. The count value of the counter 304 is the clock C generated at the next change point of the image signal Vin.
The data is held in the DF / F 305 in synchronization with the rising edge of CLK1 and is output as compressed data Do.

The clock CCLK1 is a signal obtained by the AND gate 306 calculating the logical product of the clock CCLK2 and the clock CCLK3 obtained by the OR gate 303 calculating the logical sum of the signal CLOAD and the pixel clock VCLK.
The data Do is written in the buffer memory by the clock CCLK1 generated at the next change point of the image signal Vin.
It is done in synchronization with.

The clock CCLK3 is a signal generated for writing the final data of the line in the buffer memory, and the line synchronization signal LSYNC is set to 1 by the DF / F310.
Inverted output delayed by pixel clock and line sync signal L
This is a signal obtained by calculating the logical sum of SYNCC and the pixel clock VCLK by the OR gate 312.

In the compression system of this embodiment, one line is a unit, and the EOL code, which is a line end code, is output as Do from the buffer 309 in synchronization with the fall of the line synchronization signal LSYNCC, and the compressed data Of the output control signal OE1 to the DF / F305
And the output control signal OE2 for the buffer 309. OE2 is a line synchronization signal LSY
OR30 of the signal CE3 of the latch 210 and the signal obtained by delaying NCC by 2 pixel clocks by the DF / Fs 310 and 311.
8 outputs.

On the other hand, OE1 is the OR output of the inverted output of DF / F 311 and CE3. Here, CE3 is set to "L" when the image data is compressed, and the compressed data Do is in the output enable state, while "H" is set when the data is transferred from the bidirectional data selector 203 to the decompression circuit 202. , The compressed data Do is in a high impedance state.

(Explanation of Expansion Circuit 202) Details of the expansion circuit 202 will be described with reference to FIGS. FIG. 5 is a circuit block diagram, and FIG. 6 is a timing chart thereof.

The compressed data Di from the buffer memories 204 and 205 is loaded into the down counter 320,
The countdown is performed in synchronization with the pixel clock VCLK. The count value DCNT of the down counter 320 is input to the comparator 321, and the output DLOAD of the comparator 321 when DCNT = 1 is "L". Output D
LOAD is input to the load terminal of the down counter 320 via the AND circuit 323, and the data next to the compressed data Di is loaded into the down counter 320 at the timing when DLOAD is "L".

DLOAD is a JK flip-flop synchronized with the pixel clock VCLK (hereinafter referred to as JKF / F) 3
Input to the inverted J and K terminals of 24, and JKF / F is DLO
When AD = “L”, the output Dout is inverted.

That is, the output Dout is the compressed data Di.
Inversion is performed every pixel clock VCLK according to the value of, and decoding of the image signal is realized.

The output of the JKF / F324 is controlled by the output CE5 of the latch 210, and CE5 = "L".
In the case of, the output is enabled, and in the case of CE5 = “H”, it is in the high impedance state.

Next, the processing of the EOL code will be described. When the EOL code is loaded into the down counter 320 as the compressed data Di, the output DEOL of the comparator 322 becomes “L”. The output EDOL is input to the inverted S terminal of the RS flip-flop (hereinafter referred to as RSF / F) 328, and the inverted output ELOAD is set to "L" in synchronization with the pixel clock VCLK.

The ELOAD is combined with the above-mentioned DLOAD by the AND gate 323 and becomes the load signal of the down counter 320. The output ELOAD is released by inputting a signal obtained by inverting the line synchronization signal LSYNCD for the expansion circuit by the inverter 327 to the inversion R terminal of the RSF / F328, and becomes "H".

The count-up clock DCLK of the address counter 207 is an inverted signal of LSYNCD, DLOA.
The AND gate 325 calculates the logical product of D and DEOL, and the logical sum of the result and the pixel clock VCLK is ORed.
It is calculated by the gate 326, and the down counter 3
It is output when the count value DCNT of 20 becomes "1" or the EOL code, and when the line synchronization signal LSYNCD becomes "H".

Although the run length method has been described as the compression method in this embodiment, the MH, MR, and MMR used for facsimile communication can be similarly adopted.

FIG. 7 shows a specific example achieved by the configuration of the above embodiment. FIG. 7A shows a fixed format for facsimile transmission, and an area A is an area for writing a transmission sentence. FIG. 7B shows a facet for facsimile transmission. FIG. 7C is an output result obtained by combining (a) and (b).

First, the format image of (a) is read and compressed by the compression circuit 201. The compressed data is stored in the memory card 117 via the buffer memories 204 and 205.

Next, the sheet in which the transmission sentence of (b) is written is read, and in synchronization with this reading operation, the compressed format data stored in the memory card 117 is expanded through the buffer memories 204 and 205. The data is decompressed in 202 and combined with the transmitted sentence data to obtain (c).

At this time, the writing area A of the transmission sentence of (a)
Is Xf × Yf, which is smaller than Xo × Yo in (b), so (b) is subjected to scaling processing and scaling processing during synthesis.
This must be done by the mobile circuit 105.

Reduction ratio Xf / Xo (or Yf /
The smaller of Yo) and the movement distance data (Xm, Ym) are
It must be set in the copying machine in advance when performing the combining process. However, if the size of the transmission sentence to be combined with the format image is always constant, this setting value is
It is not efficient to set each time the synthesizing process is performed.

Therefore, this set value is stored in a predetermined format in a predetermined address of the memory card in which the format image data is stored. Further, a signal Int for detecting that the memory card is mounted in the main body of the copying apparatus is input to the interrupt terminal of the CPU 114 in advance.

When the memory card 117 is attached to the main body, the processing contents stored on the memory card and the set values thereof are automatically read by the interrupt processing and set in the apparatus. By doing so, a composite image can be obtained only by mounting the memory card on the copying apparatus.

FIG. 8 is a diagram in which the date information generated by the character generation circuit 108 is added to the format image and combined.

In this case, the information for synthesizing the date and the information regarding the synthesizing date are also stored in the memory card, and the information is stored in the CPU 1 when the memory card is mounted in the main body.
14 is read together with the image processing information.

In addition to date, information such as time, telephone number, page, etc. can be synthesized if there is a character generation circuit capable of generating simple alphanumeric characters.

The format image shown in the above-mentioned embodiment can be said to be an image suitable for the run length method. However, if the dithered image is compressed by the run length method to maintain the reproducibility of continuous tone images such as photographs,
On the contrary, the data amount may be larger than that of the original image.

Therefore, the image synthesizing circuit 109 is provided with means for selecting whether or not to compress the data, and when synthesizing the image data stored in the memory card without compressing, the decompression circuit is bypassed. Means were also provided.

FIG. 9 is a circuit block diagram for explaining the present embodiment. In the figure, the same symbols are assigned to blocks having the same functions as those in FIG.

Since the image signal Vin is a binary signal, the serial / parallel conversion circuit 212 converts it into parallel data in units of 16 pixels in order to match the bit length with the compressed data.

From this circuit, the count-up clock PCLK of the address counter 207 is generated every 16 pixels. The selection of compressed / uncompressed data is controlled by the outputs CE2 and CE3 of the latch 210. CE2 = “L”, CE
When 3 = “H”, the output of the compression circuit 201 is in a high impedance state and non-compressed data is stored in the memory card, and when CE2 = “H” and CE3 = “L”, the serial / parallel conversion circuit 212. Output becomes a high impedance state and the compressed data is stored in the memory card.

On the other hand, in the case of image composition, the memory card 11
The image data stored in 7 is the buffer memory 204, 2
1 via the parallel / serial conversion circuit 213 via 05
It is converted into a binary image signal Vout in units of 6 pixels.

From this circuit, the count-up clock SCLK of the address counter 207 is generated every time one data is converted into image data of 16 pixels. Latch 21
The outputs are controlled by outputs CE4 and CE5 of 0. C
When E4 = “L” and CE5 = “H”, the output of the expansion circuit 202 becomes a high impedance state and the serial conversion output becomes the composite signal Vout, and CE4 = “H”, CE5.
When "L", the output of the parallel / serial conversion circuit 213 becomes a high impedance state, and the expanded output becomes the composite signal Vout.

The clock selector 214 switches the count-up clock by the outputs CE2 and C of the latch 210.
It is realized as shown in Table 3 by using E3, CE4, and CE5 as switching signals.

[0065]

[Table 3]

[0066]

As described above, by compressing and storing the composite image stored in the memory card, it is possible to combine the format image covering the entire copy area even if the memory has a large capacity. it can.

Further, when image editing processing such as scaling and movement is required in image composition, information related to it is also stored in the same memory card, and is automatically required when the memory card is mounted in the copying machine. It is possible to improve the operability by setting a different mode.

Further, by providing a means for generating simple characters such as alphanumeric characters, the date, time, page, etc. can be added to an arbitrary place on the format to be combined. Further, the operability can be improved by storing the information on the item to be added and the information on the position in the memory card so that the information is automatically read when the item is attached to the copying apparatus.

Further, by providing a means for bypassing the compression processing and the expansion processing, it is possible to deal with an image whose data amount increases rather than the compression processing such as the dither processing image.

[Brief description of drawings]

FIG. 1 is an image processing block diagram of an apparatus.

FIG. 2 is a block diagram of an image synthesizing circuit.

FIG. 3 is a block diagram of a compression circuit.

FIG. 4 is a timing chart of a compression circuit.

FIG. 5 is a block diagram of a decompression circuit.

FIG. 6 is a timing chart of a decompression circuit.

FIG. 7 is a diagram showing a specific example according to the present invention.

FIG. 8 is a diagram showing a specific example of the second exemplary embodiment.

FIG. 9 is a circuit block diagram of a third embodiment.

[Explanation of symbols]

 101 CCD 105 Magnification / Movement Circuit 106 Area Processing Circuit 108 Character Generation Circuit 109 Image Compositing Circuit 117 Memory Card

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 1/00 107 Z 4226-5C

Claims (5)

[Claims] 1. An image reading unit for forming image information of a document on a photoelectric conversion element and converting it into an electric signal, a first processing unit for processing a read image signal of a first document, and the first processing unit. Removable storage means for storing the image signal processed by the processing means, second processing means for processing the image signal stored in the storage means, and image signal processed by the second processing means And an image synthesizing device for synthesizing the read image signal of the second original. 2. The image synthesizing apparatus according to claim 1, wherein the first processing means is an image compression processing and the second processing means is an image expansion processing. 3. The detachable storage means according to claim 1, wherein image editing information for a document image signal at the time of composition is stored, and when the storage means is attached to the apparatus, the image editing information is read and edited. An image synthesizing device characterized by automatically setting a mode. 4. The apparatus according to claim 1, further comprising means for generating a character image signal, wherein the character image signal is generated in accordance with an instruction stored as image editing information at the time of combining, and the first read image signal and the first read image signal are generated. An image synthesizing device characterized by synthesizing with the read image signal of 2. 5. The image synthesizing apparatus according to claim 1, further comprising means for bypassing the first processing means and the second processing means.