JPH05122052A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a circuit area with a level conversion function and also a logic circuit function. CONSTITUTION:A semiconductor device is constituted in such a way that a first inverter circuit 1 which is operated by a power source Vcc and the power source Vss and also inputs an input signal IN is connected with a second inverter circuit 2 which is operated by the power source Vss and the power source VDD which is higher than the power source Vcc and also outputs an output signal OUT via N-channel MOS transistor Tr1, a binary control signal phiwhich changes between a power source voltage VDD and the power source voltage Vss is inputted in the gate of the transistor Tr1, the input terminal of the second inverter circuit 2 is connected with the power source VDD via the P-channel MOS transistor Tr2 and the gate of the P-channel MOS transistor Tr2 is connected with the output terminal of the second inverter circuit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which transmits signals between circuits which operate at different power supply voltages.

In recent semiconductor integrated circuits, a large number of power supplies having different voltages are used to drive internal circuits. For this reason, a level conversion circuit is required between the circuits that operate with different power supply voltages to transmit signals, and it is necessary to reduce the area occupied by the level conversion circuit in order to achieve high integration. is there.

[0003]

2. Description of the Related Art An example of a conventional level conversion circuit will be described with reference to FIG. 4. An input signal IN is input to a power source Vcc and an inverter circuit 1 having the power source Vss, and an output signal SG1 of the inverter circuit 1 is applied to a gate. The output signal SG2 is input to the inverter circuit 2 having the power source VDD and the same Vss as the power source through the N-channel MOS transistor Tr1 supplied with the power source VDD, and the inverter circuit 2 outputs the output signal OUT. The drain of the P-channel MOS transistor Tr2 is connected to the input terminal of the inverter circuit 2, the power source VDD is supplied to the source of the transistor Tr2, and the gate is connected to the output terminal of the inverter circuit 2.

The operation of the level conversion circuit having such a configuration will be described with reference to FIG. 5. When the input signal IN changes from H level to L level, the output signal SG of the inverter circuit 1 is output.
1 rises from the level of the power source Vss at the L level to the level of the power source Vcc at the H level.

Then, the input signal SG of the inverter circuit 2 is generated based on the operation of the transistor Tr1 which is always on.
2 also rises to the power supply Vcc, and the output signal OUT falls from the H level, which is the level of the power supply VDD, to the L level, which is the level of the power supply Vss, based on this input signal.

When the output signal OUT shifts to the L level, the transistor Tr2 is turned on, the input signal SG2 of the inverter circuit 2 is pulled up to the H level which is the level of the power source VDD, and this state is maintained. In addition, power supply VDD
And the voltage difference between the power source Vcc and the threshold V of the transistor Tr1.
It is about th.

On the other hand, when the input signal IN shifts from the L level to the H level, the output signal SG1 of the inverter circuit 1 falls from the level of the power source Vcc to the level of the power source Vss.
Then, the input signal SG2 of the inverter circuit 2 also falls to the level of the power source Vss based on the operation of the transistor Tr1, and the output signal OUT changes the power source Vss based on this input signal.
Rising to the level of DD, the transistor Tr2 is turned off.

Therefore, the input signal IN which fluctuates between the power supply Vcc and the power supply Vss due to such an operation has the same voltage as the power supply VDD.
The level is converted into an output signal OUT which varies between ss and ss.

[0009]

However, the level conversion circuit as described above requires two transistors Tr1 and Tr2 to perform the level conversion operation. In addition to the usual logic circuit, such a circuit is required every time the level conversion is performed, which causes a problem that the circuit area increases.

An object of the present invention is to provide a semiconductor device capable of reducing the circuit area by having a level conversion function and a logic circuit function together.

[0011]

FIG. 1 illustrates the principle of the present invention. That is, the first inverter circuit 1 which is operated by the first high-potential power supply Vcc and the low-potential power supply Vss and receives the input signal IN, and the second high voltage which is higher than the first high-potential power supply Vcc. A potential side power source VDD and a second inverter circuit 2 that operates on the low potential side power source Vss and outputs an output signal OUT are connected via an N-channel MOS transistor Tr1 and the gate of the transistor Tr1 is connected to the second The binary control signal φ changing between the high-potential-side power supply voltage VDD and the low-potential-side power supply voltage Vss of
The input terminal of the second inverter circuit 2 is a P channel M
The P-channel MOS transistor T is connected to the second high-potential-side power source VDD through the OS transistor Tr2.
The gate of r2 is connected to the output terminal of the second inverter circuit 2.

[0012]

When the second high-potential-side power supply voltage VDD is input to the gate of the N-channel MOS transistor Tr1 as the control signal φ, the level of the input signal IN is converted and the output signal OUT is output.
When the low-potential-side power supply Vss is input to the gate of the N-channel MOS transistor Tr1 as the control signal φ, an output signal OUT having a logic different from that of the input signal IN can be output.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIG.
According to the above description, this embodiment is different from the above-mentioned conventional example only in that the binary control signal φ varying between the power supply VDD and the power supply VDD is inputted to the gate of the transistor Tr1.

With such a structure, as shown in FIG. 3, when the control signal .phi. Is supplied with the H level which is the level of the power supply VDD, the operation is similar to that of the conventional example. On the other hand, for example, when the control signal φ is shifted to the L level when the input signal SG2 of the inverter circuit 2 is at the H level and the output signal OUT of the inverter circuit 2 is at the L level, the transistor T
r1 is turned off. Then, even if the input signal IN is shifted to the H level, the output signal OUT is maintained at the L level without being influenced by the input signal IN.

Further, the input signal SG2 of the inverter circuit 2 is
Is L level, and the output signal OUT of the inverter circuit 2 is H
When the control signal φ is shifted to the L level in the level state,
The transistor Tr1 is turned off. Then, the input signal IN
Of the input signal I
The H level is maintained without being affected by N.

Therefore, since this level conversion circuit has a function as a logic circuit based on the control signal φ in addition to the level conversion operation, the logic circuit for outputting the above logic is omitted and the circuit area is reduced. It can be reduced.

[0017]

As described above in detail, the present invention exerts an excellent effect that it is possible to provide a semiconductor device having a level converting function and a function of a logic circuit, which can reduce the circuit area.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

FIG. 3 is a waveform diagram showing the operation of one embodiment.

FIG. 4 is a circuit diagram showing a conventional example.

FIG. 5 is a waveform diagram showing an operation of a conventional example.

[Explanation of symbols]

 1 First Inverter Circuit 2 Second Inverter Circuit Vcc First High-potential-side power supply VDD Second High-potential-side power supply Vss Low-potential-side power supply IN Input signal OUT Output signal φ Control signal Tr1 N-channel MOS transistor Tr1 P-channel MOS transistor

Claims (1)

[Claims] 1. A first inverter circuit (1) which operates with a first high potential side power source (Vcc) and a low potential side power source (Vss) and receives an input signal (IN), and the first inverter circuit (1). The second high potential side power supply (VD) higher than the high potential side power supply (Vcc)
D) is connected to the second inverter circuit (2) which operates on the low potential side power source (Vss) and outputs an output signal (OUT) via an N-channel MOS transistor (Tr1), and the transistor (Tr1) ) Is inputted with a binary control signal (φ) which changes between the second high potential side power source voltage (VDD) and the low potential side power source voltage (Vss), and the second inverter circuit ( The input terminal of 2) is connected to the second high-potential-side power source (VDD) through a P-channel MOS transistor (Tr2), and the P-channel MOS transistor is connected.
The semiconductor device, wherein the gate of the transistor (Tr2) is connected to the output terminal of the second inverter circuit (2).