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JPH05121739A - Insulating gate semiconductor device - Google Patents

Insulating gate semiconductor device

Info

Publication number
JPH05121739A
JPH05121739A JP27926091A JP27926091A JPH05121739A JP H05121739 A JPH05121739 A JP H05121739A JP 27926091 A JP27926091 A JP 27926091A JP 27926091 A JP27926091 A JP 27926091A JP H05121739 A JPH05121739 A JP H05121739A
Authority
JP
Japan
Prior art keywords
semiconductor region
semiconductor
region
drain
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27926091A
Other languages
Japanese (ja)
Inventor
Isao Yoshida
功 吉田
Mineo Katsueda
嶺雄 勝枝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP27926091A priority Critical patent/JPH05121739A/en
Publication of JPH05121739A publication Critical patent/JPH05121739A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To reduce the drain capacitance and thereby to improve the high- frequency characteristics of an MOSFET. CONSTITUTION:A low impurity cencentration drain region 5 and a high impurity cencentration drain region 6 are formed using an insulator spacer 7' formed on the end sidewall of a gate electrode 9. Accordingly, the drain region 5 can have a self-aligned structure using the insulator spacer 7' so that the capacitance of the drain including an offset gate part may be notably decreased, thereby improving the high-frequency characteristics of the MOSFETs.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置に係り、特に
高周波用途に好適な絶縁ゲート半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an insulated gate semiconductor device suitable for high frequency applications.

【０００２】[0002]

【従来の技術】従来、高周波用途の絶縁ゲート形電界効
果トランジスタ（ＭＯＳＦＥＴ）においては、特開昭５
８−１１１３７２号公報、特開平１−２６８０６６号公
報に記載のように、高周波特性改善のために、低濃度ド
レイン領域を設け、その長さをフォトエッチングのマス
クにより規定したり、高濃度ドレインをスタックド構造
として、ドレイン−基板間の容量の低減の方策が取られ
ていた。2. Description of the Related Art Conventionally, an insulated gate field effect transistor (MOSFET) for high frequency use is disclosed in Japanese Unexamined Patent Publication (Kokai) No.
As described in Japanese Patent Application Laid-Open No. 8-111372 and Japanese Patent Application Laid-Open No. 1-268066, a low-concentration drain region is provided and its length is defined by a photoetching mask or a high-concentration drain is provided in order to improve high frequency characteristics. As a stacked structure, a measure for reducing the drain-substrate capacitance has been taken.

【０００３】[0003]

【発明が解決しようとする課題】前記従来技術は、ＭＯ
ＳＦＥＴのドレイン−基板間の容量の低減に着目しては
いるもののオフセットゲート部を含めたドレイン容量の
低減が十分でなく、なお高周波特性に問題があった。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Although attention is paid to the reduction of the drain-substrate capacitance of the SFET, the reduction of the drain capacitance including the offset gate portion is not sufficient, and there is still a problem in the high frequency characteristics.

【０００４】本発明の目的は、ドレイン−基板間特にオ
フセットゲート部の容量を極力低減して、ＭＯＳＦＥＴ
の高周波特性を改善することにある。An object of the present invention is to reduce the capacitance between the drain and the substrate, particularly the offset gate portion as much as possible, and
Is to improve the high frequency characteristics of.

【０００５】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明の一実施形態によれば、高不純物濃度の第１
導電型（ｐ＋）の第１半導体領域（１）上に低不純物濃
度の第１導電型（ｐ−）の第２半導体領域（２）を設
け、半導体主面から前記第１半導体領域（１）に達する
ように形成した第１導電型（ｐ）の第３半導体領域
（３）をベース領域とし、高不純物濃度の第２導電型
（ｎ＋）の第４半導体領域（４）をＭＯＳＦＥＴのソー
ス領域とし、前記第２半導体領域（２）内に低不純物濃
度の第２導電型（ｎ）の第５半導体領域（５）並びに高
不純物濃度の第２導電型（ｎ＋）の第６半導体領域
（６）を、ゲート電極（９）の端部側壁を覆うように形
成した絶縁物スペーサ（７’）をマスクとして形成し、
低不純物濃度の第２導電型（ｎ）の第５半導体領域
（５）並びに高不純物濃度の第２導電型（ｎ＋）の第６
半導体領域（６）をドレイン領域としたことを特徴とす
るものである（図１参照）。To achieve the above object, according to one embodiment of the present invention, a high impurity concentration first
A second semiconductor region (2) of the first conductivity type (p−) having a low impurity concentration is provided on the first semiconductor region (1) of the conductivity type (p +), and the first semiconductor region (1) is formed from the semiconductor main surface. To the source region of the MOSFET by using the third semiconductor region (3) of the first conductivity type (p) formed so as to reach the base region as the base region and the fourth semiconductor region (4) of the second conductivity type (n +) having a high impurity concentration. In the second semiconductor region (2), a fifth semiconductor region (5) of the second conductivity type (n) having a low impurity concentration and a sixth semiconductor region (6) of the second conductivity type (n +) having a high impurity concentration are provided. ) Is formed using an insulator spacer (7 ′) formed so as to cover the end side wall of the gate electrode (9) as a mask,
A fifth semiconductor region (5) of the second conductivity type (n) having a low impurity concentration and a sixth semiconductor region (5) of the second conductivity type (n +) having a high impurity concentration.
The semiconductor region (6) is a drain region (see FIG. 1).

【０００６】本発明の好適な実施形態によれば、前記ベ
ースに接続され、前記ゲート電極（９）のソース側端部
側壁を覆うように形成した絶縁物スペーサ（７’）をマ
スクとして形成した第１導電型（ｐ）の第７半導体領域
（１３）を設けたことを特徴とするものである（図３参
照）。According to a preferred embodiment of the present invention, an insulator spacer (7 ') connected to the base and formed so as to cover the source side end side wall of the gate electrode (9) is formed using a mask. A seventh semiconductor region (13) of the first conductivity type (p) is provided (see FIG. 3).

【０００７】さらに、本発明の他の一実施形態によれ
ば、前記低不純物濃度の第１導電型（ｐ−）の第２半導
体領域（２）内に、前記第５半導体領域（５）より浅く
第１導電型（ｐ）の第８半導体領域（１４）を設けたこ
とを特徴とするものである（図４参照）。According to another embodiment of the present invention, the fifth semiconductor region (5) is formed in the second semiconductor region (2) of the first conductivity type (p-) having a low impurity concentration. It is characterized in that a shallow eighth semiconductor region (14) of the first conductivity type (p) is provided (see FIG. 4).

【０００８】さらに、本発明の他の一実施形態によれ
ば、前記低不純物濃度の第１導電型（ｐ−）の第２半導
体領域（２）内に、前記第４半導体領域（４）と第５半
導体領域との間に第１導電型（ｐ）の第９半導体領域
（１５）を設けたことを特徴とするものである（図５参
照）。Further, according to another embodiment of the present invention, the fourth semiconductor region (4) is provided in the second semiconductor region (2) of the first conductivity type (p-) having the low impurity concentration. A ninth semiconductor region (15) of the first conductivity type (p) is provided between the fifth semiconductor region and the fifth semiconductor region (see FIG. 5).

【０００９】さらに、本発明の他の一実施形態によれ
ば、低不純物濃度の第１導電型（ｐ）の第２半導体領域
（２）に形成したＭＯＳＦＥＴにおいて、ゲート電極の
端部側壁を覆うように形成した絶縁物スペーサ（７’）
をマスクとして形成し、高不純物濃度の第２導電型（ｎ
＋）の第４半導体領域（４）をソース、低不純物濃度の
第２導電型（ｎ）の第５半導体領域（５）並びに高不純
物濃度の第２導電型（ｎ＋）の第６半導体領域（６）を
ドレインとしたことを特徴とする絶縁ゲート半導体装置
（図７参照）。Furthermore, according to another embodiment of the present invention, in the MOSFET formed in the second semiconductor region (2) of the first conductivity type (p) having a low impurity concentration, the end sidewall of the gate electrode is covered. Insulator spacer (7 ')
Of the second conductivity type (n
+) Fourth semiconductor region (4) as a source, low impurity concentration second conductivity type (n) fifth semiconductor region (5) and high impurity concentration second conductivity type (n +) sixth semiconductor region ( An insulated gate semiconductor device having a drain of 6) (see FIG. 7).

【００１０】[0010]

【作用】本発明の代表的な実施形態（図１）では、オフ
セットゲートＭＯＳＦＥＴの低濃度を含むドレイン領域
を、絶縁物スペーサを用いた自己整合構造で構成するこ
とができる。これにより、オフセットゲート部を含めた
ドレイン容量（ドレイン−基板間容量）が大幅に低減で
き、ＭＯＳＦＥＴの高周波特性を向上させることができ
る。本発明のＭＯＳＦＥＴを電力用高周波増幅器として
用いた場合の効率は、１０ＧＨｚの動作周波数において
従来構造と比較すると、約２倍向上する（図６参照）。In a typical embodiment of the present invention (FIG. 1), the drain region of the offset gate MOSFET including a low concentration can be formed by a self-aligned structure using an insulator spacer. As a result, the drain capacitance (drain-substrate capacitance) including the offset gate portion can be significantly reduced, and the high frequency characteristics of the MOSFET can be improved. When the MOSFET of the present invention is used as a high frequency power amplifier, the efficiency at the operating frequency of 10 GHz is improved by about 2 times as compared with the conventional structure (see FIG. 6).

【００１１】[0011]

【実施例】以下、本発明の実施例を図面により詳細に説
明する。Embodiments of the present invention will now be described in detail with reference to the drawings.

【００１２】図１は本発明の第１の実施例の絶縁ゲート
半導体装置の断面図を示してある。本素子はベース領域
がソースと接続されるソース接地型の高周波用ＭＯＳＦ
ＥＴである。本構造は０．０２Ωｃｍ以下のＰ型半導体
基板１上に低濃度Ｐ型半導体層２を厚さ５μｍのエピタ
キシャル成長したものを用いる。その半導体表面より、
ベースとなるＰ型領域３をＰ型半導体基板１に達するよ
うに５μｍ以上の深さに形成する。ゲート絶縁膜８は厚
さ３０ｎｍで、ゲート電極９はモリブデン金属を用い、
ゲート長０．８μｍである。ゲート電極の端部側壁を絶
縁物スペーサ７で覆い、その絶縁物下方の半導体表面領
域に表面濃度が１×１０18／ｃｍ3以下の低濃度Ｎ型領
域５が自己整合的に配置されている。ここで、スペーサ
の幅は０．８μｍであり、ドレイン電極を取り出すドレ
イン・コンタクト領域の幅は０．６μｍである。なおド
レイン電極１２及びソース電極１０は高濃度Ｎ型領域
６、４に接続されている。さらに、裏面のソース電極１
１は前記Ｐ型半導体基板１とベースとなるＰ型領域３を
介して前記ソース電極１０に接続されている。FIG. 1 is a sectional view of an insulated gate semiconductor device according to the first embodiment of the present invention. This element is a source-grounded high-frequency MOSF whose base region is connected to the source.
It is ET. This structure uses a low-concentration P-type semiconductor layer 2 epitaxially grown to a thickness of 5 μm on a P-type semiconductor substrate 1 of 0.02 Ωcm or less. From the semiconductor surface,
A P-type region 3 serving as a base is formed to a depth of 5 μm or more so as to reach the P-type semiconductor substrate 1. The gate insulating film 8 has a thickness of 30 nm, the gate electrode 9 is made of molybdenum metal,
The gate length is 0.8 μm. An end side wall of the gate electrode is covered with an insulator spacer 7, and a low concentration N-type region 5 having a surface concentration of 1 × 10 18 / cm 3 or less is arranged in a self-aligned manner in a semiconductor surface region below the insulator. .. Here, the width of the spacer is 0.8 μm, and the width of the drain / contact region for taking out the drain electrode is 0.6 μm. The drain electrode 12 and the source electrode 10 are connected to the high concentration N type regions 6 and 4. Furthermore, the source electrode 1 on the back surface
1 is connected to the source electrode 10 via the P-type semiconductor substrate 1 and a P-type region 3 serving as a base.

【００１３】図２は図１の本発明の実施例のＭＯＳＦＥ
Ｔの主要製造プロセスを示す断面構造図である。FIG. 2 shows the MOSFE of the embodiment of the present invention shown in FIG.
FIG. 6 is a cross-sectional structure diagram showing a main manufacturing process of T.

【００１４】図２（ａ）に示すように、ゲート絶縁膜８
形成後、モリブデン金属９及び絶縁膜７を被着し、ゲー
ト電極９を形成する。しかる後、図２（ｂ）に示すよう
にＣＶＤ法により絶縁膜を厚さ０．８μｍ被着し、全面
ドライエッチングにより、絶縁膜スペーサ７’を形成す
る。図２（ｃ）に示すように前記絶縁膜スペーサ７’を
マスクにして、低濃度ドレイン領域５および高濃度ソー
ス領域４をそれぞれイオン打ち込みにより形成する。打
ち込み量は、ドレインがリン５×１０13／ｃｍ2、ソー
スが砒素１×１０15／ｃｍ2である。図２（ｄ）に示す
ようにドレイン電極コンタクト用の高濃度ドレイン領域
６を形成する。打ち込み量は、砒素１×１０15／ｃｍ2
である。As shown in FIG. 2A, the gate insulating film 8
After the formation, the molybdenum metal 9 and the insulating film 7 are deposited to form the gate electrode 9. Thereafter, as shown in FIG. 2B, an insulating film having a thickness of 0.8 μm is deposited by the CVD method, and the entire surface is dry-etched to form an insulating film spacer 7 ′. As shown in FIG. 2C, the low-concentration drain region 5 and the high-concentration source region 4 are formed by ion implantation using the insulating film spacer 7'as a mask. The amount of implantation is 5 × 10 13 / cm 2 for phosphorus in the drain and 1 × 10 15 / cm 2 for arsenic in the source. As shown in FIG. 2D, a high concentration drain region 6 for contacting the drain electrode is formed. The implantation amount is 1 × 10 15 / cm 2 arsenic
Is.

【００１５】以下の工程は通常に行なわれる高周波半導
体プロセスを用いて製作できるので説明は省略する。Since the following steps can be manufactured by using a high frequency semiconductor process which is usually performed, the description thereof will be omitted.

【００１６】本構造の特徴は、ＭＯＳＦＥＴの低濃度ド
レイン領域が絶縁物スペーサの自己整合マスクにより、
精度良く制御されるので、目標のドレイン耐圧を得るた
めに余分な面積を必要としないことである。また、ドレ
イン電極を取るための高濃度領域の面積も必要最小限に
することができるので、ドレイン−基板間の容量が、従
来構造に比して、大幅に低減できる。本実施例によれ
ば、１．２×４ｍｍ2チップのパワーＭＯＳＦＥＴにお
いて、ドレイン耐圧２０Ｖ、電流容量２０Ａ、カットオ
フ周波数１６ＧＨｚが得られた。The feature of this structure is that the low-concentration drain region of the MOSFET is formed by a self-aligning mask of an insulator spacer.
Since it is controlled with high precision, no extra area is required to obtain the target drain breakdown voltage. Also, the area of the high concentration region for taking the drain electrode can be minimized, so that the capacitance between the drain and the substrate can be significantly reduced as compared with the conventional structure. According to this example, a drain MOSFET with a breakdown voltage of 20 V, a current capacity of 20 A, and a cutoff frequency of 16 GHz were obtained in a 1.2 × 4 mm 2 chip power MOSFET.

【００１７】本発明の実施例の効果を示す特性説明図を
図６に示す。これは、このパワーＭＯＳＦＥＴを高周波
増幅器として用いて、電力効率の動作周波数依存性を測
定し、従来の素子と比較したものである。図より明らか
なように、周波数が高くなるにつれて、本発明の実施例
の効果が現われ、１０ＧＨｚで効率は約２倍に向上す
る。FIG. 6 is a characteristic explanatory view showing the effect of the embodiment of the present invention. This is obtained by measuring the operating frequency dependence of power efficiency by using this power MOSFET as a high frequency amplifier and comparing it with a conventional device. As is clear from the figure, as the frequency becomes higher, the effect of the embodiment of the present invention appears, and the efficiency is improved about twice at 10 GHz.

【００１８】図３は、本発明の第２の実施例の絶縁ゲー
ト半導体装置の断面構造図である。本実施例では、ＭＯ
ＳＦＥＴのパンチスルー耐圧を向上させるために、Ｐ型
ベース領域１３を前記絶縁物スペーサ７’をマスクに形
成している。そのイオン打ち込み量はボロン１×１０14
／ｃｍ2である。これにより、ドレイン耐圧は２５Ｖに
向上した。FIG. 3 is a sectional structural view of an insulated gate semiconductor device according to the second embodiment of the present invention. In this embodiment, MO
In order to improve the punch-through breakdown voltage of the SFET, the P-type base region 13 is formed using the insulator spacer 7'as a mask. The ion implantation amount is boron 1 × 10 14
/ Cm 2 . As a result, the drain breakdown voltage was improved to 25V.

【００１９】図４は、本発明の第３の実施例の絶縁ゲー
ト半導体装置の断面構造図である。本実施例では、ＭＯ
ＳＦＥＴのパンチスルー耐圧を向上させるために、Ｐ型
不純物領域１４を、あらかじめ形成している。この１４
の領域の深さは、前記Ｎ型低濃度ドレイン領域５よりも
浅く設定してある。これにより、ドレイン−基板間の容
量をほとんど増加させないで、ドレイン耐圧は２４Ｖに
向上させることができた。FIG. 4 is a sectional structural view of an insulated gate semiconductor device according to the third embodiment of the present invention. In this embodiment, MO
The P-type impurity region 14 is formed in advance in order to improve the punch-through breakdown voltage of the SFET. This 14
The depth of the region is set to be shallower than that of the N type low concentration drain region 5. As a result, the drain breakdown voltage could be improved to 24 V without increasing the drain-substrate capacitance.

【００２０】図５は、本発明の第４の実施例の絶縁ゲー
ト半導体装置の断面構造図である。本実施例では、ＭＯ
ＳＦＥＴのパンチスルー耐圧を向上させるために、Ｐ型
不純物領域１５を、あらかじめ部分的に形成している。
これにより、ドレイン−基板間の容量を全く増加させな
いで、ドレイン耐圧は２４Ｖに向上させることができ
た。FIG. 5 is a sectional structural view of an insulated gate semiconductor device according to the fourth embodiment of the present invention. In this embodiment, MO
In order to improve the punch through breakdown voltage of the SFET, the P-type impurity region 15 is partially formed in advance.
As a result, the drain breakdown voltage could be improved to 24V without increasing the drain-substrate capacitance at all.

【００２１】図７は、本発明の第５の実施例の絶縁ゲー
ト半導体装置の断面構造図である。本実施例では、ＭＯ
ＳＦＥＴのソース電極１０を表面より取り出す構造にし
ている。そして、ソース領域４をも前記絶縁物スペーサ
７’をマスクに形成している。その結果、ソース領域も
低面積化が図れ、集積度が向上した。FIG. 7 is a sectional structural view of an insulated gate semiconductor device according to the fifth embodiment of the present invention. In this embodiment, MO
The structure is such that the source electrode 10 of the SFET is taken out from the surface. The source region 4 is also formed by using the insulator spacer 7'as a mask. As a result, the area of the source region can be reduced and the degree of integration is improved.

【００２２】[0022]

【発明の効果】本発明によれば、ドレイン−基板間の容
量が低減できるので、ＭＯＳＦＥＴの高周波特性が格段
に向上するという効果がある。According to the present invention, the capacitance between the drain and the substrate can be reduced, so that there is an effect that the high frequency characteristics of the MOSFET are remarkably improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例の半導体装置の断面図で
ある。FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

【図２】図１の本発明の実施例の断面構造を作成するた
めの主要製造プロセスを示す断面構造図である。FIG. 2 is a sectional structural view showing a main manufacturing process for producing a sectional structure of the embodiment of the present invention in FIG.

【図３】本発明の第２の実施例の半導体装置の断面図で
ある。FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

【図４】本発明の第３の実施例の半導体装置の断面図で
ある。FIG. 4 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

【図５】本発明の第４の実施例の半導体装置の断面図で
ある。FIG. 5 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

【図６】図１の本発明の第１の実施例の特性を説明する
図である。FIG. 6 is a diagram illustrating characteristics of the first embodiment of the present invention in FIG.

【図７】本発明の第５の実施例の半導体装置である。FIG. 7 is a semiconductor device according to a fifth embodiment of the present invention.

【符号の説明】 １…Ｐ型高濃度半導体基板、２…Ｐ型半導体領域、３…
Ｐ型ベース領域、４…Ｎ型ソース領域、５…Ｎ型低濃度
ドレイン領域、６…Ｎ型低濃度ドレイン領域、７…絶縁
膜、７’…絶縁膜スペーサ、８…ゲート絶縁膜、９…ゲ
ート電極、１０…ソース電極、１１…ソース裏面電極、
１２…ドレイン電極、１３、１４、１５…Ｐ型低濃度ベ
ース領域。[Explanation of reference numerals] 1 ... P-type high-concentration semiconductor substrate, 2 ... P-type semiconductor region, 3 ...
P type base region, 4 ... N type source region, 5 ... N type low concentration drain region, 6 ... N type low concentration drain region, 7 ... Insulating film, 7 '... Insulating film spacer, 8 ... Gate insulating film, 9 ... Gate electrode, 10 ... Source electrode, 11 ... Source back surface electrode,
12 ... Drain electrode, 13, 14, 15 ... P type low concentration base region.

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】第１導電型の第１半導体領域上に第１導電
型の第２半導体領域を設け、半導体主面から前記第１半
導体領域に達するように形成した第１導電型の第３半導
体領域をベースとし、第２導電型の第４半導体領域をＭ
ＯＳＦＥＴのソースとし、前記第２半導体領域内に、第
２導電型の第５半導体領域並びに第２導電型の第６半導
体領域を、ゲート電極の端部側壁を覆うように形成した
絶縁物スペーサをマスクとして形成し、それらをドレイ
ンとしたことを特徴とする絶縁ゲート半導体装置。1. A first-conductivity-type third semiconductor formed so that a first-conductivity-type second semiconductor region is provided on a first-conductivity-type first semiconductor region so as to reach the first semiconductor region from a semiconductor main surface. Based on the semiconductor region, the second conductivity type fourth semiconductor region is M
An insulating material spacer, which is a source of the OSFET and has a second conductive type fifth semiconductor region and a second conductive type sixth semiconductor region formed in the second semiconductor region so as to cover the end sidewall of the gate electrode, is formed. An insulated gate semiconductor device, which is formed as a mask and is used as a drain. 【請求項２】前記ベースに接続され、前記ゲート電極の
ソース側端部側壁を覆うように形成した絶縁物スペーサ
をマスクとして形成した第１導電型の第７半導体領域を
設けたことを特徴とする請求項１記載の絶縁ゲート半導
体装置。2. A seventh semiconductor region of the first conductivity type is provided, which is connected to the base and is formed by using an insulating spacer formed so as to cover an end side wall of the source side of the gate electrode. The insulated gate semiconductor device according to claim 1. 【請求項３】前記第１導電型の第２半導体領域内に、前
記第５半導体領域より浅く第１導電型の第８半導体領域
を設けたことを特徴とする請求項１記載の絶縁ゲート半
導体装置。3. The insulated gate semiconductor according to claim 1, wherein an eighth semiconductor region of the first conductivity type is provided in the second semiconductor region of the first conductivity type so as to be shallower than the fifth semiconductor region. apparatus. 【請求項４】前記第４半導体領域と第５半導体領域との
間に第１導電型の第９半導体領域を設けたことを特徴と
する請求項１記載の絶縁ゲート半導体装置。4. The insulated gate semiconductor device according to claim 1, wherein a ninth semiconductor region of the first conductivity type is provided between the fourth semiconductor region and the fifth semiconductor region. 【請求項５】第１導電型の第２半導体領域上に形成した
ＭＯＳＦＥＴにおいて、ゲート電極の端部側壁を覆うよ
うに形成した絶縁物スペーサをマスクとして形成し、第
２導電型の第４半導体領域をソース、第５半導体領域並
びに第２導電型の第６半導体領域をドレインとしたこと
を特徴とする絶縁ゲート半導体装置。5. In a MOSFET formed on a second semiconductor region of the first conductivity type, an insulator spacer formed so as to cover an end side wall of a gate electrode is used as a mask to form a fourth semiconductor of the second conductivity type. An insulated gate semiconductor device, wherein the region is a source and the fifth semiconductor region and the second conductivity type sixth semiconductor region are drains.
JP27926091A 1991-10-25 1991-10-25 Insulating gate semiconductor device Pending JPH05121739A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27926091A JPH05121739A (en) 1991-10-25 1991-10-25 Insulating gate semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27926091A JPH05121739A (en) 1991-10-25 1991-10-25 Insulating gate semiconductor device

Publications (1)

Publication Number Publication Date
JPH05121739A true JPH05121739A (en) 1993-05-18

Family

ID=17608686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27926091A Pending JPH05121739A (en) 1991-10-25 1991-10-25 Insulating gate semiconductor device

Country Status (1)

Country Link
JP (1) JPH05121739A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5760440A (en) * 1995-02-21 1998-06-02 Fuji Electric Co., Ltd. Back-source MOSFET
US6552389B2 (en) 2000-12-14 2003-04-22 Kabushiki Kaisha Toshiba Offset-gate-type semiconductor device
US6864533B2 (en) 2000-09-11 2005-03-08 Kabushiki Kaisha Toshiba MOS field effect transistor with reduced on-resistance

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5760440A (en) * 1995-02-21 1998-06-02 Fuji Electric Co., Ltd. Back-source MOSFET
US6864533B2 (en) 2000-09-11 2005-03-08 Kabushiki Kaisha Toshiba MOS field effect transistor with reduced on-resistance
US6552389B2 (en) 2000-12-14 2003-04-22 Kabushiki Kaisha Toshiba Offset-gate-type semiconductor device
US7026214B2 (en) 2000-12-14 2006-04-11 Kabushiki Kaisha Toshiba Offset-gate-type semiconductor device
US7061060B2 (en) 2000-12-14 2006-06-13 Kabushiki Kaisha Toshiba Offset-gate-type semiconductor device

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