JPH05120125A - Data processor - Google Patents

Abstract

PURPOSE:To realize the data processor which can improve the processing throughput (average memory access speed) by succeeding conventional software and hardware to the utmost. CONSTITUTION:In addition to a main storage device 60, a high speed memory 12 for storing that which has higher access frequency in a program and data is provided. The high speed memory 12 is placed in the vicinity of a CPU 11 since a high speed is expected. In this case, an address space of the high speed memory 12 is formed as the same as a part of an address space of the main storage device 60. As for this overlap address space, the high speed memory 12 becomes effective. Therefore, this data processor is provided with a high speed memory access detecting circuit 14 for detecting an access of the overlap address space, and an access inhibiting circuit 23 for inhibiting an access of the main storage device 60 at the time of its detection.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a central processing unit (CPU).
Also, the present invention can be applied to an automatic exchange processing device, for example, regarding a data processing device including a main storage device.

[0002]

2. Description of the Related Art For example, an automatic exchange processing device, like a general data processing device, includes a main storage device for storing a program and data required for this program processing, and a large number of storage devices based on these programs and data. It is composed of a CPU for performing task processing. In such an automatic exchange processing device, an inexpensive and highly integrated dynamic RAM is generally used as a main memory device.

The processing capacity of the automatic exchange processing device is determined by the access time, since the device accesses and operates programs and data stored in the main storage device. Since thousands of tasks operate in real time in an automatic exchange processing device, there is a high demand for processing capacity, and higher processing capacity is required.

The following method has already been implemented as a method for further increasing the processing capacity of an automatic exchange processing device having a main memory device using a dynamic RAM.

(1) The memory constituting the main memory is changed to a high-speed memory (static RAM) to shorten the access time of the main memory.

(2) In response to one access request from the CPU, memory access at a plurality of consecutive addresses is started, and data is prepared prior to the next CPU access request. That is, the so-called interleave method is applied.

(3) A memory buffer (cache memory) that operates at high speed is provided inside or near the CPU, and programs and data that are frequently or repeatedly used are stored in this memory buffer. To process. That is, a so-called cache memory method is applied.

[0008]

However, each of the methods (1) to (3) described above has the following problems.

(1) High-speed memory device (static RA
Problems of the method using M) In general, static RAM has higher cost and lower integration rate than dynamic RAM. Therefore, if it is attempted to speed up all of the same amount of memory, more expensive parts will be used, and the cost and size of the automatic exchange processing apparatus will increase. In addition, there is a possibility that the number of mounting slots (slots for mounting the memory modules) allowed in the automatic exchange processing device cannot be realized. In such a case, it is necessary to change the device and the backboard, and the change to the high-speed memory device makes it impossible to inherit the existing configuration as it is.

Therefore, as shown in FIG. 2, it has been considered to apply a high speed memory to only a part of the memories. That is, as shown in FIG. 2A, for example, 32-bit C
A CPU package 1 equipped with a PU and four memory packages 2-5 are connected via a data bus having a data width of 16 bits, and one of the four memory packages 2-5 is connected.
A high-speed memory is mounted on each memory package 2, and a low-speed memory is mounted on the other memory packages 3 to 5. Here, the processing capacity as a whole is improved by storing programs and data that are frequently or repeatedly used in the high-speed memory. In this case, the address space is shown in FIG.
As shown in (B), the high-speed memory and the low-speed memory are connected continuously.

However, as described above, the integration rate of the static RAM, which is a high-speed memory, is different from that of the dynamic RAM, which is a low-speed memory.
It is practically impossible to construct the ideal address space shown in FIG. 7B, that is, the address space in which addresses are continuous.

That is, in reality, as shown in FIG. 2C, the address space for the high-speed memory is only a part of the address space for the memory package 2 in which the high-speed memory is mounted. Therefore, the continuity of the address space is lost. Here, in an apparatus having a basic program at a young address, the addresses viewed from the software become non-contiguous, and adopting such a new method impairs the inheritance of the software.

A 32-bit CPU is applied, and
Even if high-speed memory is applied, the data width of the system bus is 1
In the case of 6 bits, the memory is accessed with 16 bits, and the effect of increasing the speed of the memory is halved.

(2) Problems of the method applying the interleave method Since the command and data of the address next to the accessed address are also fetched, the hardware of the main storage device becomes large and the cost increases.

Further, since the interleaving method is greatly related to the continuity of the program processing, in an apparatus relating to a program such as an exchange processing program in which thousands of tasks are processed in real time (that is, addresses frequently jump), Processing capacity does not improve so much.

(3) Problem of the method applying the cache memory system When this system is applied, a high-speed circuit technology is required, and the replacement control of the information (instruction or data) in the cache memory and the associative control are required. It requires a configuration, requires large hardware, and increases costs.

Further, software-like control is required to guarantee the match between the contents on the cache memory and the contents on the main memory, and when this method is adopted for speeding up, the software You need to make changes and you cannot inherit existing software.

Further, since the cache memory system is also greatly related to the continuity of program processing, the processing capability is not so much improved in a device relating to a program such as an exchange processing program in which thousands of tasks are processed in real time.

As described above, the conventionally provided speed-up methods (1) to (3) inherit the software and hardware including the OS so as to minimize the increase in the cost of the device or to configure the device. It is not always appropriate when trying to prevent the increase in size.

Particularly, since the automatic exchange processing device has an automatic exchange processing program having many task switches, many inter-task communication, many programs commonly accessed by a plurality of tasks, etc. Even if the speed-up method is applied, the processing capacity does not improve so much.

The above-mentioned problem of the conventional method does not occur only in the case of the automatic exchange processing apparatus, but widely occurs in the data processing apparatus which executes a large number of task processes in response to a plurality of randomly generated processing requests. It is a thing.

The present invention has been made in consideration of the above points, and it is possible to inherit the software and hardware up to now as much as possible to minimize the cost increase and improve the processing capacity. An object of the present invention is to provide a data processing device that processes tasks in parallel.

[0023]

In order to solve such a problem, in the present invention, a main storage device for storing a program and data necessary for this program processing, and a random generation based on the program and the data. In the data processing device including the central processing unit that executes a large number of task processes according to the processing request, the following means are provided.

That is, in the vicinity of the central processing unit, a high-speed memory that operates at a higher speed than the memory constituting the main memory and is assigned the same address space as a part of the address space of the main memory. A high-speed memory access detection means for detecting an access to the high-speed memory and giving a detection signal to the main storage device, and accessing the main storage device when the detection signal is given from the high-speed memory access detection means. An access deterrent means to deter the operation is provided. Then, the high-speed memory stores the programs and data that are frequently accessed.

[0025]

When the speed is increased regardless of the cache memory method or the interleave method, the high speed memory is used. However, it is also possible to use all the memories constituting the main storage device as the high speed memory. There is a problem in that a part of the memory of the storage device is a high-speed memory as described above.

Therefore, a high-speed memory is provided separately from the main storage device. Since such a high-speed memory is arranged at a high speed, it is located near the central processing unit.

Considering inheritance of existing software, it is preferable that the address space viewed from the central processing unit is continuous. Therefore, the address space of the newly provided high-speed memory is also part of the existing address space. That is, it is part of the address space of the main memory. In this case, the main memory device and the high-speed memory naturally have a partial overlap of the address spaces, which causes a problem when the central processing unit accesses such an overlapped address space. Therefore, the high-speed memory is enabled for the duplicate address space, and high-speed memory access detection means for detecting access to such an address space is provided in association with the high-speed memory. The main memory is provided with access restraining means for restraining access to the device.

Even if the high-speed memory is provided, if the access to the high-speed memory is small, the significance (higher speed) of the provision is small, and therefore such a high-speed memory is frequently accessed in programs and data. I tried to store things.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an automatic exchange processing apparatus will be described in detail below with reference to the drawings.

FIG. 1 shows a data processing configuration in the automatic exchange processing apparatus according to this embodiment. In FIG. 1, a CPU package 10 is provided as a data processing configuration.
And a main storage device 60 composed of four (four for convenience of description) memory packages 20, 30, 40, and 50. Between the CPU package 10 and the main storage device 60, for example, 16 bits are provided. Width is connected via the system data bus.

The CPU package 10 includes a 32-bit C
A PU 11, a high speed memory (chip group) 12 and a high speed memory control circuit 13 are provided. The high speed memory 12 is, for example, a static RAM. The CPU 11 and the high-speed memory 12 are connected via an internal data bus having a data width of 32 bits, for example, and half of the internal data buses are connected to the system bus described above. The high-speed memory 12 stores fixed information (instruction code and data) used frequently or repeatedly as described later. The high speed memory control circuit 13 executes a known memory control operation for the high speed memory 12.

The capacity of the high speed memory 12 is smaller than the capacity of one memory package.

In the case of this embodiment, the CPU package 10
Further, a high-speed memory access detection circuit 14 is provided in association with the high-speed memory 12. The high-speed memory access detection circuit 14 monitors the access to the high-speed memory 12 by the CPU 11, and when detecting the access, outputs a main memory access inhibition signal to a signal line dedicated to the signal. For example, when the address output by the CPU 11 is within the address space of the high speed memory 12, the high speed memory access detection circuit 14
The main memory access inhibition signal is output. In the case of this example, the high-speed memory access detection circuit 14 can use the configuration in the high-speed memory control circuit 13 without being configured as a dedicated circuit.

Each memory package 20, 30, 40, 5
0 is a low-speed memory (chip group) 21, 31,
41, 51 and memory control circuits 22, 3 for these
2, 42, 52 are mounted. The low-speed memories 21, 31, 41, 51 mounted are, for example, dynamic RAMs. These low speed memories 21, 31, 41,
As will be described later, 51 stores an automatic exchange processing program (including data) other than that stored in the high-speed memory 12. Memory control circuits 22, 32,
Reference numerals 42 and 52 perform well-known memory control operations such as decoding addresses to generate various control signals and multiplexing into row addresses and column addresses.

In the case of this embodiment, a memory access inhibition circuit 23 is provided in the memory package 20 associated with the youngest address. Memory access inhibition circuit 23
Suppresses access to the low speed memory 21 of the memory package 20 when the main memory access prohibition signal is given from the high speed memory access detection circuit 14 described above. That is, the inhibition control signal is given to the memory control circuit 22 to inhibit it. Memory access suppression circuit 2
3 controls the memory control circuit 22 so as to prevent the row address strobe signal (RAS) and the column address strobe signal (CAS) applied to the memory elements in the low-speed memory 21 from becoming significant. Or
The memory access inhibition circuit 23 is, for example, the low-speed memory 2
Chip enable signal (C
The memory control circuit 22 is controlled so as to prevent E) and the output enable signal (OE) from becoming significant.

As described above, the CPU package 10 is provided with the high-speed memory access detection circuit 14 and the memory package 20 is provided with the memory access inhibition circuit 23. In this embodiment, the address of the high-speed memory 12 is set. This is because the space overlaps the partial address space of the low-speed memory 21.

FIG. 3 is an explanatory diagram showing an address space according to this embodiment. FIG. 3A shows an address space of the high speed memory 12, to which addresses AD1 to AD6 are assigned. FIG. 3B shows an address space of the main memory device 60. Addresses AD1 to AD2 are assigned to the memory package 20, and addresses AD2 + 1 (AD) to the memory package 30.
(Meaning the address next to 2) is assigned to the memory package 40, addresses AD3 + 1 to AD4 are assigned to the memory package 40, and addresses AD4 + 1 to AD5 are assigned to the memory package 50. Therefore, the space of addresses AD1 to AD6 of the memory package 20 is equal to the address space of the high speed memory 12.

Therefore, without providing any arbitration circuit,
When the CPU 11 tries to access an address in the address spaces AD1 to AD6, the high speed memory 12 and the memory package 20 operate simultaneously.
Therefore, when the CPU 11 attempts to access an address in the address spaces AD1 to AD6, the high speed memory access detection circuit 14 and the memory access inhibition circuit 23 are provided as described above so that only the high speed memory 12 operates effectively. Provided. Therefore, the address spaces AD1 to AD6 of the low-speed memory 21 are almost nonexistent, and the automatic exchange processing program is not stored.

Therefore, as shown in FIG. 3C, a part PG1 of the automatic exchange processing program (including data and OS) PG is stored in the high speed memory 12, and the remaining part PG2.
Is a space in which the address of the memory package 20 is AD6 + 1 to AD2 and other memory packages 30, 40, 50.
Stored in the address space of.

FIG. 4 is a conceptual diagram showing the structure of the automatic exchange processing program 70 which is distributed and stored in the high speed memory 12 and the low speed memories 21, 31, 41 and 51 in this way.

In FIG. 4, a plurality of user processes (hereinafter referred to as tasks) 710, ..., 71n are various tasks such as controlling a protocol of exchange processing and coping with failure detection. For example, a task corresponding to each stage of call processing such as a task activated when a call is detected or a task for controlling transmission to a central line is included. The task execution management program 72 manages the execution of tasks such as deciding the task to be executed at that time so that the call processing for a plurality of calls appears to the outside as if they are being executed in parallel in real time. Is. The interprocess communication control program 73 controls data transfer between tasks. Data is often passed from a task in one call processing stage to a task in the next call processing stage. The common library 74 stores various files related to the task interface.
The data and the like defining the method of data transfer between tasks are stored. The system common data 75 is basic data common to each task. The station data 76 is data such as the telephone number of the subscriber stored in the exchange. The database management program 77 manages this station data 76. The various pools 78 represent data stored in the working area by various tasks. The memory management program 79 is used for various pools 7.
It manages the storage and read-out to the storage device 8. The physical input / output control program 80 is for physically controlling an input / output device such as a serial port or a hard disk or a floppy disk. The virtual input / output control program 81 controls each task to perform input / output operations without being aware of the physical characteristics of the input / output device.

Of these parts, the capacity is small but the access frequency is high. For example, the task execution management program 72, the interprocess communication control program 73, the common library 74, the system common data 75, the database management program 77, the memory. The management program 79 and the virtual input / output control program 81 are stored in the high speed memory 12.

This is because the high-speed memory 12 is mounted in the same package 10 as the CPU 11 for speeding up and the capacity is limited, and the high-speed memory 12 is frequently accessed. This is to increase the processing capacity as a whole by storing in. Incidentally, the access ratio of the program portion stored in the high-speed memory 12 is about 30%, and the program portion is 10% or less of the entire program.

In the automatic exchange processing program 70 having the above-mentioned configuration, thousands of tasks operate in real time, and switching of tasks is frequently performed.
It has many features such as inter-task communication and many commonly accessed programs. Therefore, there is a demand for speeding up the memory access (improving the capability of the device) as described above.

In the automatic exchange processing apparatus having the above-mentioned configuration and storing the automatic exchange processing program 70 in the high-speed memory 12 and the main storage device 60 as described above, the CPU 11 accesses the high-speed memory 12. To do. At this time, the high speed memory 12 fetches an instruction command or data from the designated address and transfers it to the CPU 11. At this time, the high-speed memory access detection circuit 1
Reference numeral 4 detects an access to the high-speed memory 12 by the CPU 11 and outputs a main memory access inhibition signal to the main memory 60 via a signal line dedicated to the signal.
When the main memory access inhibition signal is given, the memory access inhibition circuit 23 in the first memory package 20 inhibits the CPU 11 from accessing the low speed memory 21 of this memory package 20. This allows
Only instruction commands and data read from the high speed memory 12 are transferred to the CPU 11 regardless of the operation of the main storage device 60.

Therefore, according to the above embodiment, the following effects can be obtained.

(1) Since the program part that is frequently accessed is stored in the high-speed memory for data processing,
The average speed of access is increased, and the processing capacity of the device can be improved. In particular, the automatic exchange processing device according to the embodiment executes a large number of task processes in response to randomly generated process requests, and conventionally, it was difficult to increase the speed. large.

For example, the access of the main memory device 60 is 16 bits as described above, and the access speed is about 6.
It is 00 ns. As for the capability on the high-speed memory 12, the access speed is 180 ns and 32-bit access is possible. In fact, the access to the high speed memory 12 is 6
0% is longword access (32-bit access)
Is.

Therefore, the access speed of the high-speed memory 12 is 3.3 as compared with the access of the main memory 60.
(= 600 ÷ 180) times better, and the number of bits per access is 1.6 (= (32 × 0.6 + 16 × 0.4) ÷
16) Double better. As a result, the capacity of the high-speed memory 12 is 5.3 times (= 3.3 × 1.6) that of the main memory 60.

Conventionally, since the program is stored only in the main memory device 60, its capability is equal to that of the main memory device 60. In the case of this embodiment, since the programs are distributed and stored in the high-speed memory 12 and the main storage device 60, the access frequency of these programs determines the capacity of the entire storage device. Actually, the access ratio of the program portion stored in the high speed memory 12 is about 30%.

Therefore, the high speed memory 12 having the capacity of 5.3 times that of the main memory 60 is accessed at a rate of 30% and the main memory 60 is accessed at a rate of 70%. Compared with the case where the program is stored only in the device 60, the access capability (data processing capability) is 2.
It is improved by 3 (= 5.3 × 0.3 + 1 × 0.7) times.

(2) Existing software can be inherited. That is, existing software can be used as high-speed memory 1
2 and the main storage device 60, and there is no need to change the program part. Further, unlike the cache memory method, the contents of the high-speed memory are not replaced, so a management program therefor is not necessary.

(3) Since the newly required components for speeding up the access are the high-speed memory 12 having a small capacity and the structure for avoiding the access conflict between the high-speed memory 12 and the main storage device 60, Few. Therefore, as described above, the high speed memory and the like can be mounted in the same package 10 as the CPU 11. Also, many hardware configurations can be used as they are. Incidentally, when the cache memory method or the like is adopted, the hardware for controlling the transfer from the main storage device to the cache memory is large.

(4) As described above, since the software is inherited and the number of additional elements of hardware is very small, even if the processing capacity of the device is improved, the cost increase is very small.

(5) As described above, since the continuity of the address space is guaranteed even if the programs are distributed to the high speed memory 12 and the main storage device 60, memory management and the like becomes easy.

Although the present invention is applied to the automatic exchange processing apparatus in the above-mentioned embodiment, the present invention is not limited to this, and it is possible to respond to processing requests that occur at random and frequently. It can be widely applied to a data processing device that executes a large number of task processes.

Further, the types of the high speed memory and the types of the low speed memory constituting the main memory are not limited to those of the above-mentioned embodiment.

[0058]

As described above, according to the present invention, a high speed memory to which the same address space as a part of the address space of the main memory is allocated is provided near the CPU, and
The high-speed memory stores the part of the program (including data) that is frequently accessed, and when the high-speed memory is accessed, the access operation of the main memory is suppressed, so the existing software and hardware can be used as much as possible. It is possible to realize a data processing device that inherits and has improved processing capability. This can be expected to minimize cost increase.

[Brief description of drawings]

FIG. 1 is a block diagram showing a data processing configuration according to an embodiment.

FIG. 2 is an explanatory diagram of a conventional speed-up method.

FIG. 3 is an explanatory diagram showing a structure of an address space according to an embodiment.

FIG. 4 is an explanatory diagram showing a configuration of a program (including data) stored in a memory of the embodiment.

[Explanation of symbols]

11 ... CPU (Central Processing Unit), 12 ... High-speed memory, 1
4 ... High-speed memory access detection circuit, 20, 30, 40,
50 ... Memory package, 23 ... Memory access inhibiting circuit, 60 ... Main memory device.

Claims (1)

[Claims] 1. A main memory device for storing a program and data necessary for processing the program, and a central processing unit for executing a large number of task processes in response to a plurality of randomly generated processing requests based on the program and the data. In a data processing device including a processing device, a memory that operates near the central processing device at a higher speed than a memory forming the main memory device, and is the same as a part of the address space of the main memory device. A high-speed memory to which an address space is assigned, and a high-speed memory access detection means for detecting an access to the high-speed memory and giving a detection signal to the main memory device are provided, and the high-speed memory access detection means is provided in the main memory device. When a detection signal is given from the access control means, access control means for controlling the access operation is provided, A data processing device, characterized in that a gram and data which are frequently accessed are stored.