JPH05129918A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To relax ringing in a power supply and GND level caused when output buffers are operated simultaneously in the output buffers in a semiconductor integrated circuit. CONSTITUTION:Several delay circuits D1-Dm whose delay time differs from each other are employed in terms of interposition for a control signal t0E controlling the state of output buffers BO-Bn as to whether they are to be brought into a high impedance state or not. Then the output buffers BO-Bn each having plural bits are controlled by using the control signals passing through the delay circuits D1-Dm and the control signal not through them. Thus, the output buffers BO-Bn each having plural bits are not simultaneously turned on, ringing in a power supply and GND level is relaxed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit, and more particularly to a circuit for mitigating ringing generated in a power supply and GND by the simultaneous operation of individual output buffers.

[0002]

2. Description of the Related Art An output buffer circuit in an IC for transmitting a signal to the outside of the IC is required to operate at high speed so that the output signal can rise and fall in a short time. Also,
Since the output buffer circuit outputs a signal to the outside of the IC at the same time as it operates at high speed, it is unavoidable to use a transistor having a high ability to carry a large current.

For this reason, in the output circuit, when the rising or falling of the output signal is accelerated and a large current is discharged, ringing occurs due to the inductance component of the lead frame and the wire, and the power source, G
The potential fluctuation value of ND becomes large.

The potential fluctuations of the power supply and GND may cause malfunction in each circuit in the IC. That is, in a general output buffer circuit, as a result of operating the output waveform at a steep rise or fall and flowing a large current, the potential fluctuations of the power supply and GND increase,
That is, it may adversely affect other circuits.

Further, the number of data buses, which are a batch processing unit of the CPU, tends to increase due to the progress of the CPU architecture, and in general, output buffers are often prepared for the data buses.

Now, the number of data buses is 8 (8 bits).
In such a case, the following description will be made with reference to FIG.

In FIG. 4, in the conventional circuit, the eight output buffer circuits B0 to B7 are connected to the power supply potential VC via the inductances L1 and L2 parasitic on the lead frame and the like.
It is connected to C and the GND potential GND. A signal t0E for controlling whether or not the output buffer is set to high impedance is applied to each of the output buffer circuits B0 to B7,
Outputs signals 00 to 07 outside the IC.

The calculated data is the signals DATA0 to DA.
The output buffers B0 to B7 are respectively input from TA7, and these output buffers output a large current I in response to the signal.
C Output to outside.

At this time, the signal t0E is the calculated signal D
Controls whether or not the ATAs 0 to 7 input to the output buffers B0 to B7 are output to the outside.

That is, as shown in the timing chart of FIG.
When the signal t0E is non-active, it is in a high impedance state and is electrically disconnected from the outside of the IC. When the signal t0E is active, data can be output to the outside.

By the way, the output data is the output buffer O0.
Everything from to O7

It is assumed that [0] is output.

Next, at t0E, a high impedance state is set, and the potential of the floating capacitance attached to the output buffers O0 to O7 is kept at 0V. Here, if the next output data is all about to output [1], when t0E becomes active, the output buffer causes a large current to flow from the power supply VCC to the floating capacitance in order to supply the charges to the floating capacitance.

At this time, as described above, the power source VCC causes ringing due to the inductance component of the lead frame or the like. Further, in the high impedance state of the output buffer, charges are stored in the floating capacitances connected to the output buffers O0 to O7, and the next output data is 8
all the bits

It is assumed that it is [0].

When the t0E signal is activated in this state, a large current flows from the stray capacitance to the GND in the IC, and
D causes ringing.

The value V of this potential fluctuation is V = -LdI / d
It is represented by t (I is current, t is time, L is inductance), and it can be seen that the larger the value of the current flowing at the moment, the larger the potential fluctuation value. That is, the larger the number of output buffers (a large current flows) and the more the output buffers operate at the same time, the larger the potential variation value V.

For the above reasons, there is a high possibility that ringing will occur in the power supply and GND especially in the mode in which the output buffers are simultaneously operated, such as the t0E mode.

[0017]

In the conventional output buffer having the t0E mode, since the output buffers operate simultaneously, a large current instantaneously flows in the power supply or GND. This momentary large current induces ringing in the power supply and GND, and there is a concern that the potential fluctuations of the power supply and GND may affect other circuits.

An object of the present invention is to solve the above problems and provide an output buffer circuit in which ringing is not induced in a power supply and GND.

[0019]

The structure of the output buffer circuit of the present invention comprises an output transistor group for transmitting a signal to the outside of a semiconductor integrated circuit, an output buffer group for individually controlling the output transistor group, and the output buffer group. It is characterized in that it is provided with means for inputting a signal for controlling whether or not to be in a high impedance state, and a delay circuit for shifting the timing of the signal.

[0020]

1 is a block diagram showing an output buffer circuit according to a first embodiment of the present invention.

In FIG. 1, the present embodiment is an output buffer group assuming that the number of output bits (bits) is 8 bits. The t0E signal that controls the output buffers B0 to B7 for each bit is t0E that has passed through the delay circuit D1.
There are a signal b and a signal a that is the original signal, and 4 bits (B0, B2, B4, 4) of the output buffer 8 bits are present.
B6) is controlled by the signal a, and the remaining 4 bits (B1, B
3, B5, B7) are controlled by the signal b. Other parts are the same as in FIG.

As shown in the timing diagram of FIG. 2, t0
When the E signal becomes active, the output buffers B0, B2, B4, B6 connected to the signal a first become operable, and the output buffers B1, B3, B5, B7 connected to the signal b operate after a delay. It becomes possible.

Therefore, as compared with the conventional circuit, the amount of current dI / dt flowing through the power source and GND instantaneously decreases, and the amount of potential fluctuation of the power source and GND accompanying it also decreases.

Although the case of 8 bits has been described above, it is obvious that the present invention is effective even if there is an output buffer of an arbitrary n bit (n is an arbitrary natural number).

FIG. 3 is a block diagram of the second embodiment of the present invention. In this embodiment, there are (n + 1) output buffers B0 to Bn, and m delay circuits D1 to Dm are prepared accordingly. This embodiment can be configured with an arbitrary number of bits and operates in the same way as in the case of FIG.

Further, in the first embodiment, one delay circuit is used for the t0E signal, and the output buffer is divided into two signals, a delayed signal and a delayed signal, and the output buffer is operated with a time difference of two times. Let

However, it is also possible to prepare m delay circuits (m is an arbitrary natural number) having different delay values as shown in FIG. 3 and operate the output buffers B0 to Bn with a time difference of two times or more using respective signals. It is possible.

[0028]

As described above, according to the present invention, the output buffer is controlled by the delayed signal and the non-delayed signal to alleviate the ringing of the power supply and the GND and to prevent the adverse effect (malfunction) of other circuits. The effect is that it can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an output buffer circuit according to a first embodiment of the present invention.

FIG. 2 is a timing diagram showing the operation of FIG.

FIG. 3 is a block diagram showing an output buffer circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional output buffer circuit.

5 is a block diagram showing the operation of FIG. 4. FIG.

[Explanation of symbols]

B0 to Bn Output buffer circuit D1 to Dm Delay circuit L1, L2 Inductance parasitic in lead frame etc. DATA0 to n Signal input from inside IC to output buffer O0 to O7 Signal output to outside IC t0E Output buffer high Signal to control whether to use impedance VCC Power supply potential GND GND potential

Claims (1)

[Claims] 1. An output transistor group for transmitting a signal to the outside of a semiconductor integrated circuit, an output buffer group for individually controlling these, and a signal for controlling whether or not the output buffer group is in a high impedance state are input. Means to do
An output buffer circuit, comprising: a delay circuit for shifting the timing of the signal.