JPH05128051A - Bus controller - Google Patents

Abstract

PURPOSE:To improve the using efficiency of a host bus by measuring the data transfer speed of a small computer system interface (SCSI) bus and permitting the generation of a data transfer request to a host system based upon the measured result and a signal indicating the volume of data stored in a data file in file out(FIFO). CONSTITUTION:This bus control device is provided with a data transfer speed measuring means 47 for the SCSI bus (not shown). An authorized signal generating means 48 permits the generation of a data transfer request to the host system (not shown) based upon the measured result of the means 47 and a signal indicating the volume of data stored in the data FIFO 46. Thus the data volume of the data FIFO 46 to the host system is changed in accordance with the data transfer speed. Namely when the FIFO 46 stores much data at a slow transfer speed as compared with a high speed, the data transfer request to the host system can be generated. Consequently continued and highly efficient data transfer can be attained on a host bus (not shown).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus controller, and more particularly to a SCSI (Small Computer System).
The present invention relates to a data transfer circuit on the host system side in a bus controller conforming to the Interface protocol.

[0002]

2. Description of the Related Art When a SCSI device such as a magnetic disk is connected to an arithmetic processing unit via a SCSI bus, a SCSI bus control unit is usually placed between the SCSI bus and the arithmetic processing unit.

A bus controller conforming to the SCSI protocol is a SCSI (Small Computer S).
control the transmission and reception of data to and from the system interface bus, and a data FIFO (First In Fires) between the SCSI bus and the host bus.
The transfer data is stored in (t out) and a data transfer request to the host system is generated according to the number of data in the data FIFO.

This SCSI bus controller has a function of controlling a control signal of the SCSI bus and a data transfer function of sending out data to the SCSI bus or receiving data on the SCSI bus.

FIG. 2 is a block diagram showing a general structure of such a SCSI bus controller and its peripherals. In FIG. 2, the SCSI bus controller 4 is connected to the host bus 7 and the SCSI bus 6 and controls the SCSI bus 6 and the data transfer between the SCSI bus 6 and the host bus 7.

When high speed is required for data processing on the host bus 7 side, DMA (Direct M) is generally used.
Since it is based on the memory access method, the DMA controller 2 functions to perform high-speed data exchange between the SCSI bus control device 4 and the memory 3.
When the DMA method is not used, the microprocessor 1 directly controls the data transfer between the SCSI bus controller 4 and the memory 3. The SCSI bus 6 is connected to the SCSI device 5.

FIG. 3 is a block diagram showing the internal configuration of the conventional SCSI bus control device 4 of FIG. In FIG.
Mainly on the main control unit 41, SCSI bus interface unit 44, host interface unit 42, data FIFO
O (First In First Out) 46, and transfer data is exchanged through the data FIFO 46.

To explain the specific operation, when the host system side receives data, the SCSI bus interface unit 44 first receives the REQ signal and the ACK signal input or output from the data transfer control unit 45. The above data is stored in the data FIFO 46. A signal indicating the amount of data in the data FIFO is input to the data transfer request control unit 43 in the host interface unit 42 to issue a data transfer request to the host system. That is, when a certain amount of data or more is accumulated in the data FIFO 46, a data transfer request is issued to the host system.

The host that received the data transfer request
The system reads the data in the data FIFO 46. A certain amount of data or more that generates a data transfer request is a value that is usually fixed by the circuit configuration, and is 1 to 2 bytes in order to fully utilize the capacity of the data FIFO 46. The data transfer request to the host system in the above description is DR in the case of the DMA method.
Q (DMA Request) signal,
In the case of the processor control system, it is a data transfer request bit in the register indicating the status.

Next, when transmitting data from the host system side, first, a signal indicating the amount of data in the data FIFO 46 is input to the data transfer request control unit 43 in the host interface unit 42, and data is transferred to the data FIFO 46. If there is space to store, a data transfer request is generated. The host system receiving the data transfer request writes the data in the data FIFO 46. This operation is repeated until a certain amount of data is stored in the data FIFO 46. That is, a data transfer request is issued to the host system until a certain amount of data is accumulated in the data FIFO 46.

In other words, when there is a certain amount of write space in the data FIFO 46, a data transfer request is issued to the host system. The write space above a certain level is a value fixed by a normal circuit configuration, and is 1 to 2 bytes in order to fully utilize the capacity of the data FIFO 46.

As described above, a data FIFO that normally issues a data transfer request to the host system.
The amount of data in 46 is fixed, but as another example, the amount of data can be switched in several stages by making the amount of data correspond to the data transfer capacity (reaction time for a data transfer request) on the host system side. There is.

However, in this case, since the register must be rewritten from the host system in order to switch, the host system must know the data transfer rate of the SCSI device 5 of the communication partner in advance and then Each time, the register needs to be rewritten each time, and the processing of the host system becomes very complicated.

Further, since it is necessary to rewrite the control program of the host system every time the connected SCSI device 5 is changed to one having a different transfer rate, this structure corresponds to the data transfer rate of the SCSI bus 6. Practically, it was very difficult to change the generation interval of the data transfer request to the host system.

[0015]

As described above, in the conventional general SCSI bus controller 4, the data F for issuing a data transfer request to the host system is generated.
The amount of data in the IFO 46 was constant. Therefore, when the system configuration is such that the host system services the data transfer request in a substantially constant time, the data amount in the data FIFO 46 becomes substantially constant.

That is, each time a data transfer on the SCSI bus side is performed once, a data transfer request is generated once on the host system side, and the generation interval of the data transfer rate on the host system side is SCSI. It depends on the data transfer rate on the bus side.

Generally, the data transfer speed difference of the SCSI device 5 is large, and the SCS having a speed difference of 10 to 20 times.
In many cases, the I devices 5 are connected to the same bus.
Further, when designing the SCSI bus control device 4, the S-speed which is the fastest among the SCSI devices 5 to be connected.
Data FIFO 46 to support CSI devices
The capacity of the data transfer system, such as the number of stages, is determined.

Therefore, when the data transfer rate of the SCSI device of the communication partner is fast, the interval of data transfer request generation on the host system side becomes narrow, but when the data transfer rate of the SCSI device is slow, the host system side. However, there is a problem in that the interval at which the data transfer request is generated is extended.

Considering the efficiency of use of the host bus, it is important that the data transfer on the host bus is performed consecutively a certain number of times, and the data transfer interval is opened so that the data transfer is performed sporadically. This means that a large amount of unnecessary time is required to acquire the right to use the bus, and the use efficiency of the host bus is reduced.

An object of the present invention is to solve the above problems and automatically optimize the generation interval of data transfer requests to the host system according to the data transfer speed of the SCSI bus without intervention of the host system. It is an object of the present invention to provide a bus control device which improves the usage efficiency of the host bus.

[0021]

The control device according to the present invention comprises a measuring means for measuring the data transfer rate of a SCSI bus, a host for outputting from the measuring means and a signal indicating the number of data in the data FIFO. And a permission signal generating means for generating a signal for permitting the generation of the data transfer request to the system, and changing the generation condition of the data transfer request to the host system according to the data transfer speed of the SCSI bus. It is characterized by

[0022]

FIG. 1 is a block diagram showing a SCSI bus controller according to an embodiment of the present invention, in which the host system side is D
An example according to the MA method is shown.

In FIG. 1, the SCSI bus control device of this embodiment has a data transfer rate measuring means 47 for measuring the data transfer rate of the SCSI bus by the data transfer control signal 101 output from the SCSI interface section 44.
And the output signal 102 of the data transfer rate measuring means 47
And a permission signal generating means 48 for generating a data transfer request permission signal 104 from the signal 103 indicating the number of data output from the data FIFO 46, and the data to the host system according to the data transfer speed of the SCSI bus. The transfer request generation interval is changed. The other blocks are the same as in FIG.

The data transfer rate measuring means 47 is a SCSI
The data transfer rate is calculated by measuring the time difference between the rising edges of the REQ signal and the ACK signal, which are signals 101 for controlling the data transfer of the bus. An example of the circuit of the data transfer rate measuring means 47 is shown in FIG.

In FIG. 4, three D-type flip-flops 53, an AND gate 54, and a counter 49 are shown. Here, the outputs T0, ..., T of the counter 49
n becomes the output signal 102.

In this circuit example, the RE output for the second time
The rising time difference between the Q signal and the ACK signal 101 is calculated by the counter 49, and the output of this counter 49 causes S
It represents the data transfer rate of the CSI bus. That is, if the data transfer rate is slow, the output value of the counter 49 becomes large, and if the data transfer rate is fast, the output value of the counter becomes small. The counter 49 and the D-type flip-flop 53 shown in FIG.

It is initialized to [0].

Next, referring to FIG. 5, the operation of the data transfer request permission signal generating means 48 and its peripherals in FIG. 1 will be described. In FIG. 5, a signal 103 indicating data in the data FIFO 46 is a signal that becomes active when a certain amount of data is stored in the data FIFO 46.
In the circuit example shown in FIG. 5, the capacity of the data FIFO 46 is set to 1
Byte x 8 stages, 9 signals in order, such as a signal indicating that the number of data in the data FIFO 46 is 0, a signal indicating 1 byte, and a signal indicating 2 height. It is output from the FIFO 46. These are selectors 50 in the permission signal generating means 48.
Is input as a selected signal. From these selected signals, two control signals are selected by the output signal 102 of the SCSI bus data transfer rate measuring means 47 described above.

These two control signals are received flip-flops.
It is connected to the set input of the flop 51 and the set input of the transmitting flip-flop 52. In addition, the reset input of the receiving flip-flop 51 has a data FIFO.
A signal indicating that 46 is empty (Empty) indicates that the reset input of the transmission flip-flop 52 is full of data FIFOs 46 (Ful).
1), the output of the receiving flip-flop 51 and the transmitting flip-flop 52 are input.
The two outputs of the
It is connected to the interface unit 42. These flips
The function of the flop causes the output of the receiving flip-flop 51 to be initialized to 0 at the time of reception, and then when the data is stored in the data FIFO 46 up to the reference value selected by the selector 50, the generation of a data transfer request is generated. Permit and continue in the permissive state until the data FIFO 46 is empty. As the reference value, a small value (for example, 1 or 2) is selected when the data transfer rate of the SCSI bus is high, and S
When the data transfer rate of the CSI bus is low, a large value (for example, 7 or 8) is selected.

At the time of transmission, first, a flip-flop for transmission
The output of the flop 52 is initialized to 1, that is, enabled, and data transfer on the host system side is started.
When all stages of the data FIFO 46 are filled by the data transfer, the transmission flip-flop 52 is reset and enters the prohibited state. After that, when the data in the data FIFO 46 is reduced to the reference value selected by the selector 50, the data is set again to be in the permit state, and the data transfer is restarted. A large value (for example, 7 or 8) is selected as the reference value when the data transfer speed of the SCSI bus is high, and a small value (for example, 1 or 2) is selected when the data transfer speed of the SCSI bus is low.

As a result, it becomes possible to change the generation interval of the data transfer request to the host system according to the data transfer speed of the SCSI bus, and the maximum data FIFO
Data of the capacity of O46 can be continuously transferred to the host system.

In the case of this embodiment, since continuous data transfer of up to 8 bytes is possible, the time spent for acquiring the right to use the host bus can be greatly reduced. Taking a commonly used DMA controller as an example, it takes two machine cycles (the minimum operation unit of the DMA controller) from the acquisition of the right to use the host bus to the actual start of data transfer. Per transfer,
It takes 3 machine cycles.

When data of 8 bytes is transferred as in the present embodiment, it takes 40 machine cycles to transfer data in a single-shot manner as in the prior art, but in the case of continuous transfer,
Since the time to acquire the bus after the second byte is unnecessary, 2
It only takes 6 machine cycles.

Therefore, the time during which the SCSI bus controller 4 occupies the host bus is greatly shortened, and the efficiency of use of the host bus can be improved.

Further, in this embodiment, the data transfer rate measuring means 47 and the permission signal generating means 48 are constituted by logic circuits, but the microprocessor is made to have the same function as in FIG.
It can be replaced as shown in.

In FIG. 6, the bus controller 4 of another embodiment of the present invention has a structure in which only two microprocessors 56 are replaced, and the other parts are the same as those of the embodiment of FIG. .. In this embodiment, finer control such as processing of fractional bytes becomes possible.

In FIG. 5, the data transfer request control unit 43, as shown in FIG. 5, is connected to the AND gate 54 which receives the reception mode, the transmission mode, and the Q outputs of the flip-flops 51 and 52, and ORs. Composed of gate 55, DR
Output EQ signal.

[0037]

As described above, the SC according to the present invention
With the SI bus controller, the host can be controlled according to the data transfer rate of the SCSI bus without the intervention of the host system.
The effect that the generation interval of the data transfer request to the system is automatically optimized, the unnecessary time for acquiring the right to use the bus is reduced, and the utilization efficiency of the host bus can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a bus control device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a SCSI bus control device and its periphery.

FIG. 3 is a block diagram showing an internal configuration of a conventional SCSI bus control device.

FIG. 4 is a block diagram showing an example of a data transfer rate measuring means of FIG.

5 is a block diagram showing an example of a permission signal generating means of FIG. 1. FIG.

FIG. 6 is a block diagram showing a bus controller according to another embodiment of the present invention.

[Explanation of symbols]

 1 Microprocessor 2 DMA Controller 3 Memory 4 SCSI Bus Control Device 5 SCSI Device 6 SCSI Bus 7 Host Bus 41 Main Control Unit 42 Host Interface Unit 43 Data Transfer Request Control Unit 44 SCSI Bus Interface Unit 45 Data Transfer Control Unit 46 Data FIFO 47 Data transfer rate measuring means 48 Permission signal generating means 49 Counter 50 Selector 51 Reception flip-flop 52 Transmission flip-flop 53 D-type flip-flop 54 AND gate 55 OR gate 56 Microprocessor 101 Data transfer control signal 102 output signal of measuring means 103 signal indicating the number of data in FIFO 104 data transfer request permission signal

Claims (2)

[Claims] 1. A method for controlling transmission and reception of data to and from a SCSI bus, storing transfer data in a data FIFO between the SCSI bus and a host bus, and storing the data F
In a bus controller that issues a data transfer request to a host system according to the number of data in the IFO, a measuring unit that measures the data transfer rate of the SCSI bus,
The data transfer of the SCSI bus is provided with a permission signal generating means for generating a signal for permitting generation of the data transfer request to the host system from the output of the measuring means and a signal indicating the number of data in the data FIFO. A bus controller characterized in that a condition for generating a data transfer request to the host system is changed according to a speed. 2. The measuring means comprises three D-type flip-flops, an AND gate, and a counter.
Bus control device as described.